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@@ -86,6 +86,15 @@ typedef int siginfo_t;
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# endif
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#endif
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#if defined(__OpenBSD__) || defined(__NetBSD__)
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# include <sys/param.h>
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# include <sys/sysctl.h>
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#endif
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#if defined(__DragonFly__)
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# include <sys/sysctl.h>
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#endif
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#ifdef __APPLE__
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# include <sys/sysctl.h>
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# include <mach/vm_statistics.h>
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@@ -133,6 +142,9 @@ typedef struct rlimit ResourceLimitType;
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#elif defined( __hpux )
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# include <sys/param.h>
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# include <sys/pstat.h>
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# if defined(KWSYS_SYS_HAS_MPCTL_H)
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# include <sys/mpctl.h>
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# endif
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#endif
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#ifdef __HAIKU__
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@@ -173,6 +185,87 @@ typedef struct rlimit ResourceLimitType;
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# endif
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#endif
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#if defined(_MSC_VER) && (_MSC_VER >= 1300) && !defined(_WIN64)
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#define USE_ASM_INSTRUCTIONS 1
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#else
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#define USE_ASM_INSTRUCTIONS 0
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#endif
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#if defined(_MSC_VER) && (_MSC_VER >= 1400)
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#include <intrin.h>
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#define USE_CPUID_INTRINSICS 1
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#else
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#define USE_CPUID_INTRINSICS 0
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#endif
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#if USE_ASM_INSTRUCTIONS || USE_CPUID_INTRINSICS
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# define USE_CPUID 1
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#else
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# define USE_CPUID 0
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#endif
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#if USE_CPUID
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#define CPUID_AWARE_COMPILER
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/**
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* call CPUID instruction
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*
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* Will return false if the instruction failed.
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*/
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static bool call_cpuid(int select, int result[4])
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{
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#if USE_CPUID_INTRINSICS
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__cpuid(result, select);
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return true;
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#else
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int tmp[4];
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// Use SEH to determine CPUID presence
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__try {
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_asm {
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#ifdef CPUID_AWARE_COMPILER
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; we must push/pop the registers <<CPUID>> writes to, as the
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; optimiser doesn't know about <<CPUID>>, and so doesn't expect
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; these registers to change.
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push eax
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push ebx
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push ecx
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push edx
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#endif
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; <<CPUID>>
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mov eax, select
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#ifdef CPUID_AWARE_COMPILER
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cpuid
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#else
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_asm _emit 0x0f
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_asm _emit 0xa2
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#endif
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mov tmp[0 * TYPE int], eax
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mov tmp[1 * TYPE int], ebx
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mov tmp[2 * TYPE int], ecx
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mov tmp[3 * TYPE int], edx
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#ifdef CPUID_AWARE_COMPILER
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pop edx
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pop ecx
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pop ebx
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pop eax
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#endif
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}
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}
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__except(1)
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{
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return false;
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}
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memcpy(result, tmp, sizeof(tmp));
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// The cpuid instruction succeeded.
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return true;
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#endif
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}
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#endif
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namespace KWSYS_NAMESPACE
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{
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template<typename T>
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@@ -336,13 +429,16 @@ protected:
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unsigned char LogicalCPUPerPhysicalCPU();
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unsigned char GetAPICId();
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unsigned int IsHyperThreadingSupported();
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LongLong GetCyclesDifference(DELAY_FUNC, unsigned int);
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static LongLong GetCyclesDifference(DELAY_FUNC, unsigned int);
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// For Linux and Cygwin, /proc/cpuinfo formats are slightly different
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int RetreiveInformationFromCpuInfoFile();
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bool RetreiveInformationFromCpuInfoFile();
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kwsys_stl::string ExtractValueFromCpuInfoFile(kwsys_stl::string buffer,
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const char* word, size_t init=0);
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bool QueryLinuxMemory();
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bool QueryCygwinMemory();
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static void Delay (unsigned int);
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static void DelayOverhead (unsigned int);
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@@ -367,8 +463,24 @@ protected:
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bool QueryQNXMemory();
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bool QueryQNXProcessor();
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//For OpenBSD, FreeBSD, NetBSD, DragonFly
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bool QueryBSDMemory();
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bool QueryBSDProcessor();
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//For HP-UX
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bool QueryHPUXMemory();
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bool QueryHPUXProcessor();
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//For Microsoft Windows
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bool QueryWindowsMemory();
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//For AIX
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bool QueryAIXMemory();
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bool QueryProcessor();
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// Evaluate the memory information.
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int QueryMemory();
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bool QueryMemory();
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size_t TotalVirtualMemory;
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size_t AvailableVirtualMemory;
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size_t TotalPhysicalMemory;
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@@ -695,24 +807,11 @@ void SystemInformation::RunMemoryCheck()
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// --------------------------------------------------------------
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// SystemInformationImplementation starts here
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#if defined(_MSC_VER) && (_MSC_VER >= 1300) && !defined(_WIN64)
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#define USE_ASM_INSTRUCTIONS 1
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#else
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#define USE_ASM_INSTRUCTIONS 0
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#endif
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#define STORE_TLBCACHE_INFO(x,y) x = (x < y) ? y : x
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#define TLBCACHE_INFO_UNITS (15)
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#define CLASSICAL_CPU_FREQ_LOOP 10000000
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#define RDTSC_INSTRUCTION _asm _emit 0x0f _asm _emit 0x31
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#define CPUID_AWARE_COMPILER
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#ifdef CPUID_AWARE_COMPILER
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#define CPUID_INSTRUCTION cpuid
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#else
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#define CPUID_INSTRUCTION _asm _emit 0x0f _asm _emit 0xa2
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#endif
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#define MMX_FEATURE 0x00000001
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#define MMX_PLUS_FEATURE 0x00000002
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#define SSE_FEATURE 0x00000004
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@@ -1189,8 +1288,14 @@ void SystemInformationImplementation::RunCPUCheck()
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this->QueryHaikuInfo();
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#elif defined(__QNX__)
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this->QueryQNXProcessor();
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#else
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#elif defined(__OpenBSD__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__DragonFly__)
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this->QueryBSDProcessor();
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#elif defined(__hpux)
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this->QueryHPUXProcessor();
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#elif defined(__linux) || defined(__CYGWIN__)
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this->RetreiveInformationFromCpuInfoFile();
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#else
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this->QueryProcessor();
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#endif
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}
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@@ -1209,6 +1314,18 @@ void SystemInformationImplementation::RunMemoryCheck()
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this->QueryHaikuInfo();
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#elif defined(__QNX__)
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this->QueryQNXMemory();
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#elif defined(__OpenBSD__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__DragonFly__)
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this->QueryBSDMemory();
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#elif defined(__CYGWIN__)
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this->QueryCygwinMemory();
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#elif defined(_WIN32)
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this->QueryWindowsMemory();
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#elif defined(__hpux)
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this->QueryHPUXMemory();
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#elif defined(__linux)
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this->QueryLinuxMemory();
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#elif defined(_AIX)
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this->QueryAIXMemory();
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#else
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this->QueryMemory();
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#endif
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@@ -1612,40 +1729,15 @@ void SystemInformationImplementation::Delay(unsigned int uiMS)
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bool SystemInformationImplementation::DoesCPUSupportCPUID()
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{
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#if USE_CPUID
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int dummy[4] = { 0, 0, 0, 0 };
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#if USE_ASM_INSTRUCTIONS
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// Use SEH to determine CPUID presence
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__try {
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_asm {
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#ifdef CPUID_AWARE_COMPILER
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; we must push/pop the registers <<CPUID>> writes to, as the
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; optimiser doesn't know about <<CPUID>>, and so doesn't expect
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; these registers to change.
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push eax
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push ebx
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push ecx
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push edx
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return call_cpuid(0, dummy);
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#else
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call_cpuid(0, dummy);
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return dummy[0] || dummy[1] || dummy[2] || dummy[3];
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#endif
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; <<CPUID>>
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mov eax, 0
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CPUID_INSTRUCTION
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#ifdef CPUID_AWARE_COMPILER
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pop edx
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pop ecx
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pop ebx
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pop eax
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#endif
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}
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}
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__except(1)
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{
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// Stop the class from trying to use CPUID again!
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return false;
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}
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// The cpuid instruction succeeded.
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return true;
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#else
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// Assume no cpuid instruction.
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return false;
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@@ -1655,58 +1747,29 @@ bool SystemInformationImplementation::DoesCPUSupportCPUID()
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bool SystemInformationImplementation::RetrieveCPUFeatures()
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{
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#if USE_ASM_INSTRUCTIONS
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int localCPUFeatures = 0;
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int localCPUAdvanced = 0;
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#if USE_CPUID
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int cpuinfo[4] = { 0, 0, 0, 0 };
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// Use assembly to detect CPUID information...
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__try {
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_asm {
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#ifdef CPUID_AWARE_COMPILER
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; we must push/pop the registers <<CPUID>> writes to, as the
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; optimiser doesn't know about <<CPUID>>, and so doesn't expect
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; these registers to change.
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push eax
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push ebx
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push ecx
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push edx
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#endif
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; <<CPUID>>
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; eax = 1 --> eax: CPU ID - bits 31..16 - unused, bits 15..12 - type, bits 11..8 - family, bits 7..4 - model, bits 3..0 - mask revision
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; ebx: 31..24 - default APIC ID, 23..16 - logical processor ID, 15..8 - CFLUSH chunk size , 7..0 - brand ID
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; edx: CPU feature flags
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mov eax,1
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CPUID_INSTRUCTION
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mov localCPUFeatures, edx
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mov localCPUAdvanced, ebx
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#ifdef CPUID_AWARE_COMPILER
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pop edx
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pop ecx
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pop ebx
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pop eax
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#endif
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}
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}
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__except(1)
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if (!call_cpuid(1, cpuinfo))
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{
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return false;
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}
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// Retrieve the features of CPU present.
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this->Features.HasFPU = ((localCPUFeatures & 0x00000001) != 0); // FPU Present --> Bit 0
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this->Features.HasTSC = ((localCPUFeatures & 0x00000010) != 0); // TSC Present --> Bit 4
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this->Features.HasAPIC = ((localCPUFeatures & 0x00000200) != 0); // APIC Present --> Bit 9
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this->Features.HasMTRR = ((localCPUFeatures & 0x00001000) != 0); // MTRR Present --> Bit 12
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this->Features.HasCMOV = ((localCPUFeatures & 0x00008000) != 0); // CMOV Present --> Bit 15
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this->Features.HasSerial = ((localCPUFeatures & 0x00040000) != 0); // Serial Present --> Bit 18
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this->Features.HasACPI = ((localCPUFeatures & 0x00400000) != 0); // ACPI Capable --> Bit 22
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this->Features.HasMMX = ((localCPUFeatures & 0x00800000) != 0); // MMX Present --> Bit 23
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this->Features.HasSSE = ((localCPUFeatures & 0x02000000) != 0); // SSE Present --> Bit 25
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this->Features.HasSSE2 = ((localCPUFeatures & 0x04000000) != 0); // SSE2 Present --> Bit 26
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this->Features.HasThermal = ((localCPUFeatures & 0x20000000) != 0); // Thermal Monitor Present --> Bit 29
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this->Features.HasIA64 = ((localCPUFeatures & 0x40000000) != 0); // IA64 Present --> Bit 30
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this->Features.HasFPU = ((cpuinfo[3] & 0x00000001) != 0); // FPU Present --> Bit 0
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this->Features.HasTSC = ((cpuinfo[3] & 0x00000010) != 0); // TSC Present --> Bit 4
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this->Features.HasAPIC = ((cpuinfo[3] & 0x00000200) != 0); // APIC Present --> Bit 9
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this->Features.HasMTRR = ((cpuinfo[3] & 0x00001000) != 0); // MTRR Present --> Bit 12
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this->Features.HasCMOV = ((cpuinfo[3] & 0x00008000) != 0); // CMOV Present --> Bit 15
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this->Features.HasSerial = ((cpuinfo[3] & 0x00040000) != 0); // Serial Present --> Bit 18
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this->Features.HasACPI = ((cpuinfo[3] & 0x00400000) != 0); // ACPI Capable --> Bit 22
|
|
|
|
|
this->Features.HasMMX = ((cpuinfo[3] & 0x00800000) != 0); // MMX Present --> Bit 23
|
|
|
|
|
this->Features.HasSSE = ((cpuinfo[3] & 0x02000000) != 0); // SSE Present --> Bit 25
|
|
|
|
|
this->Features.HasSSE2 = ((cpuinfo[3] & 0x04000000) != 0); // SSE2 Present --> Bit 26
|
|
|
|
|
this->Features.HasThermal = ((cpuinfo[3] & 0x20000000) != 0); // Thermal Monitor Present --> Bit 29
|
|
|
|
|
this->Features.HasIA64 = ((cpuinfo[3] & 0x40000000) != 0); // IA64 Present --> Bit 30
|
|
|
|
|
|
|
|
|
|
#if USE_ASM_INSTRUCTIONS
|
|
|
|
|
// Retrieve extended SSE capabilities if SSE is available.
|
|
|
|
|
if (this->Features.HasSSE) {
|
|
|
|
|
|
|
|
|
@@ -1735,17 +1798,20 @@ bool SystemInformationImplementation::RetrieveCPUFeatures()
|
|
|
|
|
// Set the advanced SSE capabilities to not available.
|
|
|
|
|
this->Features.HasSSEFP = false;
|
|
|
|
|
}
|
|
|
|
|
#else
|
|
|
|
|
this->Features.HasSSEFP = false;
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
// Retrieve Intel specific extended features.
|
|
|
|
|
if (this->ChipManufacturer == Intel)
|
|
|
|
|
{
|
|
|
|
|
this->Features.ExtendedFeatures.SupportsHyperthreading = ((localCPUFeatures & 0x10000000) != 0); // Intel specific: Hyperthreading --> Bit 28
|
|
|
|
|
this->Features.ExtendedFeatures.LogicalProcessorsPerPhysical = (this->Features.ExtendedFeatures.SupportsHyperthreading) ? ((localCPUAdvanced & 0x00FF0000) >> 16) : 1;
|
|
|
|
|
this->Features.ExtendedFeatures.SupportsHyperthreading = ((cpuinfo[3] & 0x10000000) != 0); // Intel specific: Hyperthreading --> Bit 28
|
|
|
|
|
this->Features.ExtendedFeatures.LogicalProcessorsPerPhysical = (this->Features.ExtendedFeatures.SupportsHyperthreading) ? ((cpuinfo[1] & 0x00FF0000) >> 16) : 1;
|
|
|
|
|
|
|
|
|
|
if ((this->Features.ExtendedFeatures.SupportsHyperthreading) && (this->Features.HasAPIC))
|
|
|
|
|
{
|
|
|
|
|
// Retrieve APIC information if there is one present.
|
|
|
|
|
this->Features.ExtendedFeatures.APIC_ID = ((localCPUAdvanced & 0xFF000000) >> 24);
|
|
|
|
|
this->Features.ExtendedFeatures.APIC_ID = ((cpuinfo[1] & 0xFF000000) >> 24);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
@@ -1773,6 +1839,7 @@ void SystemInformationImplementation::FindManufacturer(const kwsys_stl::string&
|
|
|
|
|
else if (this->ChipID.Vendor == "Geode By NSC") this->ChipManufacturer = NSC; // National Semiconductor
|
|
|
|
|
else if (this->ChipID.Vendor == "Sun") this->ChipManufacturer = Sun; // Sun Microelectronics
|
|
|
|
|
else if (this->ChipID.Vendor == "IBM") this->ChipManufacturer = IBM; // IBM Microelectronics
|
|
|
|
|
else if (this->ChipID.Vendor == "Hewlett-Packard") this->ChipManufacturer = HP; // Hewlett-Packard
|
|
|
|
|
else if (this->ChipID.Vendor == "Motorola") this->ChipManufacturer = Motorola; // Motorola Microelectronics
|
|
|
|
|
else if (family.substr(0, 7) == "PA-RISC") this->ChipManufacturer = HP; // Hewlett-Packard
|
|
|
|
|
else this->ChipManufacturer = UnknownManufacturer; // Unknown manufacturer
|
|
|
|
@@ -1782,71 +1849,41 @@ void SystemInformationImplementation::FindManufacturer(const kwsys_stl::string&
|
|
|
|
|
/** */
|
|
|
|
|
bool SystemInformationImplementation::RetrieveCPUIdentity()
|
|
|
|
|
{
|
|
|
|
|
#if USE_ASM_INSTRUCTIONS
|
|
|
|
|
int localCPUVendor[3];
|
|
|
|
|
int localCPUSignature;
|
|
|
|
|
#if USE_CPUID
|
|
|
|
|
int localCPUVendor[4];
|
|
|
|
|
int localCPUSignature[4];
|
|
|
|
|
|
|
|
|
|
// Use assembly to detect CPUID information...
|
|
|
|
|
__try
|
|
|
|
|
if (!call_cpuid(0, localCPUVendor))
|
|
|
|
|
{
|
|
|
|
|
_asm
|
|
|
|
|
{
|
|
|
|
|
#ifdef CPUID_AWARE_COMPILER
|
|
|
|
|
; we must push/pop the registers <<CPUID>> writes to, as the
|
|
|
|
|
; optimiser doesn't know about <<CPUID>>, and so doesn't expect
|
|
|
|
|
; these registers to change.
|
|
|
|
|
push eax
|
|
|
|
|
push ebx
|
|
|
|
|
push ecx
|
|
|
|
|
push edx
|
|
|
|
|
#endif
|
|
|
|
|
; <<CPUID>>
|
|
|
|
|
; eax = 0 --> eax: maximum value of CPUID instruction.
|
|
|
|
|
; ebx: part 1 of 3; CPU signature.
|
|
|
|
|
; edx: part 2 of 3; CPU signature.
|
|
|
|
|
; ecx: part 3 of 3; CPU signature.
|
|
|
|
|
mov eax, 0
|
|
|
|
|
CPUID_INSTRUCTION
|
|
|
|
|
mov localCPUVendor[0 * TYPE int], ebx
|
|
|
|
|
mov localCPUVendor[1 * TYPE int], edx
|
|
|
|
|
mov localCPUVendor[2 * TYPE int], ecx
|
|
|
|
|
|
|
|
|
|
; <<CPUID>>
|
|
|
|
|
; eax = 1 --> eax: CPU ID - bits 31..16 - unused, bits 15..12 - type, bits 11..8 - family, bits 7..4 - model, bits 3..0 - mask revision
|
|
|
|
|
; ebx: 31..24 - default APIC ID, 23..16 - logical processor ID, 15..8 - CFLUSH chunk size , 7..0 - brand ID
|
|
|
|
|
; edx: CPU feature flags
|
|
|
|
|
mov eax,1
|
|
|
|
|
CPUID_INSTRUCTION
|
|
|
|
|
mov localCPUSignature, eax
|
|
|
|
|
|
|
|
|
|
#ifdef CPUID_AWARE_COMPILER
|
|
|
|
|
pop edx
|
|
|
|
|
pop ecx
|
|
|
|
|
pop ebx
|
|
|
|
|
pop eax
|
|
|
|
|
#endif
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
__except(1)
|
|
|
|
|
if (!call_cpuid(1, localCPUSignature))
|
|
|
|
|
{
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Process the returned information.
|
|
|
|
|
// ; eax = 0 --> eax: maximum value of CPUID instruction.
|
|
|
|
|
// ; ebx: part 1 of 3; CPU signature.
|
|
|
|
|
// ; edx: part 2 of 3; CPU signature.
|
|
|
|
|
// ; ecx: part 3 of 3; CPU signature.
|
|
|
|
|
char vbuf[13];
|
|
|
|
|
memcpy (&(vbuf[0]), &(localCPUVendor[0]), sizeof (int));
|
|
|
|
|
memcpy (&(vbuf[4]), &(localCPUVendor[1]), sizeof (int));
|
|
|
|
|
memcpy (&(vbuf[0]), &(localCPUVendor[1]), sizeof (int));
|
|
|
|
|
memcpy (&(vbuf[4]), &(localCPUVendor[3]), sizeof (int));
|
|
|
|
|
memcpy (&(vbuf[8]), &(localCPUVendor[2]), sizeof (int));
|
|
|
|
|
vbuf[12] = '\0';
|
|
|
|
|
this->ChipID.Vendor = vbuf;
|
|
|
|
|
|
|
|
|
|
// Retrieve the family of CPU present.
|
|
|
|
|
this->ChipID.ExtendedFamily = ((localCPUSignature & 0x0FF00000) >> 20); // Bits 27..20 Used
|
|
|
|
|
this->ChipID.ExtendedModel = ((localCPUSignature & 0x000F0000) >> 16); // Bits 19..16 Used
|
|
|
|
|
this->ChipID.Type = ((localCPUSignature & 0x0000F000) >> 12); // Bits 15..12 Used
|
|
|
|
|
this->ChipID.Family = ((localCPUSignature & 0x00000F00) >> 8); // Bits 11..8 Used
|
|
|
|
|
this->ChipID.Model = ((localCPUSignature & 0x000000F0) >> 4); // Bits 7..4 Used
|
|
|
|
|
this->ChipID.Revision = ((localCPUSignature & 0x0000000F) >> 0); // Bits 3..0 Used
|
|
|
|
|
// ; eax = 1 --> eax: CPU ID - bits 31..16 - unused, bits 15..12 - type, bits 11..8 - family, bits 7..4 - model, bits 3..0 - mask revision
|
|
|
|
|
// ; ebx: 31..24 - default APIC ID, 23..16 - logical processor ID, 15..8 - CFLUSH chunk size , 7..0 - brand ID
|
|
|
|
|
// ; edx: CPU feature flags
|
|
|
|
|
this->ChipID.ExtendedFamily = ((localCPUSignature[0] & 0x0FF00000) >> 20); // Bits 27..20 Used
|
|
|
|
|
this->ChipID.ExtendedModel = ((localCPUSignature[0] & 0x000F0000) >> 16); // Bits 19..16 Used
|
|
|
|
|
this->ChipID.Type = ((localCPUSignature[0] & 0x0000F000) >> 12); // Bits 15..12 Used
|
|
|
|
|
this->ChipID.Family = ((localCPUSignature[0] & 0x00000F00) >> 8); // Bits 11..8 Used
|
|
|
|
|
this->ChipID.Model = ((localCPUSignature[0] & 0x000000F0) >> 4); // Bits 7..4 Used
|
|
|
|
|
this->ChipID.Revision = ((localCPUSignature[0] & 0x0000000F) >> 0); // Bits 3..0 Used
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
|
|
|
|
@@ -1859,48 +1896,14 @@ bool SystemInformationImplementation::RetrieveCPUIdentity()
|
|
|
|
|
/** */
|
|
|
|
|
bool SystemInformationImplementation::RetrieveCPUCacheDetails()
|
|
|
|
|
{
|
|
|
|
|
#if USE_ASM_INSTRUCTIONS
|
|
|
|
|
#if USE_CPUID
|
|
|
|
|
int L1Cache[4] = { 0, 0, 0, 0 };
|
|
|
|
|
int L2Cache[4] = { 0, 0, 0, 0 };
|
|
|
|
|
|
|
|
|
|
// Check to see if what we are about to do is supported...
|
|
|
|
|
if (RetrieveCPUExtendedLevelSupport (0x80000005))
|
|
|
|
|
{
|
|
|
|
|
// Use assembly to retrieve the L1 cache information ...
|
|
|
|
|
__try
|
|
|
|
|
{
|
|
|
|
|
_asm
|
|
|
|
|
{
|
|
|
|
|
#ifdef CPUID_AWARE_COMPILER
|
|
|
|
|
; we must push/pop the registers <<CPUID>> writes to, as the
|
|
|
|
|
; optimiser doesn't know about <<CPUID>>, and so doesn't expect
|
|
|
|
|
; these registers to change.
|
|
|
|
|
push eax
|
|
|
|
|
push ebx
|
|
|
|
|
push ecx
|
|
|
|
|
push edx
|
|
|
|
|
#endif
|
|
|
|
|
; <<CPUID>>
|
|
|
|
|
; eax = 0x80000005 --> eax: L1 cache information - Part 1 of 4.
|
|
|
|
|
; ebx: L1 cache information - Part 2 of 4.
|
|
|
|
|
; edx: L1 cache information - Part 3 of 4.
|
|
|
|
|
; ecx: L1 cache information - Part 4 of 4.
|
|
|
|
|
mov eax, 0x80000005
|
|
|
|
|
CPUID_INSTRUCTION
|
|
|
|
|
mov L1Cache[0 * TYPE int], eax
|
|
|
|
|
mov L1Cache[1 * TYPE int], ebx
|
|
|
|
|
mov L1Cache[2 * TYPE int], ecx
|
|
|
|
|
mov L1Cache[3 * TYPE int], edx
|
|
|
|
|
|
|
|
|
|
#ifdef CPUID_AWARE_COMPILER
|
|
|
|
|
pop edx
|
|
|
|
|
pop ecx
|
|
|
|
|
pop ebx
|
|
|
|
|
pop eax
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
__except(1)
|
|
|
|
|
if (!call_cpuid(0x80000005, L1Cache))
|
|
|
|
|
{
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
@@ -1917,41 +1920,7 @@ bool SystemInformationImplementation::RetrieveCPUCacheDetails()
|
|
|
|
|
// Check to see if what we are about to do is supported...
|
|
|
|
|
if (RetrieveCPUExtendedLevelSupport (0x80000006))
|
|
|
|
|
{
|
|
|
|
|
// Use assembly to retrieve the L2 cache information ...
|
|
|
|
|
__try
|
|
|
|
|
{
|
|
|
|
|
_asm
|
|
|
|
|
{
|
|
|
|
|
#ifdef CPUID_AWARE_COMPILER
|
|
|
|
|
; we must push/pop the registers <<CPUID>> writes to, as the
|
|
|
|
|
; optimiser doesn't know about <<CPUID>>, and so doesn't expect
|
|
|
|
|
; these registers to change.
|
|
|
|
|
push eax
|
|
|
|
|
push ebx
|
|
|
|
|
push ecx
|
|
|
|
|
push edx
|
|
|
|
|
#endif
|
|
|
|
|
; <<CPUID>>
|
|
|
|
|
; eax = 0x80000006 --> eax: L2 cache information - Part 1 of 4.
|
|
|
|
|
; ebx: L2 cache information - Part 2 of 4.
|
|
|
|
|
; edx: L2 cache information - Part 3 of 4.
|
|
|
|
|
; ecx: L2 cache information - Part 4 of 4.
|
|
|
|
|
mov eax, 0x80000006
|
|
|
|
|
CPUID_INSTRUCTION
|
|
|
|
|
mov L2Cache[0 * TYPE int], eax
|
|
|
|
|
mov L2Cache[1 * TYPE int], ebx
|
|
|
|
|
mov L2Cache[2 * TYPE int], ecx
|
|
|
|
|
mov L2Cache[3 * TYPE int], edx
|
|
|
|
|
|
|
|
|
|
#ifdef CPUID_AWARE_COMPILER
|
|
|
|
|
pop edx
|
|
|
|
|
pop ecx
|
|
|
|
|
pop ebx
|
|
|
|
|
pop eax
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
__except(1)
|
|
|
|
|
if (!call_cpuid(0x80000006, L2Cache))
|
|
|
|
|
{
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
@@ -1977,7 +1946,7 @@ bool SystemInformationImplementation::RetrieveCPUCacheDetails()
|
|
|
|
|
/** */
|
|
|
|
|
bool SystemInformationImplementation::RetrieveClassicalCPUCacheDetails()
|
|
|
|
|
{
|
|
|
|
|
#if USE_ASM_INSTRUCTIONS
|
|
|
|
|
#if USE_CPUID
|
|
|
|
|
int TLBCode = -1, TLBData = -1, L1Code = -1, L1Data = -1, L1Trace = -1, L2Unified = -1, L3Unified = -1;
|
|
|
|
|
int TLBCacheData[4] = { 0, 0, 0, 0 };
|
|
|
|
|
int TLBPassCounter = 0;
|
|
|
|
@@ -1985,39 +1954,7 @@ bool SystemInformationImplementation::RetrieveClassicalCPUCacheDetails()
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
do {
|
|
|
|
|
// Use assembly to retrieve the L2 cache information ...
|
|
|
|
|
__try {
|
|
|
|
|
_asm {
|
|
|
|
|
#ifdef CPUID_AWARE_COMPILER
|
|
|
|
|
; we must push/pop the registers <<CPUID>> writes to, as the
|
|
|
|
|
; optimiser doesn't know about <<CPUID>>, and so doesn't expect
|
|
|
|
|
; these registers to change.
|
|
|
|
|
push eax
|
|
|
|
|
push ebx
|
|
|
|
|
push ecx
|
|
|
|
|
push edx
|
|
|
|
|
#endif
|
|
|
|
|
; <<CPUID>>
|
|
|
|
|
; eax = 2 --> eax: TLB and cache information - Part 1 of 4.
|
|
|
|
|
; ebx: TLB and cache information - Part 2 of 4.
|
|
|
|
|
; ecx: TLB and cache information - Part 3 of 4.
|
|
|
|
|
; edx: TLB and cache information - Part 4 of 4.
|
|
|
|
|
mov eax, 2
|
|
|
|
|
CPUID_INSTRUCTION
|
|
|
|
|
mov TLBCacheData[0 * TYPE int], eax
|
|
|
|
|
mov TLBCacheData[1 * TYPE int], ebx
|
|
|
|
|
mov TLBCacheData[2 * TYPE int], ecx
|
|
|
|
|
mov TLBCacheData[3 * TYPE int], edx
|
|
|
|
|
|
|
|
|
|
#ifdef CPUID_AWARE_COMPILER
|
|
|
|
|
pop edx
|
|
|
|
|
pop ecx
|
|
|
|
|
pop ebx
|
|
|
|
|
pop eax
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
__except(1)
|
|
|
|
|
if (!call_cpuid(2, TLBCacheData))
|
|
|
|
|
{
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
@@ -2184,11 +2121,40 @@ bool SystemInformationImplementation::RetrieveCPUClockSpeed()
|
|
|
|
|
bool retrieved = false;
|
|
|
|
|
|
|
|
|
|
#if defined(_WIN32)
|
|
|
|
|
// First of all we check to see if the RDTSC (0x0F, 0x31) instruction is
|
|
|
|
|
// supported. If not, we fallback to trying to read this value from the
|
|
|
|
|
// registry:
|
|
|
|
|
//
|
|
|
|
|
if (!this->Features.HasTSC)
|
|
|
|
|
unsigned int uiRepetitions = 1;
|
|
|
|
|
unsigned int uiMSecPerRepetition = 50;
|
|
|
|
|
__int64 i64Total = 0;
|
|
|
|
|
__int64 i64Overhead = 0;
|
|
|
|
|
|
|
|
|
|
// Check if the TSC implementation works at all
|
|
|
|
|
if (this->Features.HasTSC &&
|
|
|
|
|
GetCyclesDifference(SystemInformationImplementation::Delay,
|
|
|
|
|
uiMSecPerRepetition) > 0)
|
|
|
|
|
{
|
|
|
|
|
for (unsigned int nCounter = 0; nCounter < uiRepetitions; nCounter ++)
|
|
|
|
|
{
|
|
|
|
|
i64Total += GetCyclesDifference (SystemInformationImplementation::Delay,
|
|
|
|
|
uiMSecPerRepetition);
|
|
|
|
|
i64Overhead +=
|
|
|
|
|
GetCyclesDifference (SystemInformationImplementation::DelayOverhead,
|
|
|
|
|
uiMSecPerRepetition);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Calculate the MHz speed.
|
|
|
|
|
i64Total -= i64Overhead;
|
|
|
|
|
i64Total /= uiRepetitions;
|
|
|
|
|
i64Total /= uiMSecPerRepetition;
|
|
|
|
|
i64Total /= 1000;
|
|
|
|
|
|
|
|
|
|
// Save the CPU speed.
|
|
|
|
|
this->CPUSpeedInMHz = (float) i64Total;
|
|
|
|
|
|
|
|
|
|
retrieved = true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// If RDTSC is not supported, we fallback to trying to read this value
|
|
|
|
|
// from the registry:
|
|
|
|
|
if (!retrieved)
|
|
|
|
|
{
|
|
|
|
|
HKEY hKey = NULL;
|
|
|
|
|
LONG err = RegOpenKeyEx(HKEY_LOCAL_MACHINE,
|
|
|
|
@@ -2213,34 +2179,7 @@ bool SystemInformationImplementation::RetrieveCPUClockSpeed()
|
|
|
|
|
RegCloseKey(hKey);
|
|
|
|
|
hKey = NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return retrieved;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
unsigned int uiRepetitions = 1;
|
|
|
|
|
unsigned int uiMSecPerRepetition = 50;
|
|
|
|
|
__int64 i64Total = 0;
|
|
|
|
|
__int64 i64Overhead = 0;
|
|
|
|
|
|
|
|
|
|
for (unsigned int nCounter = 0; nCounter < uiRepetitions; nCounter ++)
|
|
|
|
|
{
|
|
|
|
|
i64Total += GetCyclesDifference (SystemInformationImplementation::Delay,
|
|
|
|
|
uiMSecPerRepetition);
|
|
|
|
|
i64Overhead +=
|
|
|
|
|
GetCyclesDifference (SystemInformationImplementation::DelayOverhead,
|
|
|
|
|
uiMSecPerRepetition);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Calculate the MHz speed.
|
|
|
|
|
i64Total -= i64Overhead;
|
|
|
|
|
i64Total /= uiRepetitions;
|
|
|
|
|
i64Total /= uiMSecPerRepetition;
|
|
|
|
|
i64Total /= 1000;
|
|
|
|
|
|
|
|
|
|
// Save the CPU speed.
|
|
|
|
|
this->CPUSpeedInMHz = (float) i64Total;
|
|
|
|
|
|
|
|
|
|
retrieved = true;
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
return retrieved;
|
|
|
|
@@ -2312,7 +2251,7 @@ bool SystemInformationImplementation::RetrieveClassicalCPUClockSpeed()
|
|
|
|
|
/** */
|
|
|
|
|
bool SystemInformationImplementation::RetrieveCPUExtendedLevelSupport(int CPULevelToCheck)
|
|
|
|
|
{
|
|
|
|
|
int MaxCPUExtendedLevel = 0;
|
|
|
|
|
int cpuinfo[4] = { 0, 0, 0, 0 };
|
|
|
|
|
|
|
|
|
|
// The extended CPUID is supported by various vendors starting with the following CPU models:
|
|
|
|
|
//
|
|
|
|
@@ -2355,35 +2294,8 @@ bool SystemInformationImplementation::RetrieveCPUExtendedLevelSupport(int CPULev
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if USE_ASM_INSTRUCTIONS
|
|
|
|
|
|
|
|
|
|
// Use assembly to detect CPUID information...
|
|
|
|
|
__try {
|
|
|
|
|
_asm {
|
|
|
|
|
#ifdef CPUID_AWARE_COMPILER
|
|
|
|
|
; we must push/pop the registers <<CPUID>> writes to, as the
|
|
|
|
|
; optimiser doesn't know about <<CPUID>>, and so doesn't expect
|
|
|
|
|
; these registers to change.
|
|
|
|
|
push eax
|
|
|
|
|
push ebx
|
|
|
|
|
push ecx
|
|
|
|
|
push edx
|
|
|
|
|
#endif
|
|
|
|
|
; <<CPUID>>
|
|
|
|
|
; eax = 0x80000000 --> eax: maximum supported extended level
|
|
|
|
|
mov eax,0x80000000
|
|
|
|
|
CPUID_INSTRUCTION
|
|
|
|
|
mov MaxCPUExtendedLevel, eax
|
|
|
|
|
|
|
|
|
|
#ifdef CPUID_AWARE_COMPILER
|
|
|
|
|
pop edx
|
|
|
|
|
pop ecx
|
|
|
|
|
pop ebx
|
|
|
|
|
pop eax
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
__except(1)
|
|
|
|
|
#if USE_CPUID
|
|
|
|
|
if (!call_cpuid(0x80000000, cpuinfo))
|
|
|
|
|
{
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
@@ -2391,7 +2303,7 @@ bool SystemInformationImplementation::RetrieveCPUExtendedLevelSupport(int CPULev
|
|
|
|
|
|
|
|
|
|
// Now we have to check the level wanted vs level returned...
|
|
|
|
|
int nLevelWanted = (CPULevelToCheck & 0x7FFFFFFF);
|
|
|
|
|
int nLevelReturn = (MaxCPUExtendedLevel & 0x7FFFFFFF);
|
|
|
|
|
int nLevelReturn = (cpuinfo[0] & 0x7FFFFFFF);
|
|
|
|
|
|
|
|
|
|
// Check to see if the level provided is supported...
|
|
|
|
|
if (nLevelWanted > nLevelReturn)
|
|
|
|
@@ -2419,60 +2331,30 @@ bool SystemInformationImplementation::RetrieveExtendedCPUFeatures()
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if USE_ASM_INSTRUCTIONS
|
|
|
|
|
int localCPUExtendedFeatures = 0;
|
|
|
|
|
#if USE_CPUID
|
|
|
|
|
int localCPUExtendedFeatures[4] = { 0, 0, 0, 0 };
|
|
|
|
|
|
|
|
|
|
// Use assembly to detect CPUID information...
|
|
|
|
|
__try
|
|
|
|
|
{
|
|
|
|
|
_asm
|
|
|
|
|
{
|
|
|
|
|
#ifdef CPUID_AWARE_COMPILER
|
|
|
|
|
; we must push/pop the registers <<CPUID>> writes to, as the
|
|
|
|
|
; optimiser doesn't know about <<CPUID>>, and so doesn't expect
|
|
|
|
|
; these registers to change.
|
|
|
|
|
push eax
|
|
|
|
|
push ebx
|
|
|
|
|
push ecx
|
|
|
|
|
push edx
|
|
|
|
|
#endif
|
|
|
|
|
; <<CPUID>>
|
|
|
|
|
; eax = 0x80000001 --> eax: CPU ID - bits 31..16 - unused, bits 15..12 - type, bits 11..8 - family, bits 7..4 - model, bits 3..0 - mask revision
|
|
|
|
|
; ebx: 31..24 - default APIC ID, 23..16 - logical processor ID, 15..8 - CFLUSH chunk size , 7..0 - brand ID
|
|
|
|
|
; edx: CPU feature flags
|
|
|
|
|
mov eax,0x80000001
|
|
|
|
|
CPUID_INSTRUCTION
|
|
|
|
|
mov localCPUExtendedFeatures, edx
|
|
|
|
|
|
|
|
|
|
#ifdef CPUID_AWARE_COMPILER
|
|
|
|
|
pop edx
|
|
|
|
|
pop ecx
|
|
|
|
|
pop ebx
|
|
|
|
|
pop eax
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
__except(1)
|
|
|
|
|
if (!call_cpuid(0x80000001, localCPUExtendedFeatures))
|
|
|
|
|
{
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Retrieve the extended features of CPU present.
|
|
|
|
|
this->Features.ExtendedFeatures.Has3DNow = ((localCPUExtendedFeatures & 0x80000000) != 0); // 3DNow Present --> Bit 31.
|
|
|
|
|
this->Features.ExtendedFeatures.Has3DNowPlus = ((localCPUExtendedFeatures & 0x40000000) != 0); // 3DNow+ Present -- > Bit 30.
|
|
|
|
|
this->Features.ExtendedFeatures.HasSSEMMX = ((localCPUExtendedFeatures & 0x00400000) != 0); // SSE MMX Present --> Bit 22.
|
|
|
|
|
this->Features.ExtendedFeatures.SupportsMP = ((localCPUExtendedFeatures & 0x00080000) != 0); // MP Capable -- > Bit 19.
|
|
|
|
|
this->Features.ExtendedFeatures.Has3DNow = ((localCPUExtendedFeatures[3] & 0x80000000) != 0); // 3DNow Present --> Bit 31.
|
|
|
|
|
this->Features.ExtendedFeatures.Has3DNowPlus = ((localCPUExtendedFeatures[3] & 0x40000000) != 0); // 3DNow+ Present -- > Bit 30.
|
|
|
|
|
this->Features.ExtendedFeatures.HasSSEMMX = ((localCPUExtendedFeatures[3] & 0x00400000) != 0); // SSE MMX Present --> Bit 22.
|
|
|
|
|
this->Features.ExtendedFeatures.SupportsMP = ((localCPUExtendedFeatures[3] & 0x00080000) != 0); // MP Capable -- > Bit 19.
|
|
|
|
|
|
|
|
|
|
// Retrieve AMD specific extended features.
|
|
|
|
|
if (this->ChipManufacturer == AMD)
|
|
|
|
|
{
|
|
|
|
|
this->Features.ExtendedFeatures.HasMMXPlus = ((localCPUExtendedFeatures & 0x00400000) != 0); // AMD specific: MMX-SSE --> Bit 22
|
|
|
|
|
this->Features.ExtendedFeatures.HasMMXPlus = ((localCPUExtendedFeatures[3] & 0x00400000) != 0); // AMD specific: MMX-SSE --> Bit 22
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Retrieve Cyrix specific extended features.
|
|
|
|
|
if (this->ChipManufacturer == Cyrix)
|
|
|
|
|
{
|
|
|
|
|
this->Features.ExtendedFeatures.HasMMXPlus = ((localCPUExtendedFeatures & 0x01000000) != 0); // Cyrix specific: Extended MMX --> Bit 24
|
|
|
|
|
this->Features.ExtendedFeatures.HasMMXPlus = ((localCPUExtendedFeatures[3] & 0x01000000) != 0); // Cyrix specific: Extended MMX --> Bit 24
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
@@ -2492,51 +2374,20 @@ bool SystemInformationImplementation::RetrieveProcessorSerialNumber()
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if USE_ASM_INSTRUCTIONS
|
|
|
|
|
int SerialNumber[3];
|
|
|
|
|
#if USE_CPUID
|
|
|
|
|
int SerialNumber[4];
|
|
|
|
|
|
|
|
|
|
// Use assembly to detect CPUID information...
|
|
|
|
|
__try {
|
|
|
|
|
_asm {
|
|
|
|
|
#ifdef CPUID_AWARE_COMPILER
|
|
|
|
|
; we must push/pop the registers <<CPUID>> writes to, as the
|
|
|
|
|
; optimiser doesn't know about <<CPUID>>, and so doesn't expect
|
|
|
|
|
; these registers to change.
|
|
|
|
|
push eax
|
|
|
|
|
push ebx
|
|
|
|
|
push ecx
|
|
|
|
|
push edx
|
|
|
|
|
#endif
|
|
|
|
|
; <<CPUID>>
|
|
|
|
|
; eax = 3 --> ebx: top 32 bits are the processor signature bits --> NB: Transmeta only ?!?
|
|
|
|
|
; ecx: middle 32 bits are the processor signature bits
|
|
|
|
|
; edx: bottom 32 bits are the processor signature bits
|
|
|
|
|
mov eax, 3
|
|
|
|
|
CPUID_INSTRUCTION
|
|
|
|
|
mov SerialNumber[0 * TYPE int], ebx
|
|
|
|
|
mov SerialNumber[1 * TYPE int], ecx
|
|
|
|
|
mov SerialNumber[2 * TYPE int], edx
|
|
|
|
|
|
|
|
|
|
#ifdef CPUID_AWARE_COMPILER
|
|
|
|
|
pop edx
|
|
|
|
|
pop ecx
|
|
|
|
|
pop ebx
|
|
|
|
|
pop eax
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
__except(1)
|
|
|
|
|
if (!call_cpuid(3, SerialNumber))
|
|
|
|
|
{
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Process the returned information.
|
|
|
|
|
// ; eax = 3 --> ebx: top 32 bits are the processor signature bits --> NB: Transmeta only ?!?
|
|
|
|
|
// ; ecx: middle 32 bits are the processor signature bits
|
|
|
|
|
// ; edx: bottom 32 bits are the processor signature bits
|
|
|
|
|
char sn[128];
|
|
|
|
|
sprintf (sn, "%.2x%.2x-%.2x%.2x-%.2x%.2x-%.2x%.2x-%.2x%.2x-%.2x%.2x",
|
|
|
|
|
((SerialNumber[0] & 0xff000000) >> 24),
|
|
|
|
|
((SerialNumber[0] & 0x00ff0000) >> 16),
|
|
|
|
|
((SerialNumber[0] & 0x0000ff00) >> 8),
|
|
|
|
|
((SerialNumber[0] & 0x000000ff) >> 0),
|
|
|
|
|
((SerialNumber[1] & 0xff000000) >> 24),
|
|
|
|
|
((SerialNumber[1] & 0x00ff0000) >> 16),
|
|
|
|
|
((SerialNumber[1] & 0x0000ff00) >> 8),
|
|
|
|
@@ -2544,7 +2395,11 @@ bool SystemInformationImplementation::RetrieveProcessorSerialNumber()
|
|
|
|
|
((SerialNumber[2] & 0xff000000) >> 24),
|
|
|
|
|
((SerialNumber[2] & 0x00ff0000) >> 16),
|
|
|
|
|
((SerialNumber[2] & 0x0000ff00) >> 8),
|
|
|
|
|
((SerialNumber[2] & 0x000000ff) >> 0));
|
|
|
|
|
((SerialNumber[2] & 0x000000ff) >> 0),
|
|
|
|
|
((SerialNumber[3] & 0xff000000) >> 24),
|
|
|
|
|
((SerialNumber[3] & 0x00ff0000) >> 16),
|
|
|
|
|
((SerialNumber[3] & 0x0000ff00) >> 8),
|
|
|
|
|
((SerialNumber[3] & 0x000000ff) >> 0));
|
|
|
|
|
this->ChipID.SerialNumber = sn;
|
|
|
|
|
return true;
|
|
|
|
|
|
|
|
|
@@ -2566,45 +2421,18 @@ bool SystemInformationImplementation::RetrieveCPUPowerManagement()
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if USE_ASM_INSTRUCTIONS
|
|
|
|
|
int localCPUPowerManagement = 0;
|
|
|
|
|
#if USE_CPUID
|
|
|
|
|
int localCPUPowerManagement[4] = { 0, 0, 0, 0 };
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// Use assembly to detect CPUID information...
|
|
|
|
|
__try {
|
|
|
|
|
_asm {
|
|
|
|
|
#ifdef CPUID_AWARE_COMPILER
|
|
|
|
|
; we must push/pop the registers <<CPUID>> writes to, as the
|
|
|
|
|
; optimiser doesn't know about <<CPUID>>, and so doesn't expect
|
|
|
|
|
; these registers to change.
|
|
|
|
|
push eax
|
|
|
|
|
push ebx
|
|
|
|
|
push ecx
|
|
|
|
|
push edx
|
|
|
|
|
#endif
|
|
|
|
|
; <<CPUID>>
|
|
|
|
|
; eax = 0x80000007 --> edx: get processor power management
|
|
|
|
|
mov eax,0x80000007
|
|
|
|
|
CPUID_INSTRUCTION
|
|
|
|
|
mov localCPUPowerManagement, edx
|
|
|
|
|
|
|
|
|
|
#ifdef CPUID_AWARE_COMPILER
|
|
|
|
|
pop edx
|
|
|
|
|
pop ecx
|
|
|
|
|
pop ebx
|
|
|
|
|
pop eax
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
__except(1)
|
|
|
|
|
if (!call_cpuid(0x80000007, localCPUPowerManagement))
|
|
|
|
|
{
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Check for the power management capabilities of the CPU.
|
|
|
|
|
this->Features.ExtendedFeatures.PowerManagement.HasTempSenseDiode = ((localCPUPowerManagement & 0x00000001) != 0);
|
|
|
|
|
this->Features.ExtendedFeatures.PowerManagement.HasFrequencyID = ((localCPUPowerManagement & 0x00000002) != 0);
|
|
|
|
|
this->Features.ExtendedFeatures.PowerManagement.HasVoltageID = ((localCPUPowerManagement & 0x00000004) != 0);
|
|
|
|
|
this->Features.ExtendedFeatures.PowerManagement.HasTempSenseDiode = ((localCPUPowerManagement[3] & 0x00000001) != 0);
|
|
|
|
|
this->Features.ExtendedFeatures.PowerManagement.HasFrequencyID = ((localCPUPowerManagement[3] & 0x00000002) != 0);
|
|
|
|
|
this->Features.ExtendedFeatures.PowerManagement.HasVoltageID = ((localCPUPowerManagement[3] & 0x00000004) != 0);
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
|
|
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@@ -2634,57 +2462,18 @@ bool SystemInformationImplementation::RetrieveExtendedCPUIdentity()
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if (!RetrieveCPUExtendedLevelSupport(static_cast<int>(0x80000004)))
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return false;
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#if USE_ASM_INSTRUCTIONS
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#if USE_CPUID
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int CPUExtendedIdentity[12];
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// Use assembly to detect CPUID information...
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__try {
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_asm {
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#ifdef CPUID_AWARE_COMPILER
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; we must push/pop the registers <<CPUID>> writes to, as the
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; optimiser doesn't know about <<CPUID>>, and so doesn't expect
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; these registers to change.
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push eax
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push ebx
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push ecx
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push edx
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#endif
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; <<CPUID>>
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; eax = 0x80000002 --> eax, ebx, ecx, edx: get processor name string (part 1)
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mov eax,0x80000002
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CPUID_INSTRUCTION
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mov CPUExtendedIdentity[0 * TYPE int], eax
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mov CPUExtendedIdentity[1 * TYPE int], ebx
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mov CPUExtendedIdentity[2 * TYPE int], ecx
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mov CPUExtendedIdentity[3 * TYPE int], edx
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; <<CPUID>>
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; eax = 0x80000003 --> eax, ebx, ecx, edx: get processor name string (part 2)
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mov eax,0x80000003
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CPUID_INSTRUCTION
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mov CPUExtendedIdentity[4 * TYPE int], eax
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mov CPUExtendedIdentity[5 * TYPE int], ebx
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mov CPUExtendedIdentity[6 * TYPE int], ecx
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mov CPUExtendedIdentity[7 * TYPE int], edx
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; <<CPUID>>
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; eax = 0x80000004 --> eax, ebx, ecx, edx: get processor name string (part 3)
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mov eax,0x80000004
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CPUID_INSTRUCTION
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mov CPUExtendedIdentity[8 * TYPE int], eax
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mov CPUExtendedIdentity[9 * TYPE int], ebx
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mov CPUExtendedIdentity[10 * TYPE int], ecx
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mov CPUExtendedIdentity[11 * TYPE int], edx
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#ifdef CPUID_AWARE_COMPILER
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pop edx
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pop ecx
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pop ebx
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pop eax
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#endif
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if (!call_cpuid(0x80000002, CPUExtendedIdentity))
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{
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return false;
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}
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}
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__except(1)
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if (!call_cpuid(0x80000003, CPUExtendedIdentity + 4))
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{
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return false;
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}
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if (!call_cpuid(0x80000004, CPUExtendedIdentity + 8))
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{
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return false;
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}
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@@ -3022,7 +2811,7 @@ kwsys_stl::string SystemInformationImplementation::ExtractValueFromCpuInfoFile(k
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}
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/** Query for the cpu status */
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int SystemInformationImplementation::RetreiveInformationFromCpuInfoFile()
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bool SystemInformationImplementation::RetreiveInformationFromCpuInfoFile()
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{
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this->NumberOfLogicalCPU = 0;
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this->NumberOfPhysicalCPU = 0;
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@@ -3032,7 +2821,7 @@ int SystemInformationImplementation::RetreiveInformationFromCpuInfoFile()
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if ( !fd )
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{
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kwsys_ios::cout << "Problem opening /proc/cpuinfo" << kwsys_ios::endl;
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return 0;
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return false;
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}
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size_t fileSize = 0;
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@@ -3171,7 +2960,79 @@ int SystemInformationImplementation::RetreiveInformationFromCpuInfoFile()
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this->Features.L1CacheSize += atoi(cacheSize.c_str());
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}
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}
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return 1;
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// processor feature flags (probably x86 specific)
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kwsys_stl::string cpuflags = this->ExtractValueFromCpuInfoFile(buffer,"flags");
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if(!cpurev.empty())
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{
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// now we can match every flags as space + flag + space
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cpuflags = " " + cpuflags + " ";
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if ((cpuflags.find(" fpu ")!=kwsys_stl::string::npos))
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{
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this->Features.HasFPU = true;
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}
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if ((cpuflags.find(" tsc ")!=kwsys_stl::string::npos))
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{
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this->Features.HasTSC = true;
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}
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if ((cpuflags.find(" mmx ")!=kwsys_stl::string::npos))
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{
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this->Features.HasMMX = true;
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}
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if ((cpuflags.find(" sse ")!=kwsys_stl::string::npos))
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{
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this->Features.HasSSE = true;
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}
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if ((cpuflags.find(" sse2 ")!=kwsys_stl::string::npos))
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{
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this->Features.HasSSE2 = true;
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}
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if ((cpuflags.find(" apic ")!=kwsys_stl::string::npos))
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{
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this->Features.HasAPIC = true;
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}
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if ((cpuflags.find(" cmov ")!=kwsys_stl::string::npos))
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{
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this->Features.HasCMOV = true;
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}
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if ((cpuflags.find(" mtrr ")!=kwsys_stl::string::npos))
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{
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this->Features.HasMTRR = true;
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}
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if ((cpuflags.find(" acpi ")!=kwsys_stl::string::npos))
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{
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this->Features.HasACPI = true;
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}
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if ((cpuflags.find(" 3dnow ")!=kwsys_stl::string::npos))
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{
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this->Features.ExtendedFeatures.Has3DNow = true;
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}
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}
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return true;
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}
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bool SystemInformationImplementation::QueryProcessor()
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{
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#if defined(_SC_NPROC_ONLN) && !defined(_SC_NPROCESSORS_ONLN)
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// IRIX names this slightly different
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# define _SC_NPROCESSORS_ONLN _SC_NPROC_ONLN
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#endif
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#ifdef _SC_NPROCESSORS_ONLN
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long c = sysconf(_SC_NPROCESSORS_ONLN);
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if (c <= 0)
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{
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return false;
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}
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this->NumberOfPhysicalCPU = c;
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this->NumberOfLogicalCPU = this->NumberOfPhysicalCPU;
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return true;
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#else
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return false;
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#endif
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}
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/**
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@@ -3501,16 +3362,9 @@ void SystemInformationImplementation::SetStackTraceOnError(int enable)
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#endif
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}
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/** Query for the memory status */
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int SystemInformationImplementation::QueryMemory()
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bool SystemInformationImplementation::QueryWindowsMemory()
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{
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this->TotalVirtualMemory = 0;
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this->TotalPhysicalMemory = 0;
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this->AvailableVirtualMemory = 0;
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this->AvailablePhysicalMemory = 0;
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#ifdef __CYGWIN__
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return 0;
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#elif defined(_WIN32)
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#if defined(_WIN32)
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# if defined(_MSC_VER) && _MSC_VER < 1300
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MEMORYSTATUS ms;
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unsigned long tv, tp, av, ap;
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@@ -3535,8 +3389,15 @@ int SystemInformationImplementation::QueryMemory()
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this->TotalPhysicalMemory = tp>>10>>10;
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this->AvailableVirtualMemory = av>>10>>10;
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this->AvailablePhysicalMemory = ap>>10>>10;
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return 1;
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#elif defined(__linux)
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return true;
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#else
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return false;
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#endif
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}
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bool SystemInformationImplementation::QueryLinuxMemory()
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{
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#if defined(__linux)
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unsigned long tv=0;
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unsigned long tp=0;
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unsigned long av=0;
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@@ -3553,7 +3414,7 @@ int SystemInformationImplementation::QueryMemory()
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if( errorFlag!=0 )
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{
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kwsys_ios::cout << "Problem calling uname(): " << strerror(errno) << kwsys_ios::endl;
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return 0;
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return false;
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}
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if( unameInfo.release!=0 && strlen(unameInfo.release)>=3 )
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@@ -3577,7 +3438,7 @@ int SystemInformationImplementation::QueryMemory()
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if ( !fd )
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{
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kwsys_ios::cout << "Problem opening /proc/meminfo" << kwsys_ios::endl;
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return 0;
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return false;
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}
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if( linuxMajor>=3 || ( (linuxMajor>=2) && (linuxMinor>=6) ) )
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@@ -3616,7 +3477,7 @@ int SystemInformationImplementation::QueryMemory()
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{
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kwsys_ios::cout << "Problem parsing /proc/meminfo" << kwsys_ios::endl;
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fclose(fd);
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return 0;
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return false;
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}
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}
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else
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@@ -3648,39 +3509,87 @@ int SystemInformationImplementation::QueryMemory()
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{
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kwsys_ios::cout << "Problem parsing /proc/meminfo" << kwsys_ios::endl;
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fclose(fd);
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return 0;
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return false;
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}
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}
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fclose( fd );
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return 1;
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#elif defined(__hpux)
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unsigned long tv=0;
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unsigned long tp=0;
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unsigned long av=0;
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unsigned long ap=0;
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struct pst_static pst;
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struct pst_dynamic pdy;
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unsigned long ps = 0;
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if (pstat_getstatic(&pst, sizeof(pst), (size_t) 1, 0) != -1)
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{
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ps = pst.page_size;
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tp = pst.physical_memory *ps;
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tv = (pst.physical_memory + pst.pst_maxmem) * ps;
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if (pstat_getdynamic(&pdy, sizeof(pdy), (size_t) 1, 0) != -1)
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{
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ap = tp - pdy.psd_rm * ps;
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av = tv - pdy.psd_vm;
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this->TotalVirtualMemory = tv>>10>>10;
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this->TotalPhysicalMemory = tp>>10>>10;
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this->AvailableVirtualMemory = av>>10>>10;
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this->AvailablePhysicalMemory = ap>>10>>10;
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return 1;
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}
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}
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return 0;
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return true;
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#else
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return 0;
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return false;
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#endif
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}
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bool SystemInformationImplementation::QueryCygwinMemory()
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{
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#ifdef __CYGWIN__
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// _SC_PAGE_SIZE does return the mmap() granularity on Cygwin,
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// see http://cygwin.com/ml/cygwin/2006-06/msg00350.html
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// Therefore just use 4096 as the page size of Windows.
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long m = sysconf(_SC_PHYS_PAGES);
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if (m < 0)
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{
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return false;
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}
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this->TotalPhysicalMemory = m >> 8;
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return true;
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#else
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return false;
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#endif
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}
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bool SystemInformationImplementation::QueryAIXMemory()
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{
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#if defined(_AIX)
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long c = sysconf(_SC_AIX_REALMEM);
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if (c <= 0)
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{
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return false;
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}
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this->TotalPhysicalMemory = c / 1024;
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return true;
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#else
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return false;
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#endif
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}
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/** Query for the memory status */
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bool SystemInformationImplementation::QueryMemory()
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{
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#if defined(_SC_PHYS_PAGES) && defined(_SC_PAGESIZE)
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// Assume the mmap() granularity as returned by _SC_PAGESIZE is also
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// the system page size. The only known system where this isn't true
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// is Cygwin.
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long p = sysconf(_SC_PHYS_PAGES);
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long m = sysconf(_SC_PAGESIZE);
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if (p < 0 || m < 0)
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{
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return false;
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}
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// assume pagesize is a power of 2 and smaller 1 MiB
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size_t pagediv = (1024 * 1024 / m);
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this->TotalPhysicalMemory = p;
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this->TotalPhysicalMemory /= pagediv;
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#if defined(_SC_AVPHYS_PAGES)
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p = sysconf(_SC_AVPHYS_PAGES);
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if (p < 0)
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{
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return false;
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|
}
|
|
|
|
|
|
|
|
|
|
this->AvailablePhysicalMemory = p;
|
|
|
|
|
this->AvailablePhysicalMemory /= pagediv;
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
#else
|
|
|
|
|
return false;
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
@@ -3712,7 +3621,15 @@ SystemInformation::LongLong
|
|
|
|
|
SystemInformationImplementation::GetCyclesDifference (DELAY_FUNC DelayFunction,
|
|
|
|
|
unsigned int uiParameter)
|
|
|
|
|
{
|
|
|
|
|
#if USE_ASM_INSTRUCTIONS
|
|
|
|
|
#if defined(_MSC_VER) && (_MSC_VER >= 1400)
|
|
|
|
|
unsigned __int64 stamp1, stamp2;
|
|
|
|
|
|
|
|
|
|
stamp1 = __rdtsc();
|
|
|
|
|
DelayFunction(uiParameter);
|
|
|
|
|
stamp2 = __rdtsc();
|
|
|
|
|
|
|
|
|
|
return stamp2 - stamp1;
|
|
|
|
|
#elif USE_ASM_INSTRUCTIONS
|
|
|
|
|
|
|
|
|
|
unsigned int edx1, eax1;
|
|
|
|
|
unsigned int edx2, eax2;
|
|
|
|
@@ -3794,20 +3711,15 @@ unsigned char SystemInformationImplementation::LogicalCPUPerPhysicalCPU(void)
|
|
|
|
|
}
|
|
|
|
|
return static_cast<unsigned char>(cores_per_package);
|
|
|
|
|
#else
|
|
|
|
|
unsigned int Regebx = 0;
|
|
|
|
|
#if USE_ASM_INSTRUCTIONS
|
|
|
|
|
int Regs[4] = { 0, 0, 0, 0 };
|
|
|
|
|
#if USE_CPUID
|
|
|
|
|
if (!this->IsHyperThreadingSupported())
|
|
|
|
|
{
|
|
|
|
|
return static_cast<unsigned char>(1); // HT not supported
|
|
|
|
|
}
|
|
|
|
|
__asm
|
|
|
|
|
{
|
|
|
|
|
mov eax, 1
|
|
|
|
|
cpuid
|
|
|
|
|
mov Regebx, ebx
|
|
|
|
|
}
|
|
|
|
|
call_cpuid(1, Regs);
|
|
|
|
|
#endif
|
|
|
|
|
return static_cast<unsigned char> ((Regebx & NUM_LOGICAL_BITS) >> 16);
|
|
|
|
|
return static_cast<unsigned char> ((Regs[1] & NUM_LOGICAL_BITS) >> 16);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
@@ -3815,40 +3727,30 @@ unsigned char SystemInformationImplementation::LogicalCPUPerPhysicalCPU(void)
|
|
|
|
|
/** Works only for windows */
|
|
|
|
|
unsigned int SystemInformationImplementation::IsHyperThreadingSupported()
|
|
|
|
|
{
|
|
|
|
|
#if USE_ASM_INSTRUCTIONS
|
|
|
|
|
unsigned int Regedx = 0,
|
|
|
|
|
Regeax = 0,
|
|
|
|
|
VendorId[3] = {0, 0, 0};
|
|
|
|
|
__try // Verify cpuid instruction is supported
|
|
|
|
|
#if USE_CPUID
|
|
|
|
|
int Regs[4] = { 0, 0, 0, 0 },
|
|
|
|
|
VendorId[4] = { 0, 0, 0, 0 };
|
|
|
|
|
// Get vendor id string
|
|
|
|
|
if (!call_cpuid(0, VendorId))
|
|
|
|
|
{
|
|
|
|
|
__asm
|
|
|
|
|
{
|
|
|
|
|
xor eax, eax // call cpuid with eax = 0
|
|
|
|
|
cpuid // Get vendor id string
|
|
|
|
|
mov VendorId, ebx
|
|
|
|
|
mov VendorId + 4, edx
|
|
|
|
|
mov VendorId + 8, ecx
|
|
|
|
|
|
|
|
|
|
mov eax, 1 // call cpuid with eax = 1
|
|
|
|
|
cpuid
|
|
|
|
|
mov Regeax, eax // eax contains family processor type
|
|
|
|
|
mov Regedx, edx // edx has info about the availability of hyper-Threading
|
|
|
|
|
}
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
__except (EXCEPTION_EXECUTE_HANDLER)
|
|
|
|
|
// eax contains family processor type
|
|
|
|
|
// edx has info about the availability of hyper-Threading
|
|
|
|
|
if (!call_cpuid(1, Regs))
|
|
|
|
|
{
|
|
|
|
|
return(0); // cpuid is unavailable
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (((Regeax & FAMILY_ID) == PENTIUM4_ID) || (Regeax & EXT_FAMILY_ID))
|
|
|
|
|
if (((Regs[0] & FAMILY_ID) == PENTIUM4_ID) || (Regs[0] & EXT_FAMILY_ID))
|
|
|
|
|
{
|
|
|
|
|
if (VendorId[0] == 'uneG')
|
|
|
|
|
if (VendorId[1] == 'uneG')
|
|
|
|
|
{
|
|
|
|
|
if (VendorId[1] == 'Ieni')
|
|
|
|
|
if (VendorId[3] == 'Ieni')
|
|
|
|
|
{
|
|
|
|
|
if (VendorId[2] == 'letn')
|
|
|
|
|
{
|
|
|
|
|
return(Regedx & HT_BIT); // Genuine Intel with hyper-Threading technology
|
|
|
|
|
return(Regs[3] & HT_BIT); // Genuine Intel with hyper-Threading technology
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
@@ -3862,22 +3764,17 @@ unsigned int SystemInformationImplementation::IsHyperThreadingSupported()
|
|
|
|
|
/** Return the APIC Id. Works only for windows. */
|
|
|
|
|
unsigned char SystemInformationImplementation::GetAPICId()
|
|
|
|
|
{
|
|
|
|
|
unsigned int Regebx = 0;
|
|
|
|
|
int Regs[4] = { 0, 0, 0, 0 };
|
|
|
|
|
|
|
|
|
|
#if USE_ASM_INSTRUCTIONS
|
|
|
|
|
#if USE_CPUID
|
|
|
|
|
if (!this->IsHyperThreadingSupported())
|
|
|
|
|
{
|
|
|
|
|
return static_cast<unsigned char>(-1); // HT not supported
|
|
|
|
|
} // Logical processor = 1
|
|
|
|
|
__asm
|
|
|
|
|
{
|
|
|
|
|
mov eax, 1
|
|
|
|
|
cpuid
|
|
|
|
|
mov Regebx, ebx
|
|
|
|
|
}
|
|
|
|
|
call_cpuid(1, Regs);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
return static_cast<unsigned char>((Regebx & INITIAL_APIC_ID_BITS) >> 24);
|
|
|
|
|
return static_cast<unsigned char>((Regs[1] & INITIAL_APIC_ID_BITS) >> 24);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
@@ -4284,25 +4181,24 @@ bool SystemInformationImplementation::QuerySolarisInfo()
|
|
|
|
|
this->NumberOfPhysicalCPU = static_cast<unsigned int>(
|
|
|
|
|
atoi(this->ParseValueFromKStat("-n syste_misc -s ncpus").c_str()));
|
|
|
|
|
this->NumberOfLogicalCPU = this->NumberOfPhysicalCPU;
|
|
|
|
|
|
|
|
|
|
if(this->NumberOfPhysicalCPU!=0)
|
|
|
|
|
{
|
|
|
|
|
this->NumberOfLogicalCPU /= this->NumberOfPhysicalCPU;
|
|
|
|
|
}
|
|
|
|
|
this->Features.ExtendedFeatures.LogicalProcessorsPerPhysical = 1;
|
|
|
|
|
|
|
|
|
|
this->CPUSpeedInMHz = static_cast<float>(atoi(this->ParseValueFromKStat("-s clock_MHz").c_str()));
|
|
|
|
|
|
|
|
|
|
// Chip family
|
|
|
|
|
this->ChipID.Family = 0;
|
|
|
|
|
|
|
|
|
|
// Chip Vendor
|
|
|
|
|
this->ChipID.Vendor = "Sun";
|
|
|
|
|
this->FindManufacturer();
|
|
|
|
|
|
|
|
|
|
// Chip Model
|
|
|
|
|
this->ChipID.ProcessorName = this->ParseValueFromKStat("-s cpu_type");
|
|
|
|
|
this->ChipID.Model = 0;
|
|
|
|
|
|
|
|
|
|
// Chip Vendor
|
|
|
|
|
if (this->ChipID.ProcessorName != "i386")
|
|
|
|
|
{
|
|
|
|
|
this->ChipID.Vendor = "Sun";
|
|
|
|
|
this->FindManufacturer();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Cache size
|
|
|
|
|
this->Features.L1CacheSize = 0;
|
|
|
|
|
this->Features.L2CacheSize = 0;
|
|
|
|
@@ -4310,9 +4206,7 @@ bool SystemInformationImplementation::QuerySolarisInfo()
|
|
|
|
|
char* tail;
|
|
|
|
|
unsigned long totalMemory =
|
|
|
|
|
strtoul(this->ParseValueFromKStat("-s physmem").c_str(),&tail,0);
|
|
|
|
|
this->TotalPhysicalMemory = totalMemory/1024;
|
|
|
|
|
this->TotalPhysicalMemory *= 8192;
|
|
|
|
|
this->TotalPhysicalMemory /= 1024;
|
|
|
|
|
this->TotalPhysicalMemory = totalMemory/128;
|
|
|
|
|
|
|
|
|
|
// Undefined values (for now at least)
|
|
|
|
|
this->TotalVirtualMemory = 0;
|
|
|
|
@@ -4426,6 +4320,31 @@ bool SystemInformationImplementation::QueryQNXMemory()
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool SystemInformationImplementation::QueryBSDMemory()
|
|
|
|
|
{
|
|
|
|
|
#if defined(__OpenBSD__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__DragonFly__)
|
|
|
|
|
int ctrl[2] = { CTL_HW, HW_PHYSMEM };
|
|
|
|
|
#if defined(HW_PHYSMEM64)
|
|
|
|
|
int64_t k;
|
|
|
|
|
ctrl[1] = HW_PHYSMEM64;
|
|
|
|
|
#else
|
|
|
|
|
int k;
|
|
|
|
|
#endif
|
|
|
|
|
size_t sz = sizeof(k);
|
|
|
|
|
|
|
|
|
|
if (sysctl(ctrl, 2, &k, &sz, NULL, 0) != 0)
|
|
|
|
|
{
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
this->TotalPhysicalMemory = k>>10>>10;
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
#else
|
|
|
|
|
return false;
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool SystemInformationImplementation::QueryQNXProcessor()
|
|
|
|
|
{
|
|
|
|
|
#if defined(__QNX__)
|
|
|
|
@@ -4479,6 +4398,124 @@ bool SystemInformationImplementation::QueryQNXProcessor()
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool SystemInformationImplementation::QueryBSDProcessor()
|
|
|
|
|
{
|
|
|
|
|
#if defined(__OpenBSD__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__DragonFly__)
|
|
|
|
|
int k;
|
|
|
|
|
size_t sz = sizeof(k);
|
|
|
|
|
int ctrl[2] = { CTL_HW, HW_NCPU };
|
|
|
|
|
|
|
|
|
|
if (sysctl(ctrl, 2, &k, &sz, NULL, 0) != 0)
|
|
|
|
|
{
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
this->NumberOfPhysicalCPU = k;
|
|
|
|
|
this->NumberOfLogicalCPU = this->NumberOfPhysicalCPU;
|
|
|
|
|
|
|
|
|
|
#if defined(HW_CPUSPEED)
|
|
|
|
|
ctrl[1] = HW_CPUSPEED;
|
|
|
|
|
|
|
|
|
|
if (sysctl(ctrl, 2, &k, &sz, NULL, 0) != 0)
|
|
|
|
|
{
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
this->CPUSpeedInMHz = (float) k;
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
#else
|
|
|
|
|
return false;
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool SystemInformationImplementation::QueryHPUXMemory()
|
|
|
|
|
{
|
|
|
|
|
#if defined(__hpux)
|
|
|
|
|
unsigned long tv=0;
|
|
|
|
|
unsigned long tp=0;
|
|
|
|
|
unsigned long av=0;
|
|
|
|
|
unsigned long ap=0;
|
|
|
|
|
struct pst_static pst;
|
|
|
|
|
struct pst_dynamic pdy;
|
|
|
|
|
|
|
|
|
|
unsigned long ps = 0;
|
|
|
|
|
if (pstat_getstatic(&pst, sizeof(pst), (size_t) 1, 0) == -1)
|
|
|
|
|
{
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ps = pst.page_size;
|
|
|
|
|
tp = pst.physical_memory *ps;
|
|
|
|
|
tv = (pst.physical_memory + pst.pst_maxmem) * ps;
|
|
|
|
|
if (pstat_getdynamic(&pdy, sizeof(pdy), (size_t) 1, 0) == -1)
|
|
|
|
|
{
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ap = tp - pdy.psd_rm * ps;
|
|
|
|
|
av = tv - pdy.psd_vm;
|
|
|
|
|
this->TotalVirtualMemory = tv>>10>>10;
|
|
|
|
|
this->TotalPhysicalMemory = tp>>10>>10;
|
|
|
|
|
this->AvailableVirtualMemory = av>>10>>10;
|
|
|
|
|
this->AvailablePhysicalMemory = ap>>10>>10;
|
|
|
|
|
return true;
|
|
|
|
|
#else
|
|
|
|
|
return false;
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool SystemInformationImplementation::QueryHPUXProcessor()
|
|
|
|
|
{
|
|
|
|
|
#if defined(__hpux)
|
|
|
|
|
# if defined(KWSYS_SYS_HAS_MPCTL_H)
|
|
|
|
|
int c = mpctl(MPC_GETNUMSPUS_SYS, 0, 0);
|
|
|
|
|
if (c <= 0)
|
|
|
|
|
{
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
this->NumberOfPhysicalCPU = c;
|
|
|
|
|
this->NumberOfLogicalCPU = this->NumberOfPhysicalCPU;
|
|
|
|
|
|
|
|
|
|
long t = sysconf(_SC_CPU_VERSION);
|
|
|
|
|
|
|
|
|
|
if (t == -1)
|
|
|
|
|
{
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (t)
|
|
|
|
|
{
|
|
|
|
|
case CPU_PA_RISC1_0:
|
|
|
|
|
this->ChipID.Vendor = "Hewlett-Packard";
|
|
|
|
|
this->ChipID.Family = 0x100;
|
|
|
|
|
case CPU_PA_RISC1_1:
|
|
|
|
|
this->ChipID.Vendor = "Hewlett-Packard";
|
|
|
|
|
this->ChipID.Family = 0x110;
|
|
|
|
|
case CPU_PA_RISC2_0:
|
|
|
|
|
this->ChipID.Vendor = "Hewlett-Packard";
|
|
|
|
|
this->ChipID.Family = 0x200;
|
|
|
|
|
case CPU_IA64_ARCHREV_0:
|
|
|
|
|
this->ChipID.Vendor = "GenuineIntel";
|
|
|
|
|
this->Features.HasIA64 = true;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
this->FindManufacturer();
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
# else
|
|
|
|
|
return false;
|
|
|
|
|
# endif
|
|
|
|
|
#else
|
|
|
|
|
return false;
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/** Query the operating system information */
|
|
|
|
|
bool SystemInformationImplementation::QueryOSInformation()
|
|
|
|
|
{
|
|
|
|
|