diff --git a/.cproject b/.cproject
index f635e1a..51983dc 100644
--- a/.cproject
+++ b/.cproject
@@ -23,7 +23,7 @@
-
+
@@ -38,13 +38,24 @@
@@ -102,7 +113,7 @@
-
+
@@ -113,13 +124,24 @@
diff --git a/.mxproject b/.mxproject
index 0f92e95..130b8e7 100644
--- a/.mxproject
+++ b/.mxproject
@@ -1,24 +1,23 @@
[PreviousLibFiles]
-LibFiles=Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_tim.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_tim_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_def.h;Drivers\STM32L4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_i2c.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_i2c_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ramfunc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_pwr.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_pwr_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_cortex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_exti.h;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_tim.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_tim_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_def.h;Drivers\STM32L4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_i2c.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_i2c_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ramfunc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_pwr.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_pwr_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_cortex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_exti.h;Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l432xx.h;Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h;Drivers\CMSIS\Device\ST\STM32L4xx\Include\system_stm32l4xx.h;Drivers\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
+LibFiles=Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_gpio.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_system.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_spi.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_dma.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_dmamux.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_bus.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_cortex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_rcc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_crs.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_utils.h;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_utils.c;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_exti.h;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_exti.c;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_pwr.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_tim.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_usart.h;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_gpio.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_spi.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_dma.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_pwr.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_exti.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_tim.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_usart.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_rcc.c;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_gpio.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_system.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_spi.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_dma.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_dmamux.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_bus.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_cortex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_rcc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_crs.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_utils.h;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_utils.c;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_exti.h;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_exti.c;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_pwr.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_tim.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_usart.h;Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l432xx.h;Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h;Drivers\CMSIS\Device\ST\STM32L4xx\Include\system_stm32l4xx.h;Drivers\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
[PreviousUsedCubeIDEFiles]
-SourceFiles=Core\Src\main.c;Core\Src\stm32l4xx_it.c;Core\Src\stm32l4xx_hal_msp.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c;Drivers\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c;Core\Src\system_stm32l4xx.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c;Drivers\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c;Core\Src\system_stm32l4xx.c;;;
-HeaderPath=Drivers\STM32L4xx_HAL_Driver\Inc;Drivers\STM32L4xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32L4xx\Include;Drivers\CMSIS\Include;Core\Inc;
-CDefines=USE_HAL_DRIVER;STM32L432xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
+SourceFiles=Core\Src\main.c;Core\Src\stm32l4xx_it.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_utils.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_exti.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_gpio.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_spi.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_dma.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_pwr.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_tim.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_usart.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_rcc.c;Drivers\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c;Core\Src\system_stm32l4xx.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_utils.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_exti.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_gpio.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_spi.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_dma.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_pwr.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_tim.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_usart.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_rcc.c;Drivers\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c;Core\Src\system_stm32l4xx.c;;;
+HeaderPath=Drivers\STM32L4xx_HAL_Driver\Inc;Drivers\CMSIS\Device\ST\STM32L4xx\Include;Drivers\CMSIS\Include;Core\Inc;
+CDefines=USE_FULL_LL_DRIVER;HSE_VALUE:8000000;HSE_STARTUP_TIMEOUT:100;LSE_STARTUP_TIMEOUT:5000;LSE_VALUE:32768;MSI_VALUE:48000000;EXTERNALSAI1_CLOCK_VALUE:2097000;HSI_VALUE:16000000;LSI_VALUE:32000;VDD_VALUE:3300;PREFETCH_ENABLE:0;INSTRUCTION_CACHE_ENABLE:1;DATA_CACHE_ENABLE:1;STM32L432xx;USE_FULL_LL_DRIVER;HSE_VALUE:8000000;HSE_STARTUP_TIMEOUT:100;LSE_STARTUP_TIMEOUT:5000;LSE_VALUE:32768;MSI_VALUE:48000000;EXTERNALSAI1_CLOCK_VALUE:2097000;HSI_VALUE:16000000;LSI_VALUE:32000;VDD_VALUE:3300;PREFETCH_ENABLE:0;INSTRUCTION_CACHE_ENABLE:1;DATA_CACHE_ENABLE:1;
[PreviousGenFiles]
AdvancedFolderStructure=true
HeaderFileListSize=3
HeaderFiles#0=C:/file/STMGyro/Core/Inc/stm32l4xx_it.h
-HeaderFiles#1=C:/file/STMGyro/Core/Inc/stm32l4xx_hal_conf.h
+HeaderFiles#1=C:/file/STMGyro/Core/Inc/stm32_assert.h
HeaderFiles#2=C:/file/STMGyro/Core/Inc/main.h
HeaderFolderListSize=1
HeaderPath#0=C:/file/STMGyro/Core/Inc
HeaderFiles=;
-SourceFileListSize=3
+SourceFileListSize=2
SourceFiles#0=C:/file/STMGyro/Core/Src/stm32l4xx_it.c
-SourceFiles#1=C:/file/STMGyro/Core/Src/stm32l4xx_hal_msp.c
-SourceFiles#2=C:/file/STMGyro/Core/Src/main.c
+SourceFiles#1=C:/file/STMGyro/Core/Src/main.c
SourceFolderListSize=1
SourcePath#0=C:/file/STMGyro/Core/Src
SourceFiles=;
diff --git a/Core/Inc/main.h b/Core/Inc/main.h
index 1474fdc..6415bf3 100644
--- a/Core/Inc/main.h
+++ b/Core/Inc/main.h
@@ -27,7 +27,23 @@ extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
+#include "stm32l4xx_ll_crs.h"
+#include "stm32l4xx_ll_rcc.h"
+#include "stm32l4xx_ll_bus.h"
+#include "stm32l4xx_ll_system.h"
+#include "stm32l4xx_ll_exti.h"
+#include "stm32l4xx_ll_cortex.h"
+#include "stm32l4xx_ll_utils.h"
+#include "stm32l4xx_ll_pwr.h"
+#include "stm32l4xx_ll_dma.h"
+#include "stm32l4xx_ll_spi.h"
+#include "stm32l4xx_ll_tim.h"
+#include "stm32l4xx_ll_usart.h"
+#include "stm32l4xx_ll_gpio.h"
+
+#if defined(USE_FULL_ASSERT)
+#include "stm32_assert.h"
+#endif /* USE_FULL_ASSERT */
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
@@ -57,14 +73,26 @@ void Error_Handler(void);
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
-#define CS1_Pin GPIO_PIN_1
+#define CS1_Pin LL_GPIO_PIN_1
#define CS1_GPIO_Port GPIOA
-#define CS2_Pin GPIO_PIN_2
+#define CS2_Pin LL_GPIO_PIN_2
#define CS2_GPIO_Port GPIOA
-#define CS3_Pin GPIO_PIN_3
+#define CS3_Pin LL_GPIO_PIN_3
#define CS3_GPIO_Port GPIOA
-#define RESET_Pin GPIO_PIN_0
+#define RESET_Pin LL_GPIO_PIN_0
#define RESET_GPIO_Port GPIOB
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority,
+ 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority,
+ 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+ 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+ 1 bit for subpriority */
+#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+ 0 bit for subpriority */
+#endif
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
diff --git a/Core/Inc/stm32_assert.h b/Core/Inc/stm32_assert.h
new file mode 100644
index 0000000..ce166a2
--- /dev/null
+++ b/Core/Inc/stm32_assert.h
@@ -0,0 +1,53 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32_assert.h
+ * @brief STM32 assert file.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
diff --git a/Core/Inc/stm32l4xx_hal_conf.h b/Core/Inc/stm32l4xx_hal_conf.h
deleted file mode 100644
index 3a19d9a..0000000
--- a/Core/Inc/stm32l4xx_hal_conf.h
+++ /dev/null
@@ -1,482 +0,0 @@
-/* USER CODE BEGIN Header */
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_conf.h
- * @author MCD Application Team
- * @brief HAL configuration template file.
- * This file should be copied to the application folder and renamed
- * to stm32l4xx_hal_conf.h.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-/* USER CODE END Header */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L4xx_HAL_CONF_H
-#define STM32L4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
- * @brief This is the list of modules to be used in the HAL driver
- */
-#define HAL_MODULE_ENABLED
-/*#define HAL_ADC_MODULE_ENABLED */
-/*#define HAL_CRYP_MODULE_ENABLED */
-/*#define HAL_CAN_MODULE_ENABLED */
-/*#define HAL_COMP_MODULE_ENABLED */
-/*#define HAL_CRC_MODULE_ENABLED */
-/*#define HAL_CRYP_MODULE_ENABLED */
-/*#define HAL_DAC_MODULE_ENABLED */
-/*#define HAL_DCMI_MODULE_ENABLED */
-/*#define HAL_DMA2D_MODULE_ENABLED */
-/*#define HAL_DFSDM_MODULE_ENABLED */
-/*#define HAL_DSI_MODULE_ENABLED */
-/*#define HAL_FIREWALL_MODULE_ENABLED */
-/*#define HAL_GFXMMU_MODULE_ENABLED */
-/*#define HAL_HCD_MODULE_ENABLED */
-/*#define HAL_HASH_MODULE_ENABLED */
-/*#define HAL_I2S_MODULE_ENABLED */
-/*#define HAL_IRDA_MODULE_ENABLED */
-/*#define HAL_IWDG_MODULE_ENABLED */
-/*#define HAL_LTDC_MODULE_ENABLED */
-/*#define HAL_LCD_MODULE_ENABLED */
-/*#define HAL_LPTIM_MODULE_ENABLED */
-/*#define HAL_MMC_MODULE_ENABLED */
-/*#define HAL_NAND_MODULE_ENABLED */
-/*#define HAL_NOR_MODULE_ENABLED */
-/*#define HAL_OPAMP_MODULE_ENABLED */
-/*#define HAL_OSPI_MODULE_ENABLED */
-/*#define HAL_OSPI_MODULE_ENABLED */
-/*#define HAL_PCD_MODULE_ENABLED */
-/*#define HAL_PKA_MODULE_ENABLED */
-/*#define HAL_QSPI_MODULE_ENABLED */
-/*#define HAL_QSPI_MODULE_ENABLED */
-/*#define HAL_RNG_MODULE_ENABLED */
-/*#define HAL_RTC_MODULE_ENABLED */
-/*#define HAL_SAI_MODULE_ENABLED */
-/*#define HAL_SD_MODULE_ENABLED */
-/*#define HAL_SMBUS_MODULE_ENABLED */
-/*#define HAL_SMARTCARD_MODULE_ENABLED */
-/*#define HAL_SPI_MODULE_ENABLED */
-/*#define HAL_SRAM_MODULE_ENABLED */
-/*#define HAL_SWPMI_MODULE_ENABLED */
-/*#define HAL_TIM_MODULE_ENABLED */
-/*#define HAL_TSC_MODULE_ENABLED */
-/*#define HAL_UART_MODULE_ENABLED */
-/*#define HAL_USART_MODULE_ENABLED */
-/*#define HAL_WWDG_MODULE_ENABLED */
-/*#define HAL_EXTI_MODULE_ENABLED */
-/*#define HAL_PSSI_MODULE_ENABLED */
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_EXTI_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
- * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
- * This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
- */
-#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
- * @brief Internal Multiple Speed oscillator (MSI) default value.
- * This value is the default MSI range value after Reset.
- */
-#if !defined (MSI_VALUE)
- #define MSI_VALUE ((uint32_t)48000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-/**
- * @brief Internal High Speed oscillator (HSI) value.
- * This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
- */
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
- * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
- * This internal oscillator is mainly dedicated to provide a high precision clock to
- * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
- * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
- * which is subject to manufacturing process variations.
- */
-#if !defined (HSI48_VALUE)
- #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
- The real value my vary depending on manufacturing process variations.*/
-#endif /* HSI48_VALUE */
-
-/**
- * @brief Internal Low Speed oscillator (LSI) value.
- */
-#if !defined (LSI_VALUE)
- #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
- The real value may vary depending on the variations
- in voltage and temperature.*/
-
-/**
- * @brief External Low Speed oscillator (LSE) value.
- * This value is used by the UART, RTC HAL module to compute the system frequency
- */
-#if !defined (LSE_VALUE)
- #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-#if !defined (LSE_STARTUP_TIMEOUT)
- #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
- * @brief External clock source for SAI1 peripheral
- * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
- * frequency.
- */
-#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
- #define EXTERNAL_SAI1_CLOCK_VALUE 2097000U /*!< Value of the SAI1 External clock source in Hz*/
-#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
-
-/**
- * @brief External clock source for SAI2 peripheral
- * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
- * frequency.
- */
-#if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
- #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2 External clock source in Hz*/
-#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
- === you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
- * @brief This is the HAL system configuration section
- */
-
-#define VDD_VALUE 3300U /*!< Value of VDD in mv */
-#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority */
-#define USE_RTOS 0U
-#define PREFETCH_ENABLE 0U
-#define INSTRUCTION_CACHE_ENABLE 1U
-#define DATA_CACHE_ENABLE 1U
-
-/* ########################## Assert Selection ############################## */
-/**
- * @brief Uncomment the line below to expanse the "assert_param" macro in the
- * HAL drivers code
- */
-/* #define USE_FULL_ASSERT 1U */
-
-/* ################## Register callback feature configuration ############### */
-/**
- * @brief Set below the peripheral configuration to "1U" to add the support
- * of HAL callback registration/deregistration feature for the HAL
- * driver(s). This allows user application to provide specific callback
- * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
- * the default weak callback functions (see each stm32l4xx_hal_ppp.h file
- * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
- * for each PPP peripheral).
- */
-#define USE_HAL_ADC_REGISTER_CALLBACKS 0U
-#define USE_HAL_CAN_REGISTER_CALLBACKS 0U
-#define USE_HAL_COMP_REGISTER_CALLBACKS 0U
-#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U
-#define USE_HAL_DAC_REGISTER_CALLBACKS 0U
-#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U
-#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U
-#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U
-#define USE_HAL_DSI_REGISTER_CALLBACKS 0U
-#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U
-#define USE_HAL_HASH_REGISTER_CALLBACKS 0U
-#define USE_HAL_HCD_REGISTER_CALLBACKS 0U
-#define USE_HAL_I2C_REGISTER_CALLBACKS 0U
-#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U
-#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U
-#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U
-#define USE_HAL_MMC_REGISTER_CALLBACKS 0U
-#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U
-#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U
-#define USE_HAL_PCD_REGISTER_CALLBACKS 0U
-#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U
-#define USE_HAL_RNG_REGISTER_CALLBACKS 0U
-#define USE_HAL_RTC_REGISTER_CALLBACKS 0U
-#define USE_HAL_SAI_REGISTER_CALLBACKS 0U
-#define USE_HAL_SD_REGISTER_CALLBACKS 0U
-#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U
-#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U
-#define USE_HAL_SPI_REGISTER_CALLBACKS 0U
-#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U
-#define USE_HAL_TIM_REGISTER_CALLBACKS 0U
-#define USE_HAL_TSC_REGISTER_CALLBACKS 0U
-#define USE_HAL_UART_REGISTER_CALLBACKS 0U
-#define USE_HAL_USART_REGISTER_CALLBACKS 0U
-#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
- * Activated: CRC code is present inside driver
- * Deactivated: CRC code cleaned from driver
- */
-
-#define USE_SPI_CRC 0U
-
-/* Includes ------------------------------------------------------------------*/
-/**
- * @brief Include module's header file
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32l4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32l4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
- #include "stm32l4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32l4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32l4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32l4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
- #include "stm32l4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
- #include "Legacy/stm32l4xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
- #include "stm32l4xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32l4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
- #include "stm32l4xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
- #include "stm32l4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
- #include "stm32l4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
- #include "stm32l4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32l4xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
- #include "stm32l4xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_GFXMMU_MODULE_ENABLED
- #include "stm32l4xx_hal_gfxmmu.h"
-#endif /* HAL_GFXMMU_MODULE_ENABLED */
-
-#ifdef HAL_FIREWALL_MODULE_ENABLED
- #include "stm32l4xx_hal_firewall.h"
-#endif /* HAL_FIREWALL_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32l4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32l4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32l4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32l4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32l4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32l4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LCD_MODULE_ENABLED
- #include "stm32l4xx_hal_lcd.h"
-#endif /* HAL_LCD_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32l4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32l4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32l4xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
- #include "stm32l4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
- #include "stm32l4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
- #include "stm32l4xx_hal_opamp.h"
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-
-#ifdef HAL_OSPI_MODULE_ENABLED
- #include "stm32l4xx_hal_ospi.h"
-#endif /* HAL_OSPI_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32l4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_PKA_MODULE_ENABLED
- #include "stm32l4xx_hal_pka.h"
-#endif /* HAL_PKA_MODULE_ENABLED */
-
-#ifdef HAL_PSSI_MODULE_ENABLED
- #include "stm32l4xx_hal_pssi.h"
-#endif /* HAL_PSSI_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32l4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32l4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32l4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32l4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32l4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32l4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32l4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32l4xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32l4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
- #include "stm32l4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_SWPMI_MODULE_ENABLED
- #include "stm32l4xx_hal_swpmi.h"
-#endif /* HAL_SWPMI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32l4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_TSC_MODULE_ENABLED
- #include "stm32l4xx_hal_tsc.h"
-#endif /* HAL_TSC_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32l4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32l4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32l4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t *file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L4xx_HAL_CONF_H */
diff --git a/Core/Inc/stm32l4xx_it.h b/Core/Inc/stm32l4xx_it.h
index 468f72d..8099b56 100644
--- a/Core/Inc/stm32l4xx_it.h
+++ b/Core/Inc/stm32l4xx_it.h
@@ -55,6 +55,9 @@ void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
+void TIM1_UP_TIM16_IRQHandler(void);
+void SPI1_IRQHandler(void);
+void USART1_IRQHandler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
diff --git a/Core/Src/main.c b/Core/Src/main.c
index 13e115f..c2becfa 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -1,20 +1,20 @@
/* USER CODE BEGIN Header */
/**
- ******************************************************************************
- * @file : main.c
- * @brief : Main program body
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2022 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
@@ -55,200 +55,403 @@ void GPIO_Reset(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
-
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
-
+uint8_t data_out[18] = {0};
+uint8_t flag_receive = 0;
+uint8_t flag_transmit = 0;
+struct sData data[3];
+int32_t tx_index = 0;
+uint8_t data_in[6] = {0};
+uint8_t str[60];
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
static void MX_GPIO_Init(void);
+static void MX_SPI1_Init(void);
+static void MX_USART1_UART_Init(void);
+static void MX_TIM1_Init(void);
/* USER CODE BEGIN PFP */
-
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_SPI1_Init(void);
+static void MX_USART1_UART_Init(void);
+static void MX_TIM1_Init(void);
+uint16_t SPI1_Read(void);
+void SPI1_Tx();
+void USART_TX (uint8_t* dt, uint16_t sz);
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
-uint8_t data_out[18] = {0};
-uint8_t flag_receive = 0;
-uint8_t flag_transmit = 0;
-struct sData data[3];
/* USER CODE END 0 */
/**
- * @brief The application entry point.
- * @retval int
- */
+ * @brief The application entry point.
+ * @retval int
+ */
int main(void)
{
- /* USER CODE BEGIN 1 */
- uint8_t data_in[6] = {0};
- /* USER CODE END 1 */
+ /* USER CODE BEGIN 1 */
+ /* USER CODE END 1 */
- /* MCU Configuration--------------------------------------------------------*/
+ /* MCU Configuration--------------------------------------------------------*/
- /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
- HAL_Init();
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
- /* USER CODE BEGIN Init */
+ LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
+ LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
- /* USER CODE END Init */
+ NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
- /* Configure the system clock */
- SystemClock_Config();
+ /* System interrupt init*/
+ /* SysTick_IRQn interrupt configuration */
+ NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),15, 0));
- /* USER CODE BEGIN SysInit */
+ /* USER CODE BEGIN Init */
- /* USER CODE END SysInit */
+ /* USER CODE END Init */
- /* Initialize all configured peripherals */
- MX_GPIO_Init();
- /* USER CODE BEGIN 2 */
- RESET_ON();
- HAL_Delay(100);
- /* USER CODE END 2 */
+ /* Configure the system clock */
+ SystemClock_Config();
- /* Infinite loop */
- /* USER CODE BEGIN WHILE */
- char str[19];
- memset(str, 0, sizeof(str));
- int8_t res = comand_mes(data_in, sizeof(data_in) / sizeof(data_in[0]));
- if(res != 0) return res;
- while (1)
- {
- while(!flag_transmit);
- CS1_ON();
- /*hspi1.Instance->DR = data_in[0]; // output something on MOSI while reading MISO
- while ((hspi1.Instance->SR & SPI_FLAG_RXNE) == 0){} //Wait for Data Ready to Read
- data_out[0] = hspi1.Instance->DR;
- //res = HAL_SPI_TransmitReceive_IT(&hspi1, data_in, data_out, sizeof(data_in) / sizeof(data_in[0]));
- while(!flag_receive && res == 0);
- CS1_OFF();
- flag_receive = 0;
+ /* USER CODE BEGIN SysInit */
- CS2_ON();
- hspi1.Instance->DR = data_in[0]; // output something on MOSI while reading MISO
- while ((hspi1.Instance->SR & SPI_FLAG_RXNE) == 0){} //Wait for Data Ready to Read
- data_out[0] = hspi1.Instance->DR;
- //res = HAL_SPI_TransmitReceive_IT(&hspi1, data_in, &data_out[6], sizeof(data_in) / sizeof(data_in[0]));
- while(!flag_receive && res == 0);
- CS2_OFF();
- flag_receive = 0;
+ /* USER CODE END SysInit */
- CS3_ON();
- hspi1.Instance->DR = data_in[0]; // output something on MOSI while reading MISO
- while ((hspi1.Instance->SR & SPI_FLAG_RXNE) == 0){} //Wait for Data Ready to Read
- data_out[0] = hspi1.Instance->DR;
- //res = HAL_SPI_TransmitReceive_IT(&hspi1, data_in, &data_out[12], sizeof(data_in) / sizeof(data_in[0]));
- while(!flag_receive && res == 0) ;
- CS3_OFF();*/
- flag_receive = 0;
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+ MX_SPI1_Init();
+ MX_USART1_UART_Init();
+ MX_TIM1_Init();
+ /* USER CODE BEGIN 2 */
+ RESET_ON();
+ LL_mDelay(100);
+ /* USER CODE END 2 */
- status_mes(&data_out[0], 6u, &data[0]);
- status_mes(&data_out[6], 6u, &data[1]);
- status_mes(&data_out[12], 6u, &data[2]);
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ char str[19];
+ memset(str, 0, sizeof(str));
+ int8_t res = comand_mes(data_in, sizeof(data_in) / sizeof(data_in[0]));
+ if(res != 0) return res;
+ LL_TIM_EnableIT_UPDATE(TIM1);
+ LL_TIM_EnableCounter(TIM1);
+ while (1)
+ {
+ while(!flag_transmit);
+ CS1_ON();
+ SPI1_Tx();
+ for(int i = 0; i < 6; i++) data_out[i] = SPI1_Read();
+ CS1_OFF();
- flag_transmit = 1;
+ CS2_ON();
+ SPI1_Tx();
+ for(int i = 0; i < 6; i++) data_out[6 + i] = SPI1_Read();
+ CS2_OFF();
- /* USER CODE END WHILE */
+ CS3_ON();
+ SPI1_Tx();
+ for(int i = 0; i < 6; i++) data_out[12 + i] = SPI1_Read();
+ CS3_OFF();
- /* USER CODE BEGIN 3 */
- }
- /* USER CODE END 3 */
+ status_mes(&data_out[0], 6u, &data[0]);
+ status_mes(&data_out[6], 6u, &data[1]);
+ status_mes(&data_out[12], 6u, &data[2]);
+
+ flag_transmit = 1;
+
+ /* USER CODE END WHILE */
+
+ /* USER CODE BEGIN 3 */
+ }
+ /* USER CODE END 3 */
}
/**
- * @brief System Clock Configuration
- * @retval None
- */
+ * @brief System Clock Configuration
+ * @retval None
+ */
void SystemClock_Config(void)
{
- RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ LL_FLASH_SetLatency(LL_FLASH_LATENCY_4);
+ while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_4)
+ {
+ }
+ LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
+ LL_RCC_HSI_Enable();
- /** Configure the main internal regulator output voltage
- */
- if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
- {
- Error_Handler();
- }
- /** Initializes the RCC Oscillators according to the specified parameters
- * in the RCC_OscInitTypeDef structure.
- */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
- RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
- RCC_OscInitStruct.PLL.PLLM = 1;
- RCC_OscInitStruct.PLL.PLLN = 10;
- RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
- RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
- RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- {
- Error_Handler();
- }
- /** Initializes the CPU, AHB and APB buses clocks
- */
- RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
- |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ /* Wait till HSI is ready */
+ while(LL_RCC_HSI_IsReady() != 1)
+ {
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
- {
- Error_Handler();
- }
+ }
+ LL_RCC_HSI_SetCalibTrimming(16);
+ LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, LL_RCC_PLLM_DIV_1, 10, LL_RCC_PLLR_DIV_2);
+ LL_RCC_PLL_EnableDomain_SYS();
+ LL_RCC_PLL_Enable();
+
+ /* Wait till PLL is ready */
+ while(LL_RCC_PLL_IsReady() != 1)
+ {
+
+ }
+ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+
+ /* Wait till System clock is ready */
+ while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+ {
+
+ }
+ LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+ LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+ LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+
+ LL_Init1msTick(80000000);
+
+ LL_SetSystemCoreClock(80000000);
}
/**
- * @brief GPIO Initialization Function
- * @param None
- * @retval None
- */
+ * @brief SPI1 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_SPI1_Init(void)
+{
+
+ /* USER CODE BEGIN SPI1_Init 0 */
+
+ /* USER CODE END SPI1_Init 0 */
+
+ LL_SPI_InitTypeDef SPI_InitStruct = {0};
+
+ LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+ /* Peripheral clock enable */
+ LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1);
+
+ LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+ /**SPI1 GPIO Configuration
+ PA5 ------> SPI1_SCK
+ PA6 ------> SPI1_MISO
+ PA7 ------> SPI1_MOSI
+ */
+ GPIO_InitStruct.Pin = LL_GPIO_PIN_5|LL_GPIO_PIN_6|LL_GPIO_PIN_7;
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ GPIO_InitStruct.Alternate = LL_GPIO_AF_5;
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ /* SPI1 interrupt Init */
+ NVIC_SetPriority(SPI1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+ NVIC_EnableIRQ(SPI1_IRQn);
+
+ /* USER CODE BEGIN SPI1_Init 1 */
+
+ /* USER CODE END SPI1_Init 1 */
+ /* SPI1 parameter configuration*/
+ SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX;
+ SPI_InitStruct.Mode = LL_SPI_MODE_MASTER;
+ SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_8BIT;
+ SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_LOW;
+ SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE;
+ SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
+ SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8;
+ SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
+ SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ SPI_InitStruct.CRCPoly = 7;
+ LL_SPI_Init(SPI1, &SPI_InitStruct);
+ LL_SPI_SetStandard(SPI1, LL_SPI_PROTOCOL_MOTOROLA);
+ LL_SPI_EnableNSSPulseMgt(SPI1);
+ /* USER CODE BEGIN SPI1_Init 2 */
+
+ /* USER CODE END SPI1_Init 2 */
+
+}
+
+/**
+ * @brief TIM1 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_TIM1_Init(void)
+{
+
+ /* USER CODE BEGIN TIM1_Init 0 */
+
+ /* USER CODE END TIM1_Init 0 */
+
+ LL_TIM_InitTypeDef TIM_InitStruct = {0};
+
+ /* Peripheral clock enable */
+ LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1);
+
+ /* TIM1 interrupt Init */
+ NVIC_SetPriority(TIM1_UP_TIM16_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+ NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);
+
+ /* USER CODE BEGIN TIM1_Init 1 */
+
+ /* USER CODE END TIM1_Init 1 */
+ TIM_InitStruct.Prescaler = 799;
+ TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
+ TIM_InitStruct.Autoreload = 99;
+ TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
+ TIM_InitStruct.RepetitionCounter = 0;
+ LL_TIM_Init(TIM1, &TIM_InitStruct);
+ LL_TIM_DisableARRPreload(TIM1);
+ LL_TIM_SetClockSource(TIM1, LL_TIM_CLOCKSOURCE_INTERNAL);
+ LL_TIM_SetTriggerOutput(TIM1, LL_TIM_TRGO_RESET);
+ LL_TIM_SetTriggerOutput2(TIM1, LL_TIM_TRGO2_RESET);
+ LL_TIM_DisableMasterSlaveMode(TIM1);
+ /* USER CODE BEGIN TIM1_Init 2 */
+
+ /* USER CODE END TIM1_Init 2 */
+
+}
+
+/**
+ * @brief USART1 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_USART1_UART_Init(void)
+{
+
+ /* USER CODE BEGIN USART1_Init 0 */
+
+ /* USER CODE END USART1_Init 0 */
+
+ LL_USART_InitTypeDef USART_InitStruct = {0};
+
+ LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+ LL_RCC_SetUSARTClockSource(LL_RCC_USART1_CLKSOURCE_PCLK2);
+
+ /* Peripheral clock enable */
+ LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1);
+
+ LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+ /**USART1 GPIO Configuration
+ PA9 ------> USART1_TX
+ PA10 ------> USART1_RX
+ */
+ GPIO_InitStruct.Pin = LL_GPIO_PIN_9|LL_GPIO_PIN_10;
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ GPIO_InitStruct.Alternate = LL_GPIO_AF_7;
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ /* USART1 interrupt Init */
+ NVIC_SetPriority(USART1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
+ NVIC_EnableIRQ(USART1_IRQn);
+
+ /* USER CODE BEGIN USART1_Init 1 */
+
+ /* USER CODE END USART1_Init 1 */
+ USART_InitStruct.BaudRate = 460800;
+ USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B;
+ USART_InitStruct.StopBits = LL_USART_STOPBITS_1;
+ USART_InitStruct.Parity = LL_USART_PARITY_NONE;
+ USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX;
+ USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+ USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16;
+ LL_USART_Init(USART1, &USART_InitStruct);
+ LL_USART_ConfigAsyncMode(USART1);
+ LL_USART_Enable(USART1);
+ /* USER CODE BEGIN USART1_Init 2 */
+
+ /* USER CODE END USART1_Init 2 */
+
+}
+
+/**
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
static void MX_GPIO_Init(void)
{
- GPIO_InitTypeDef GPIO_InitStruct = {0};
+ LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
- /* GPIO Ports Clock Enable */
- __HAL_RCC_GPIOA_CLK_ENABLE();
- __HAL_RCC_GPIOB_CLK_ENABLE();
+ /* GPIO Ports Clock Enable */
+ LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+ LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
- /*Configure GPIO pin Output Level */
- HAL_GPIO_WritePin(GPIOA, CS1_Pin|CS2_Pin|CS3_Pin, GPIO_PIN_SET);
+ /**/
+ LL_GPIO_SetOutputPin(GPIOA, CS1_Pin|CS2_Pin|CS3_Pin);
- /*Configure GPIO pin Output Level */
- HAL_GPIO_WritePin(RESET_GPIO_Port, RESET_Pin, GPIO_PIN_RESET);
+ /**/
+ LL_GPIO_ResetOutputPin(RESET_GPIO_Port, RESET_Pin);
- /*Configure GPIO pins : CS1_Pin CS2_Pin CS3_Pin */
- GPIO_InitStruct.Pin = CS1_Pin|CS2_Pin|CS3_Pin;
- GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ /**/
+ GPIO_InitStruct.Pin = CS1_Pin|CS2_Pin|CS3_Pin;
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- /*Configure GPIO pin : RESET_Pin */
- GPIO_InitStruct.Pin = RESET_Pin;
- GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- HAL_GPIO_Init(RESET_GPIO_Port, &GPIO_InitStruct);
+ /**/
+ GPIO_InitStruct.Pin = RESET_Pin;
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_OPENDRAIN;
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ LL_GPIO_Init(RESET_GPIO_Port, &GPIO_InitStruct);
}
/* USER CODE BEGIN 4 */
+
+void USART_TX (uint8_t* dt, uint16_t sz)
+{
+ uint16_t ind = 0;
+ while (indSR & SPI_SR_BSY);
+ SPI1->DR = 0; //запускаем обмен почками
+ while(!(SPI1->SR & SPI_SR_RXNE));
+ return SPI1->DR;
+}
+
+void SPI1_Tx()
+{
+ while(SPI1->SR & SPI_SR_BSY);
+ tx_index = 0;
+ SPI1->CR2 |= (1<ISR & USART_ISR_TXE) == 0 && (USART1->ISR & USART_ISR_TC) == 0 && (flag_transmit)) USART_TX(str, res);
+ else USART1->TDR = 1234;
+ flag_transmit = 0;
+ LL_TIM_ClearFlag_UPDATE(TIM1);
+}
/*void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
{
flag_receive = 1;
}
-*/
+ */
/*void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
flag_transmit = 0;
@@ -263,34 +466,34 @@ static void MX_GPIO_Init(void)
/* USER CODE END 4 */
/**
- * @brief This function is executed in case of error occurrence.
- * @retval None
- */
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
void Error_Handler(void)
{
- /* USER CODE BEGIN Error_Handler_Debug */
- /* User can add his own implementation to report the HAL error return state */
- __disable_irq();
- while (1)
- {
- }
- /* USER CODE END Error_Handler_Debug */
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
- * @brief Reports the name of the source file and the source line number
- * where the assert_param error has occurred.
- * @param file: pointer to the source file name
- * @param line: assert_param error line source number
- * @retval None
- */
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
void assert_failed(uint8_t *file, uint32_t line)
{
- /* USER CODE BEGIN 6 */
- /* User can add his own implementation to report the file name and line number,
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
- /* USER CODE END 6 */
+ /* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */
diff --git a/Core/Src/stm32l4xx_hal_msp.c b/Core/Src/stm32l4xx_hal_msp.c
deleted file mode 100644
index 943b2ce..0000000
--- a/Core/Src/stm32l4xx_hal_msp.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* USER CODE BEGIN Header */
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_msp.c
- * @brief This file provides code for the MSP Initialization
- * and de-Initialization codes.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2022 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-/* USER CODE END Header */
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-/* USER CODE BEGIN Includes */
-
-/* USER CODE END Includes */
-
-/* Private typedef -----------------------------------------------------------*/
-/* USER CODE BEGIN TD */
-
-/* USER CODE END TD */
-
-/* Private define ------------------------------------------------------------*/
-/* USER CODE BEGIN Define */
-
-/* USER CODE END Define */
-
-/* Private macro -------------------------------------------------------------*/
-/* USER CODE BEGIN Macro */
-
-/* USER CODE END Macro */
-
-/* Private variables ---------------------------------------------------------*/
-/* USER CODE BEGIN PV */
-
-/* USER CODE END PV */
-
-/* Private function prototypes -----------------------------------------------*/
-/* USER CODE BEGIN PFP */
-
-/* USER CODE END PFP */
-
-/* External functions --------------------------------------------------------*/
-/* USER CODE BEGIN ExternalFunctions */
-
-/* USER CODE END ExternalFunctions */
-
-/* USER CODE BEGIN 0 */
-
-/* USER CODE END 0 */
-/**
- * Initializes the Global MSP.
- */
-void HAL_MspInit(void)
-{
- /* USER CODE BEGIN MspInit 0 */
-
- /* USER CODE END MspInit 0 */
-
- __HAL_RCC_SYSCFG_CLK_ENABLE();
- __HAL_RCC_PWR_CLK_ENABLE();
-
- /* System interrupt init*/
-
- /* USER CODE BEGIN MspInit 1 */
-
- /* USER CODE END MspInit 1 */
-}
-
-/* USER CODE BEGIN 1 */
-
-/* USER CODE END 1 */
-
diff --git a/Core/Src/stm32l4xx_it.c b/Core/Src/stm32l4xx_it.c
index 81cbdb3..50d2e97 100644
--- a/Core/Src/stm32l4xx_it.c
+++ b/Core/Src/stm32l4xx_it.c
@@ -41,6 +41,8 @@
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
+extern int32_t tx_index;
+extern uint8_t data_in[6];
/* USER CODE END PV */
@@ -185,7 +187,7 @@ void SysTick_Handler(void)
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
- HAL_IncTick();
+
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
@@ -198,6 +200,50 @@ void SysTick_Handler(void)
/* please refer to the startup file (startup_stm32l4xx.s). */
/******************************************************************************/
+/**
+ * @brief This function handles TIM1 update interrupt and TIM16 global interrupt.
+ */
+void TIM1_UP_TIM16_IRQHandler(void)
+{
+ /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 0 */
+
+ /* USER CODE END TIM1_UP_TIM16_IRQn 0 */
+
+ /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 1 */
+
+ /* USER CODE END TIM1_UP_TIM16_IRQn 1 */
+}
+
+/**
+ * @brief This function handles SPI1 global interrupt.
+ */
+void SPI1_IRQHandler(void)
+{
+ /* USER CODE BEGIN SPI1_IRQn 0 */
+ SPI1->DR = data_in[tx_index]; //Записываем новое значение в DR
+ tx_index++; //увеличиваем счетчик переданных байт на единицу
+
+ if(tx_index >= 6u)
+ SPI1->CR2 &= ~(1<APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
-#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
-#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
-#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
-#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
-#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
-#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
-#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
-#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
-#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
-#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)
-#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
-#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP)
-#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
-#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_CAN2_STOP)
-#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
-#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
-#endif
-
-#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
-#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
-#endif
-
-#if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
-#endif
-
-#if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
-#endif
-
-#if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
-#endif
-
-#if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
-#endif
-
-#if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
- * @{
- */
-
-/** @brief Main Flash memory mapped at 0x00000000.
- */
-#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
-
-/** @brief System Flash memory mapped at 0x00000000.
- */
-#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
-
-/** @brief Embedded SRAM mapped at 0x00000000.
- */
-#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
-
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-
-/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
- */
-#define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
-
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
- /* STM32L496xx || STM32L4A6xx || */
- /* STM32L4P5xx || STM32L4Q5xx || */
- /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-
-/** @brief OCTOSPI mapped at 0x00000000.
- */
-#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI1() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2))
-#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI2() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_0))
-
-#else
-
-/** @brief QUADSPI mapped at 0x00000000.
- */
-#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
-
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-/**
- * @brief Return the boot mode as configured by user.
- * @retval The boot mode as configured by user. The returned value can be one
- * of the following values:
- * @arg @ref SYSCFG_BOOT_MAINFLASH
- * @arg @ref SYSCFG_BOOT_SYSTEMFLASH
- @if STM32L486xx
- * @arg @ref SYSCFG_BOOT_FMC
- @endif
- * @arg @ref SYSCFG_BOOT_SRAM
- @if STM32L422xx
- * @arg @ref SYSCFG_BOOT_QUADSPI
- @endif
- @if STM32L443xx
- * @arg @ref SYSCFG_BOOT_QUADSPI
- @endif
- @if STM32L462xx
- * @arg @ref SYSCFG_BOOT_QUADSPI
- @endif
- @if STM32L486xx
- * @arg @ref SYSCFG_BOOT_QUADSPI
- @endif
- */
-#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
-
-/** @brief SRAM2 page 0 to 31 write protection enable macro
- * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP
- * @note Write protection can only be disabled by a system reset
- */
-#define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
- SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\
- }while(0)
-
-#if defined(SYSCFG_SWPR2_PAGE63)
-/** @brief SRAM2 page 32 to 63 write protection enable macro
- * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63
- * @note Write protection can only be disabled by a system reset
- */
-#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
- SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\
- }while(0)
-#endif /* SYSCFG_SWPR2_PAGE63 */
-
-/** @brief SRAM2 page write protection unlock prior to erase
- * @note Writing a wrong key reactivates the write protection
- */
-#define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\
- SYSCFG->SKR = 0x53;\
- }while(0)
-
-/** @brief SRAM2 erase
- * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase
- */
-#define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER)
-
-/** @brief Floating Point Unit interrupt enable/disable macros
- * @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts
- */
-#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
- SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
- }while(0)
-
-#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
- CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
- }while(0)
-
-/** @brief SYSCFG Break ECC lock.
- * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
- * @note The selected configuration is locked and can be unlocked only by system reset.
- */
-#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
-
-/** @brief SYSCFG Break Cortex-M4 Lockup lock.
- * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
- * @note The selected configuration is locked and can be unlocked only by system reset.
- */
-#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
-
-/** @brief SYSCFG Break PVD lock.
- * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
- * @note The selected configuration is locked and can be unlocked only by system reset.
- */
-#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
-
-/** @brief SYSCFG Break SRAM2 parity lock.
- * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input.
- * @note The selected configuration is locked and can be unlocked by system reset.
- */
-#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
-
-/** @brief Check SYSCFG flag is set or not.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag
- * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)
-
-/** @brief Set the SPF bit to clear the SRAM Parity Error Flag.
- */
-#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
-
-/** @brief Fast-mode Plus driving capability enable/disable macros
- * @param __FASTMODEPLUS__ This parameter can be a value of :
- * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
- * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
- * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
- * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
- */
-#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
- SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
- }while(0)
-
-#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
- CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
- }while(0)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup HAL_Private_Macros HAL Private Macros
- * @{
- */
-
-/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
- * @{
- */
-
-#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
- (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
- (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
- (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
- (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
- (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
-
-#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \
- ((__CONFIG__) == SYSCFG_BREAK_PVD) || \
- ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \
- ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
-
-#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFUL))
-
-#if defined(VREFBUF)
-#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
- ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
-
-#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
- ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
-
-#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
-#endif /* VREFBUF */
-
-#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
-#elif defined(SYSCFG_FASTMODEPLUS_PB8)
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))
-#elif defined(SYSCFG_FASTMODEPLUS_PB9)
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
-#else
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))
-#endif
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported variables --------------------------------------------------------*/
-
-/** @addtogroup HAL_Exported_Variables
- * @{
- */
-extern __IO uint32_t uwTick;
-extern uint32_t uwTickPrio;
-extern HAL_TickFreqTypeDef uwTickFreq;
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup HAL_Exported_Functions
- * @{
- */
-
-/** @addtogroup HAL_Exported_Functions_Group1
- * @{
- */
-
-/* Initialization and de-initialization functions ******************************/
-HAL_StatusTypeDef HAL_Init(void);
-HAL_StatusTypeDef HAL_DeInit(void);
-void HAL_MspInit(void);
-void HAL_MspDeInit(void);
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
-
-/**
- * @}
- */
-
-/** @addtogroup HAL_Exported_Functions_Group2
- * @{
- */
-
-/* Peripheral Control functions ************************************************/
-void HAL_IncTick(void);
-void HAL_Delay(uint32_t Delay);
-uint32_t HAL_GetTick(void);
-uint32_t HAL_GetTickPrio(void);
-HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
-HAL_TickFreqTypeDef HAL_GetTickFreq(void);
-void HAL_SuspendTick(void);
-void HAL_ResumeTick(void);
-uint32_t HAL_GetHalVersion(void);
-uint32_t HAL_GetREVID(void);
-uint32_t HAL_GetDEVID(void);
-uint32_t HAL_GetUIDw0(void);
-uint32_t HAL_GetUIDw1(void);
-uint32_t HAL_GetUIDw2(void);
-
-/**
- * @}
- */
-
-/** @addtogroup HAL_Exported_Functions_Group3
- * @{
- */
-
-/* DBGMCU Peripheral Control functions *****************************************/
-void HAL_DBGMCU_EnableDBGSleepMode(void);
-void HAL_DBGMCU_DisableDBGSleepMode(void);
-void HAL_DBGMCU_EnableDBGStopMode(void);
-void HAL_DBGMCU_DisableDBGStopMode(void);
-void HAL_DBGMCU_EnableDBGStandbyMode(void);
-void HAL_DBGMCU_DisableDBGStandbyMode(void);
-
-/**
- * @}
- */
-
-/** @addtogroup HAL_Exported_Functions_Group4
- * @{
- */
-
-/* SYSCFG Control functions ****************************************************/
-void HAL_SYSCFG_SRAM2Erase(void);
-void HAL_SYSCFG_EnableMemorySwappingBank(void);
-void HAL_SYSCFG_DisableMemorySwappingBank(void);
-
-#if defined(VREFBUF)
-void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
-void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
-void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
-HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
-void HAL_SYSCFG_DisableVREFBUF(void);
-#endif /* VREFBUF */
-
-void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
-void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L4xx_HAL_H */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h
deleted file mode 100644
index 2aca387..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h
+++ /dev/null
@@ -1,420 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_cortex.h
- * @author MCD Application Team
- * @brief Header file of CORTEX HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file in
- * the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L4xx_HAL_CORTEX_H
-#define STM32L4xx_HAL_CORTEX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup CORTEX CORTEX
- * @brief CORTEX HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
- * @{
- */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
- * @brief MPU Region initialization structure
- * @{
- */
-typedef struct
-{
- uint8_t Enable; /*!< Specifies the status of the region.
- This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
- uint8_t Number; /*!< Specifies the number of the region to protect.
- This parameter can be a value of @ref CORTEX_MPU_Region_Number */
- uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
- uint8_t Size; /*!< Specifies the size of the region to protect.
- This parameter can be a value of @ref CORTEX_MPU_Region_Size */
- uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
- uint8_t TypeExtField; /*!< Specifies the TEX field level.
- This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
- uint8_t AccessPermission; /*!< Specifies the region access permission type.
- This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
- uint8_t DisableExec; /*!< Specifies the instruction access status.
- This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
- uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
- This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
- uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
- This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
- uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
- This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
-}MPU_Region_InitTypeDef;
-/**
- * @}
- */
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
- * @{
- */
-
-/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
- * @{
- */
-#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority,
- 4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority,
- 3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
- 2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
- 1 bit for subpriority */
-#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
- 0 bit for subpriority */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
- * @{
- */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
-#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
-
-/**
- * @}
- */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
- * @{
- */
-#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
-#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
-#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
-#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
- * @{
- */
-#define MPU_REGION_ENABLE ((uint8_t)0x01)
-#define MPU_REGION_DISABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
- * @{
- */
-#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
-#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
- * @{
- */
-#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
- * @{
- */
-#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
- * @{
- */
-#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
- * @{
- */
-#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
-#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
-#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
-#define MPU_TEX_LEVEL4 ((uint8_t)0x04)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
- * @{
- */
-#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
-#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
-#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
-#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
-#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
-#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
-#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
-#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
-#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
-#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
-#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
-#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
-#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
-#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
-#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
-#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
-#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
-#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
-#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
-#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
-#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
-#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
-#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
-#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
-#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
-#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
-#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
-#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
- * @{
- */
-#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
-#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
-#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
-#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
-#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
-#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
- * @{
- */
-#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
-#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
-#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
-#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
-#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
-#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
-#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
-#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
-/**
- * @}
- */
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
- * @{
- */
-
-/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- * @{
- */
-/* Initialization and Configuration functions *****************************/
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SystemReset(void);
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
- * @brief Cortex control functions
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-uint32_t HAL_NVIC_GetPriorityGrouping(void);
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
-void HAL_SYSTICK_IRQHandler(void);
-void HAL_SYSTICK_Callback(void);
-
-#if (__MPU_PRESENT == 1)
-void HAL_MPU_Enable(uint32_t MPU_Control);
-void HAL_MPU_Disable(void);
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-#endif /* __MPU_PRESENT */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
- * @{
- */
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
- ((GROUP) == NVIC_PRIORITYGROUP_1) || \
- ((GROUP) == NVIC_PRIORITYGROUP_2) || \
- ((GROUP) == NVIC_PRIORITYGROUP_3) || \
- ((GROUP) == NVIC_PRIORITYGROUP_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
-
-#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
-
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
- ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
-
-#if (__MPU_PRESENT == 1)
-#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
- ((STATE) == MPU_REGION_DISABLE))
-
-#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
- ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
-
-#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
- ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
-
-#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
- ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
-
-#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
- ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
-
-#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
- ((TYPE) == MPU_TEX_LEVEL1) || \
- ((TYPE) == MPU_TEX_LEVEL2) || \
- ((TYPE) == MPU_TEX_LEVEL4))
-
-#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
- ((TYPE) == MPU_REGION_PRIV_RW) || \
- ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
- ((TYPE) == MPU_REGION_FULL_ACCESS) || \
- ((TYPE) == MPU_REGION_PRIV_RO) || \
- ((TYPE) == MPU_REGION_PRIV_RO_URO))
-
-#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
- ((NUMBER) == MPU_REGION_NUMBER1) || \
- ((NUMBER) == MPU_REGION_NUMBER2) || \
- ((NUMBER) == MPU_REGION_NUMBER3) || \
- ((NUMBER) == MPU_REGION_NUMBER4) || \
- ((NUMBER) == MPU_REGION_NUMBER5) || \
- ((NUMBER) == MPU_REGION_NUMBER6) || \
- ((NUMBER) == MPU_REGION_NUMBER7))
-
-#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
- ((SIZE) == MPU_REGION_SIZE_64B) || \
- ((SIZE) == MPU_REGION_SIZE_128B) || \
- ((SIZE) == MPU_REGION_SIZE_256B) || \
- ((SIZE) == MPU_REGION_SIZE_512B) || \
- ((SIZE) == MPU_REGION_SIZE_1KB) || \
- ((SIZE) == MPU_REGION_SIZE_2KB) || \
- ((SIZE) == MPU_REGION_SIZE_4KB) || \
- ((SIZE) == MPU_REGION_SIZE_8KB) || \
- ((SIZE) == MPU_REGION_SIZE_16KB) || \
- ((SIZE) == MPU_REGION_SIZE_32KB) || \
- ((SIZE) == MPU_REGION_SIZE_64KB) || \
- ((SIZE) == MPU_REGION_SIZE_128KB) || \
- ((SIZE) == MPU_REGION_SIZE_256KB) || \
- ((SIZE) == MPU_REGION_SIZE_512KB) || \
- ((SIZE) == MPU_REGION_SIZE_1MB) || \
- ((SIZE) == MPU_REGION_SIZE_2MB) || \
- ((SIZE) == MPU_REGION_SIZE_4MB) || \
- ((SIZE) == MPU_REGION_SIZE_8MB) || \
- ((SIZE) == MPU_REGION_SIZE_16MB) || \
- ((SIZE) == MPU_REGION_SIZE_32MB) || \
- ((SIZE) == MPU_REGION_SIZE_64MB) || \
- ((SIZE) == MPU_REGION_SIZE_128MB) || \
- ((SIZE) == MPU_REGION_SIZE_256MB) || \
- ((SIZE) == MPU_REGION_SIZE_512MB) || \
- ((SIZE) == MPU_REGION_SIZE_1GB) || \
- ((SIZE) == MPU_REGION_SIZE_2GB) || \
- ((SIZE) == MPU_REGION_SIZE_4GB))
-
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L4xx_HAL_CORTEX_H */
-
-
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h
deleted file mode 100644
index 4c55db6..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_def.h
- * @author MCD Application Team
- * @brief This file contains HAL common defines, enumeration, macros and
- * structures definitions.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L4xx_HAL_DEF_H
-#define STM32L4xx_HAL_DEF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx.h"
-#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
-#include
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief HAL Status structures definition
- */
-typedef enum
-{
- HAL_OK = 0x00,
- HAL_ERROR = 0x01,
- HAL_BUSY = 0x02,
- HAL_TIMEOUT = 0x03
-} HAL_StatusTypeDef;
-
-/**
- * @brief HAL Lock structures definition
- */
-typedef enum
-{
- HAL_UNLOCKED = 0x00,
- HAL_LOCKED = 0x01
-} HAL_LockTypeDef;
-
-/* Exported macros -----------------------------------------------------------*/
-
-#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
-
-#define HAL_MAX_DELAY 0xFFFFFFFFU
-
-#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
-#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
-
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
- do{ \
- (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
- (__DMA_HANDLE__).Parent = (__HANDLE__); \
- } while(0)
-
-/** @brief Reset the Handle's State field.
- * @param __HANDLE__: specifies the Peripheral Handle.
- * @note This macro can be used for the following purpose:
- * - When the Handle is declared as local variable; before passing it as parameter
- * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
- * to set to 0 the Handle's "State" field.
- * Otherwise, "State" field may have any random value and the first time the function
- * HAL_PPP_Init() is called, the low level hardware initialization will be missed
- * (i.e. HAL_PPP_MspInit() will not be executed).
- * - When there is a need to reconfigure the low level hardware: instead of calling
- * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
- * In this later function, when the Handle's "State" field is set to 0, it will execute the function
- * HAL_PPP_MspInit() which will reconfigure the low level hardware.
- * @retval None
- */
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
-
-#if (USE_RTOS == 1)
- /* Reserved for future use */
- #error " USE_RTOS should be 0 in the current HAL release "
-#else
- #define __HAL_LOCK(__HANDLE__) \
- do{ \
- if((__HANDLE__)->Lock == HAL_LOCKED) \
- { \
- return HAL_BUSY; \
- } \
- else \
- { \
- (__HANDLE__)->Lock = HAL_LOCKED; \
- } \
- }while (0)
-
- #define __HAL_UNLOCK(__HANDLE__) \
- do{ \
- (__HANDLE__)->Lock = HAL_UNLOCKED; \
- }while (0)
-#endif /* USE_RTOS */
-
-
-#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
- #ifndef __weak
- #define __weak __attribute__((weak))
- #endif
- #ifndef __packed
- #define __packed __attribute__((packed))
- #endif
-#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
- #ifndef __weak
- #define __weak __attribute__((weak))
- #endif /* __weak */
- #ifndef __packed
- #define __packed __attribute__((__packed__))
- #endif /* __packed */
-#endif /* __GNUC__ */
-
-
-/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
- #ifndef __ALIGN_BEGIN
- #define __ALIGN_BEGIN
- #endif
- #ifndef __ALIGN_END
- #define __ALIGN_END __attribute__ ((aligned (4)))
- #endif
-#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
- #ifndef __ALIGN_END
- #define __ALIGN_END __attribute__ ((aligned (4)))
- #endif /* __ALIGN_END */
- #ifndef __ALIGN_BEGIN
- #define __ALIGN_BEGIN
- #endif /* __ALIGN_BEGIN */
-#else
- #ifndef __ALIGN_END
- #define __ALIGN_END
- #endif /* __ALIGN_END */
- #ifndef __ALIGN_BEGIN
- #if defined (__CC_ARM) /* ARM Compiler V5 */
- #define __ALIGN_BEGIN __align(4)
- #elif defined (__ICCARM__) /* IAR Compiler */
- #define __ALIGN_BEGIN
- #endif /* __CC_ARM */
- #endif /* __ALIGN_BEGIN */
-#endif /* __GNUC__ */
-
-/**
- * @brief __RAM_FUNC definition
- */
-#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
-/* ARM Compiler V4/V5 and V6
- --------------------------
- RAM functions are defined using the toolchain options.
- Functions that are executed in RAM should reside in a separate source module.
- Using the 'Options for File' dialog you can simply change the 'Code / Const'
- area of a module to a memory space in physical RAM.
- Available memory areas are declared in the 'Target' tab of the 'Options for Target'
- dialog.
-*/
-#define __RAM_FUNC
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
- ---------------
- RAM functions are defined using a specific toolchain keyword "__ramfunc".
-*/
-#define __RAM_FUNC __ramfunc
-
-#elif defined ( __GNUC__ )
-/* GNU Compiler
- ------------
- RAM functions are defined using a specific toolchain attribute
- "__attribute__((section(".RamFunc")))".
-*/
-#define __RAM_FUNC __attribute__((section(".RamFunc")))
-
-#endif
-
-/**
- * @brief __NOINLINE definition
- */
-#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
-/* ARM V4/V5 and V6 & GNU Compiler
- -------------------------------
-*/
-#define __NOINLINE __attribute__ ( (noinline) )
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
- ---------------
-*/
-#define __NOINLINE _Pragma("optimize = no_inline")
-
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L4xx_HAL_DEF_H */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h
deleted file mode 100644
index f354c4f..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h
+++ /dev/null
@@ -1,861 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_dma.h
- * @author MCD Application Team
- * @brief Header file of DMA HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L4xx_HAL_DMA_H
-#define STM32L4xx_HAL_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DMA
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DMA_Exported_Types DMA Exported Types
- * @{
- */
-
-/**
- * @brief DMA Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Request; /*!< Specifies the request selected for the specified channel.
- This parameter can be a value of @ref DMA_request */
-
- uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
- from memory to memory or from peripheral to memory.
- This parameter can be a value of @ref DMA_Data_transfer_direction */
-
- uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
- This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
-
- uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
- This parameter can be a value of @ref DMA_Memory_incremented_mode */
-
- uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
- This parameter can be a value of @ref DMA_Peripheral_data_size */
-
- uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
- This parameter can be a value of @ref DMA_Memory_data_size */
-
- uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
- This parameter can be a value of @ref DMA_mode
- @note The circular buffer mode cannot be used if the memory-to-memory
- data transfer is configured on the selected Channel */
-
- uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
- This parameter can be a value of @ref DMA_Priority_level */
-} DMA_InitTypeDef;
-
-/**
- * @brief HAL DMA State structures definition
- */
-typedef enum
-{
- HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
- HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
- HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
- HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
-}HAL_DMA_StateTypeDef;
-
-/**
- * @brief HAL DMA Error Code structure definition
- */
-typedef enum
-{
- HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
- HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
-}HAL_DMA_LevelCompleteTypeDef;
-
-
-/**
- * @brief HAL DMA Callback ID structure definition
- */
-typedef enum
-{
- HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
- HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
- HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
- HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
- HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
-}HAL_DMA_CallbackIDTypeDef;
-
-/**
- * @brief DMA handle Structure definition
- */
-typedef struct __DMA_HandleTypeDef
-{
- DMA_Channel_TypeDef *Instance; /*!< Register base address */
-
- DMA_InitTypeDef Init; /*!< DMA communication parameters */
-
- HAL_LockTypeDef Lock; /*!< DMA locking object */
-
- __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
-
- void *Parent; /*!< Parent object state */
-
- void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
-
- void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
-
- void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
-
- void (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
-
- __IO uint32_t ErrorCode; /*!< DMA Error code */
-
- DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
-
- uint32_t ChannelIndex; /*!< DMA Channel Index */
-
-#if defined(DMAMUX1)
- DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */
-
- DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */
-
- uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */
-
- DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */
-
- DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */
-
- uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */
-
-#endif /* DMAMUX1 */
-
-}DMA_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants DMA Exported Constants
- * @{
- */
-
-/** @defgroup DMA_Error_Code DMA Error Code
- * @{
- */
-#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
-#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */
-#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
-#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
-#define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */
-#define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */
-
-/**
- * @}
- */
-
-/** @defgroup DMA_request DMA request
- * @{
- */
-#if !defined (DMAMUX1)
-
-#define DMA_REQUEST_0 0U
-#define DMA_REQUEST_1 1U
-#define DMA_REQUEST_2 2U
-#define DMA_REQUEST_3 3U
-#define DMA_REQUEST_4 4U
-#define DMA_REQUEST_5 5U
-#define DMA_REQUEST_6 6U
-#define DMA_REQUEST_7 7U
-
-#endif
-
-#if defined(DMAMUX1)
-
-#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */
-
-#define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */
-#define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */
-#define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */
-#define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */
-
-#define DMA_REQUEST_ADC1 5U /*!< DMAMUX1 ADC1 request */
-
-#if defined (STM32L4P5xx) || defined (STM32L4Q5xx)
-
-#define DMA_REQUEST_ADC2 6U /*!< DMAMUX1 ADC1 request */
-
-#define DMA_REQUEST_DAC1_CH1 7U /*!< DMAMUX1 DAC1 CH1 request */
-#define DMA_REQUEST_DAC1_CH2 8U /*!< DMAMUX1 DAC1 CH2 request */
-
-#define DMA_REQUEST_TIM6_UP 9U /*!< DMAMUX1 TIM6 UP request */
-#define DMA_REQUEST_TIM7_UP 10U /*!< DMAMUX1 TIM7 UP request */
-
-#define DMA_REQUEST_SPI1_RX 11U /*!< DMAMUX1 SPI1 RX request */
-#define DMA_REQUEST_SPI1_TX 12U /*!< DMAMUX1 SPI1 TX request */
-#define DMA_REQUEST_SPI2_RX 13U /*!< DMAMUX1 SPI2 RX request */
-#define DMA_REQUEST_SPI2_TX 14U /*!< DMAMUX1 SPI2 TX request */
-#define DMA_REQUEST_SPI3_RX 15U /*!< DMAMUX1 SPI3 RX request */
-#define DMA_REQUEST_SPI3_TX 16U /*!< DMAMUX1 SPI3 TX request */
-
-#define DMA_REQUEST_I2C1_RX 17U /*!< DMAMUX1 I2C1 RX request */
-#define DMA_REQUEST_I2C1_TX 18U /*!< DMAMUX1 I2C1 TX request */
-#define DMA_REQUEST_I2C2_RX 19U /*!< DMAMUX1 I2C2 RX request */
-#define DMA_REQUEST_I2C2_TX 20U /*!< DMAMUX1 I2C2 TX request */
-#define DMA_REQUEST_I2C3_RX 21U /*!< DMAMUX1 I2C3 RX request */
-#define DMA_REQUEST_I2C3_TX 22U /*!< DMAMUX1 I2C3 TX request */
-#define DMA_REQUEST_I2C4_RX 23U /*!< DMAMUX1 I2C4 RX request */
-#define DMA_REQUEST_I2C4_TX 24U /*!< DMAMUX1 I2C4 TX request */
-
-#define DMA_REQUEST_USART1_RX 25U /*!< DMAMUX1 USART1 RX request */
-#define DMA_REQUEST_USART1_TX 26U /*!< DMAMUX1 USART1 TX request */
-#define DMA_REQUEST_USART2_RX 27U /*!< DMAMUX1 USART2 RX request */
-#define DMA_REQUEST_USART2_TX 28U /*!< DMAMUX1 USART2 TX request */
-#define DMA_REQUEST_USART3_RX 29U /*!< DMAMUX1 USART3 RX request */
-#define DMA_REQUEST_USART3_TX 30U /*!< DMAMUX1 USART3 TX request */
-
-#define DMA_REQUEST_UART4_RX 31U /*!< DMAMUX1 UART4 RX request */
-#define DMA_REQUEST_UART4_TX 32U /*!< DMAMUX1 UART4 TX request */
-#define DMA_REQUEST_UART5_RX 33U /*!< DMAMUX1 UART5 RX request */
-#define DMA_REQUEST_UART5_TX 34U /*!< DMAMUX1 UART5 TX request */
-
-#define DMA_REQUEST_LPUART1_RX 35U /*!< DMAMUX1 LP_UART1_RX request */
-#define DMA_REQUEST_LPUART1_TX 36U /*!< DMAMUX1 LP_UART1_RX request */
-
-#define DMA_REQUEST_SAI1_A 37U /*!< DMAMUX1 SAI1 A request */
-#define DMA_REQUEST_SAI1_B 38U /*!< DMAMUX1 SAI1 B request */
-#define DMA_REQUEST_SAI2_A 39U /*!< DMAMUX1 SAI2 A request */
-#define DMA_REQUEST_SAI2_B 40U /*!< DMAMUX1 SAI2 B request */
-
-#define DMA_REQUEST_OCTOSPI1 41U /*!< DMAMUX1 OCTOSPI1 request */
-#define DMA_REQUEST_OCTOSPI2 42U /*!< DMAMUX1 OCTOSPI2 request */
-
-#define DMA_REQUEST_TIM1_CH1 43U /*!< DMAMUX1 TIM1 CH1 request */
-#define DMA_REQUEST_TIM1_CH2 44U /*!< DMAMUX1 TIM1 CH2 request */
-#define DMA_REQUEST_TIM1_CH3 45U /*!< DMAMUX1 TIM1 CH3 request */
-#define DMA_REQUEST_TIM1_CH4 46U /*!< DMAMUX1 TIM1 CH4 request */
-#define DMA_REQUEST_TIM1_UP 47U /*!< DMAMUX1 TIM1 UP request */
-#define DMA_REQUEST_TIM1_TRIG 48U /*!< DMAMUX1 TIM1 TRIG request */
-#define DMA_REQUEST_TIM1_COM 49U /*!< DMAMUX1 TIM1 COM request */
-
-#define DMA_REQUEST_TIM8_CH1 50U /*!< DMAMUX1 TIM8 CH1 request */
-#define DMA_REQUEST_TIM8_CH2 51U /*!< DMAMUX1 TIM8 CH2 request */
-#define DMA_REQUEST_TIM8_CH3 52U /*!< DMAMUX1 TIM8 CH3 request */
-#define DMA_REQUEST_TIM8_CH4 53U /*!< DMAMUX1 TIM8 CH4 request */
-#define DMA_REQUEST_TIM8_UP 54U /*!< DMAMUX1 TIM8 UP request */
-#define DMA_REQUEST_TIM8_TRIG 55U /*!< DMAMUX1 TIM8 TRIG request */
-#define DMA_REQUEST_TIM8_COM 56U /*!< DMAMUX1 TIM8 COM request */
-
-#define DMA_REQUEST_TIM2_CH1 57U /*!< DMAMUX1 TIM2 CH1 request */
-#define DMA_REQUEST_TIM2_CH2 58U /*!< DMAMUX1 TIM2 CH2 request */
-#define DMA_REQUEST_TIM2_CH3 59U /*!< DMAMUX1 TIM2 CH3 request */
-#define DMA_REQUEST_TIM2_CH4 60U /*!< DMAMUX1 TIM2 CH4 request */
-#define DMA_REQUEST_TIM2_UP 61U /*!< DMAMUX1 TIM2 UP request */
-
-#define DMA_REQUEST_TIM3_CH1 62U /*!< DMAMUX1 TIM3 CH1 request */
-#define DMA_REQUEST_TIM3_CH2 63U /*!< DMAMUX1 TIM3 CH2 request */
-#define DMA_REQUEST_TIM3_CH3 64U /*!< DMAMUX1 TIM3 CH3 request */
-#define DMA_REQUEST_TIM3_CH4 65U /*!< DMAMUX1 TIM3 CH4 request */
-#define DMA_REQUEST_TIM3_UP 66U /*!< DMAMUX1 TIM3 UP request */
-#define DMA_REQUEST_TIM3_TRIG 67U /*!< DMAMUX1 TIM3 TRIG request */
-
-#define DMA_REQUEST_TIM4_CH1 68U /*!< DMAMUX1 TIM4 CH1 request */
-#define DMA_REQUEST_TIM4_CH2 69U /*!< DMAMUX1 TIM4 CH2 request */
-#define DMA_REQUEST_TIM4_CH3 70U /*!< DMAMUX1 TIM4 CH3 request */
-#define DMA_REQUEST_TIM4_CH4 71U /*!< DMAMUX1 TIM4 CH4 request */
-#define DMA_REQUEST_TIM4_UP 72U /*!< DMAMUX1 TIM4 UP request */
-
-#define DMA_REQUEST_TIM5_CH1 73U /*!< DMAMUX1 TIM5 CH1 request */
-#define DMA_REQUEST_TIM5_CH2 74U /*!< DMAMUX1 TIM5 CH2 request */
-#define DMA_REQUEST_TIM5_CH3 75U /*!< DMAMUX1 TIM5 CH3 request */
-#define DMA_REQUEST_TIM5_CH4 76U /*!< DMAMUX1 TIM5 CH4 request */
-#define DMA_REQUEST_TIM5_UP 77U /*!< DMAMUX1 TIM5 UP request */
-#define DMA_REQUEST_TIM5_TRIG 78U /*!< DMAMUX1 TIM5 TRIG request */
-
-#define DMA_REQUEST_TIM15_CH1 79U /*!< DMAMUX1 TIM15 CH1 request */
-#define DMA_REQUEST_TIM15_UP 80U /*!< DMAMUX1 TIM15 UP request */
-#define DMA_REQUEST_TIM15_TRIG 81U /*!< DMAMUX1 TIM15 TRIG request */
-#define DMA_REQUEST_TIM15_COM 82U /*!< DMAMUX1 TIM15 COM request */
-
-#define DMA_REQUEST_TIM16_CH1 83U /*!< DMAMUX1 TIM16 CH1 request */
-#define DMA_REQUEST_TIM16_UP 84U /*!< DMAMUX1 TIM16 UP request */
-#define DMA_REQUEST_TIM17_CH1 85U /*!< DMAMUX1 TIM17 CH1 request */
-#define DMA_REQUEST_TIM17_UP 86U /*!< DMAMUX1 TIM17 UP request */
-
-#define DMA_REQUEST_DFSDM1_FLT0 87U /*!< DMAMUX1 DFSDM1 Filter0 request */
-#define DMA_REQUEST_DFSDM1_FLT1 88U /*!< DMAMUX1 DFSDM1 Filter1 request */
-
-#define DMA_REQUEST_DCMI 91U /*!< DMAMUX1 DCMI request */
-#define DMA_REQUEST_DCMI_PSSI 91U /*!< DMAMUX1 DCMI/PSSI request */
-
-#define DMA_REQUEST_AES_IN 92U /*!< DMAMUX1 AES IN request */
-#define DMA_REQUEST_AES_OUT 93U /*!< DMAMUX1 AES OUT request */
-
-#define DMA_REQUEST_HASH_IN 94U /*!< DMAMUX1 HASH IN request */
-
-#else
-
-#define DMA_REQUEST_DAC1_CH1 6U /*!< DMAMUX1 DAC1 CH1 request */
-#define DMA_REQUEST_DAC1_CH2 7U /*!< DMAMUX1 DAC1 CH2 request */
-
-#define DMA_REQUEST_TIM6_UP 8U /*!< DMAMUX1 TIM6 UP request */
-#define DMA_REQUEST_TIM7_UP 9U /*!< DMAMUX1 TIM7 UP request */
-
-#define DMA_REQUEST_SPI1_RX 10U /*!< DMAMUX1 SPI1 RX request */
-#define DMA_REQUEST_SPI1_TX 11U /*!< DMAMUX1 SPI1 TX request */
-#define DMA_REQUEST_SPI2_RX 12U /*!< DMAMUX1 SPI2 RX request */
-#define DMA_REQUEST_SPI2_TX 13U /*!< DMAMUX1 SPI2 TX request */
-#define DMA_REQUEST_SPI3_RX 14U /*!< DMAMUX1 SPI3 RX request */
-#define DMA_REQUEST_SPI3_TX 15U /*!< DMAMUX1 SPI3 TX request */
-
-#define DMA_REQUEST_I2C1_RX 16U /*!< DMAMUX1 I2C1 RX request */
-#define DMA_REQUEST_I2C1_TX 17U /*!< DMAMUX1 I2C1 TX request */
-#define DMA_REQUEST_I2C2_RX 18U /*!< DMAMUX1 I2C2 RX request */
-#define DMA_REQUEST_I2C2_TX 19U /*!< DMAMUX1 I2C2 TX request */
-#define DMA_REQUEST_I2C3_RX 20U /*!< DMAMUX1 I2C3 RX request */
-#define DMA_REQUEST_I2C3_TX 21U /*!< DMAMUX1 I2C3 TX request */
-#define DMA_REQUEST_I2C4_RX 22U /*!< DMAMUX1 I2C4 RX request */
-#define DMA_REQUEST_I2C4_TX 23U /*!< DMAMUX1 I2C4 TX request */
-
-#define DMA_REQUEST_USART1_RX 24U /*!< DMAMUX1 USART1 RX request */
-#define DMA_REQUEST_USART1_TX 25U /*!< DMAMUX1 USART1 TX request */
-#define DMA_REQUEST_USART2_RX 26U /*!< DMAMUX1 USART2 RX request */
-#define DMA_REQUEST_USART2_TX 27U /*!< DMAMUX1 USART2 TX request */
-#define DMA_REQUEST_USART3_RX 28U /*!< DMAMUX1 USART3 RX request */
-#define DMA_REQUEST_USART3_TX 29U /*!< DMAMUX1 USART3 TX request */
-
-#define DMA_REQUEST_UART4_RX 30U /*!< DMAMUX1 UART4 RX request */
-#define DMA_REQUEST_UART4_TX 31U /*!< DMAMUX1 UART4 TX request */
-#define DMA_REQUEST_UART5_RX 32U /*!< DMAMUX1 UART5 RX request */
-#define DMA_REQUEST_UART5_TX 33U /*!< DMAMUX1 UART5 TX request */
-
-#define DMA_REQUEST_LPUART1_RX 34U /*!< DMAMUX1 LP_UART1_RX request */
-#define DMA_REQUEST_LPUART1_TX 35U /*!< DMAMUX1 LP_UART1_RX request */
-
-#define DMA_REQUEST_SAI1_A 36U /*!< DMAMUX1 SAI1 A request */
-#define DMA_REQUEST_SAI1_B 37U /*!< DMAMUX1 SAI1 B request */
-#define DMA_REQUEST_SAI2_A 38U /*!< DMAMUX1 SAI2 A request */
-#define DMA_REQUEST_SAI2_B 39U /*!< DMAMUX1 SAI2 B request */
-
-#define DMA_REQUEST_OCTOSPI1 40U /*!< DMAMUX1 OCTOSPI1 request */
-#define DMA_REQUEST_OCTOSPI2 41U /*!< DMAMUX1 OCTOSPI2 request */
-
-#define DMA_REQUEST_TIM1_CH1 42U /*!< DMAMUX1 TIM1 CH1 request */
-#define DMA_REQUEST_TIM1_CH2 43U /*!< DMAMUX1 TIM1 CH2 request */
-#define DMA_REQUEST_TIM1_CH3 44U /*!< DMAMUX1 TIM1 CH3 request */
-#define DMA_REQUEST_TIM1_CH4 45U /*!< DMAMUX1 TIM1 CH4 request */
-#define DMA_REQUEST_TIM1_UP 46U /*!< DMAMUX1 TIM1 UP request */
-#define DMA_REQUEST_TIM1_TRIG 47U /*!< DMAMUX1 TIM1 TRIG request */
-#define DMA_REQUEST_TIM1_COM 48U /*!< DMAMUX1 TIM1 COM request */
-
-#define DMA_REQUEST_TIM8_CH1 49U /*!< DMAMUX1 TIM8 CH1 request */
-#define DMA_REQUEST_TIM8_CH2 50U /*!< DMAMUX1 TIM8 CH2 request */
-#define DMA_REQUEST_TIM8_CH3 51U /*!< DMAMUX1 TIM8 CH3 request */
-#define DMA_REQUEST_TIM8_CH4 52U /*!< DMAMUX1 TIM8 CH4 request */
-#define DMA_REQUEST_TIM8_UP 53U /*!< DMAMUX1 TIM8 UP request */
-#define DMA_REQUEST_TIM8_TRIG 54U /*!< DMAMUX1 TIM8 TRIG request */
-#define DMA_REQUEST_TIM8_COM 55U /*!< DMAMUX1 TIM8 COM request */
-
-#define DMA_REQUEST_TIM2_CH1 56U /*!< DMAMUX1 TIM2 CH1 request */
-#define DMA_REQUEST_TIM2_CH2 57U /*!< DMAMUX1 TIM2 CH2 request */
-#define DMA_REQUEST_TIM2_CH3 58U /*!< DMAMUX1 TIM2 CH3 request */
-#define DMA_REQUEST_TIM2_CH4 59U /*!< DMAMUX1 TIM2 CH4 request */
-#define DMA_REQUEST_TIM2_UP 60U /*!< DMAMUX1 TIM2 UP request */
-
-#define DMA_REQUEST_TIM3_CH1 61U /*!< DMAMUX1 TIM3 CH1 request */
-#define DMA_REQUEST_TIM3_CH2 62U /*!< DMAMUX1 TIM3 CH2 request */
-#define DMA_REQUEST_TIM3_CH3 63U /*!< DMAMUX1 TIM3 CH3 request */
-#define DMA_REQUEST_TIM3_CH4 64U /*!< DMAMUX1 TIM3 CH4 request */
-#define DMA_REQUEST_TIM3_UP 65U /*!< DMAMUX1 TIM3 UP request */
-#define DMA_REQUEST_TIM3_TRIG 66U /*!< DMAMUX1 TIM3 TRIG request */
-
-#define DMA_REQUEST_TIM4_CH1 67U /*!< DMAMUX1 TIM4 CH1 request */
-#define DMA_REQUEST_TIM4_CH2 68U /*!< DMAMUX1 TIM4 CH2 request */
-#define DMA_REQUEST_TIM4_CH3 69U /*!< DMAMUX1 TIM4 CH3 request */
-#define DMA_REQUEST_TIM4_CH4 70U /*!< DMAMUX1 TIM4 CH4 request */
-#define DMA_REQUEST_TIM4_UP 71U /*!< DMAMUX1 TIM4 UP request */
-
-#define DMA_REQUEST_TIM5_CH1 72U /*!< DMAMUX1 TIM5 CH1 request */
-#define DMA_REQUEST_TIM5_CH2 73U /*!< DMAMUX1 TIM5 CH2 request */
-#define DMA_REQUEST_TIM5_CH3 74U /*!< DMAMUX1 TIM5 CH3 request */
-#define DMA_REQUEST_TIM5_CH4 75U /*!< DMAMUX1 TIM5 CH4 request */
-#define DMA_REQUEST_TIM5_UP 76U /*!< DMAMUX1 TIM5 UP request */
-#define DMA_REQUEST_TIM5_TRIG 77U /*!< DMAMUX1 TIM5 TRIG request */
-
-#define DMA_REQUEST_TIM15_CH1 78U /*!< DMAMUX1 TIM15 CH1 request */
-#define DMA_REQUEST_TIM15_UP 79U /*!< DMAMUX1 TIM15 UP request */
-#define DMA_REQUEST_TIM15_TRIG 80U /*!< DMAMUX1 TIM15 TRIG request */
-#define DMA_REQUEST_TIM15_COM 81U /*!< DMAMUX1 TIM15 COM request */
-
-#define DMA_REQUEST_TIM16_CH1 82U /*!< DMAMUX1 TIM16 CH1 request */
-#define DMA_REQUEST_TIM16_UP 83U /*!< DMAMUX1 TIM16 UP request */
-#define DMA_REQUEST_TIM17_CH1 84U /*!< DMAMUX1 TIM17 CH1 request */
-#define DMA_REQUEST_TIM17_UP 85U /*!< DMAMUX1 TIM17 UP request */
-
-#define DMA_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX1 DFSDM1 Filter0 request */
-#define DMA_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX1 DFSDM1 Filter1 request */
-#define DMA_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX1 DFSDM1 Filter2 request */
-#define DMA_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX1 DFSDM1 Filter3 request */
-
-#define DMA_REQUEST_DCMI 90U /*!< DMAMUX1 DCMI request */
-
-#define DMA_REQUEST_AES_IN 91U /*!< DMAMUX1 AES IN request */
-#define DMA_REQUEST_AES_OUT 92U /*!< DMAMUX1 AES OUT request */
-
-#define DMA_REQUEST_HASH_IN 93U /*!< DMAMUX1 HASH IN request */
-#endif /* STM32L4P5xx || STM32L4Q5xx */
-
-#endif /* DMAMUX1 */
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
- * @{
- */
-#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
-#define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
-#define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
-/**
- * @}
- */
-
-/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
- * @{
- */
-#define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */
-#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
- * @{
- */
-#define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */
-#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
- * @{
- */
-#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
-#define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
-#define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_Memory_data_size DMA Memory data size
- * @{
- */
-#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
-#define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
-#define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_mode DMA mode
- * @{
- */
-#define DMA_NORMAL 0x00000000U /*!< Normal mode */
-#define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */
-/**
- * @}
- */
-
-/** @defgroup DMA_Priority_level DMA Priority level
- * @{
- */
-#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
-#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
-#define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
-#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */
-/**
- * @}
- */
-
-
-/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
- * @{
- */
-#define DMA_IT_TC DMA_CCR_TCIE
-#define DMA_IT_HT DMA_CCR_HTIE
-#define DMA_IT_TE DMA_CCR_TEIE
-/**
- * @}
- */
-
-/** @defgroup DMA_flag_definitions DMA flag definitions
- * @{
- */
-#define DMA_FLAG_GL1 DMA_ISR_GIF1
-#define DMA_FLAG_TC1 DMA_ISR_TCIF1
-#define DMA_FLAG_HT1 DMA_ISR_HTIF1
-#define DMA_FLAG_TE1 DMA_ISR_TEIF1
-#define DMA_FLAG_GL2 DMA_ISR_GIF2
-#define DMA_FLAG_TC2 DMA_ISR_TCIF2
-#define DMA_FLAG_HT2 DMA_ISR_HTIF2
-#define DMA_FLAG_TE2 DMA_ISR_TEIF2
-#define DMA_FLAG_GL3 DMA_ISR_GIF3
-#define DMA_FLAG_TC3 DMA_ISR_TCIF3
-#define DMA_FLAG_HT3 DMA_ISR_HTIF3
-#define DMA_FLAG_TE3 DMA_ISR_TEIF3
-#define DMA_FLAG_GL4 DMA_ISR_GIF4
-#define DMA_FLAG_TC4 DMA_ISR_TCIF4
-#define DMA_FLAG_HT4 DMA_ISR_HTIF4
-#define DMA_FLAG_TE4 DMA_ISR_TEIF4
-#define DMA_FLAG_GL5 DMA_ISR_GIF5
-#define DMA_FLAG_TC5 DMA_ISR_TCIF5
-#define DMA_FLAG_HT5 DMA_ISR_HTIF5
-#define DMA_FLAG_TE5 DMA_ISR_TEIF5
-#define DMA_FLAG_GL6 DMA_ISR_GIF6
-#define DMA_FLAG_TC6 DMA_ISR_TCIF6
-#define DMA_FLAG_HT6 DMA_ISR_HTIF6
-#define DMA_FLAG_TE6 DMA_ISR_TEIF6
-#define DMA_FLAG_GL7 DMA_ISR_GIF7
-#define DMA_FLAG_TC7 DMA_ISR_TCIF7
-#define DMA_FLAG_HT7 DMA_ISR_HTIF7
-#define DMA_FLAG_TE7 DMA_ISR_TEIF7
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup DMA_Exported_Macros DMA Exported Macros
- * @{
- */
-
-/** @brief Reset DMA handle state.
- * @param __HANDLE__ DMA handle
- * @retval None
- */
-#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
-
-/**
- * @brief Enable the specified DMA Channel.
- * @param __HANDLE__ DMA handle
- * @retval None
- */
-#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
-
-/**
- * @brief Disable the specified DMA Channel.
- * @param __HANDLE__ DMA handle
- * @retval None
- */
-#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
-
-
-/* Interrupt & Flag management */
-
-/**
- * @brief Return the current DMA Channel transfer complete flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified transfer complete flag index.
- */
-
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
- DMA_FLAG_TC7)
-
-/**
- * @brief Return the current DMA Channel half transfer complete flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified half transfer complete flag index.
- */
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
- DMA_FLAG_HT7)
-
-/**
- * @brief Return the current DMA Channel transfer error flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified transfer error flag index.
- */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
- DMA_FLAG_TE7)
-
-/**
- * @brief Return the current DMA Channel Global interrupt flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified transfer error flag index.
- */
-#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
- DMA_ISR_GIF7)
-
-/**
- * @brief Get the DMA Channel pending flags.
- * @param __HANDLE__ DMA handle
- * @param __FLAG__ Get the specified flag.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCx: Transfer complete flag
- * @arg DMA_FLAG_HTx: Half transfer complete flag
- * @arg DMA_FLAG_TEx: Transfer error flag
- * @arg DMA_FLAG_GLx: Global interrupt flag
- * Where x can be from 1 to 7 to select the DMA Channel x flag.
- * @retval The state of FLAG (SET or RESET).
- */
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
- (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
-
-/**
- * @brief Clear the DMA Channel pending flags.
- * @param __HANDLE__ DMA handle
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCx: Transfer complete flag
- * @arg DMA_FLAG_HTx: Half transfer complete flag
- * @arg DMA_FLAG_TEx: Transfer error flag
- * @arg DMA_FLAG_GLx: Global interrupt flag
- * Where x can be from 1 to 7 to select the DMA Channel x flag.
- * @retval None
- */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
- (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
-
-/**
- * @brief Enable the specified DMA Channel interrupts.
- * @param __HANDLE__ DMA handle
- * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer complete interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @retval None
- */
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the specified DMA Channel interrupts.
- * @param __HANDLE__ DMA handle
- * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer complete interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @retval None
- */
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
-
-/**
- * @brief Check whether the specified DMA Channel interrupt is enabled or not.
- * @param __HANDLE__ DMA handle
- * @param __INTERRUPT__ specifies the DMA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer complete interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @retval The state of DMA_IT (SET or RESET).
- */
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
-
-/**
- * @brief Return the number of remaining data units in the current DMA Channel transfer.
- * @param __HANDLE__ DMA handle
- * @retval The number of remaining data units in the current DMA Channel transfer.
- */
-#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
-
-/**
- * @}
- */
-
-#if defined(DMAMUX1)
-/* Include DMA HAL Extension module */
-#include "stm32l4xx_hal_dma_ex.h"
-#endif /* DMAMUX1 */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup DMA_Exported_Functions
- * @{
- */
-
-/** @addtogroup DMA_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/** @addtogroup DMA_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
-
-/**
- * @}
- */
-
-/** @addtogroup DMA_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMA_Private_Macros DMA Private Macros
- * @{
- */
-
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
- ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
- ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
-
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
- ((STATE) == DMA_PINC_DISABLE))
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
- ((STATE) == DMA_MINC_DISABLE))
-
-#if !defined (DMAMUX1)
-
-#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
- ((REQUEST) == DMA_REQUEST_1) || \
- ((REQUEST) == DMA_REQUEST_2) || \
- ((REQUEST) == DMA_REQUEST_3) || \
- ((REQUEST) == DMA_REQUEST_4) || \
- ((REQUEST) == DMA_REQUEST_5) || \
- ((REQUEST) == DMA_REQUEST_6) || \
- ((REQUEST) == DMA_REQUEST_7))
-#endif
-
-#if defined(DMAMUX1)
-
-#define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_HASH_IN)
-
-#endif /* DMAMUX1 */
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
- ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_PDATAALIGN_WORD))
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
- ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_MDATAALIGN_WORD ))
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
- ((MODE) == DMA_CIRCULAR))
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
- ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
- ((PRIORITY) == DMA_PRIORITY_HIGH) || \
- ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L4xx_HAL_DMA_H */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h
deleted file mode 100644
index 77b89df..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h
+++ /dev/null
@@ -1,284 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_dma_ex.h
- * @author MCD Application Team
- * @brief Header file of DMA HAL extension module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L4xx_HAL_DMA_EX_H
-#define STM32L4xx_HAL_DMA_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(DMAMUX1)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DMAEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
- * @{
- */
-
-/**
- * @brief HAL DMA Synchro definition
- */
-
-
-/**
- * @brief HAL DMAMUX Synchronization configuration structure definition
- */
-typedef struct
-{
- uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
- This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */
-
- uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
- This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
-
- FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled
- This parameter can take the value ENABLE or DISABLE*/
-
-
- FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached.
- This parameter can take the value ENABLE or DISABLE */
-
- uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event
- This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
-
-
-}HAL_DMA_MuxSyncConfigTypeDef;
-
-
-/**
- * @brief HAL DMAMUX request generator parameters structure definition
- */
-typedef struct
-{
- uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator
- This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
-
- uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated.
- This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
-
- uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event
- This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
-
-}HAL_DMA_MuxRequestGeneratorConfigTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
- * @{
- */
-
-/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
- * @{
- */
-#define HAL_DMAMUX1_SYNC_EXTI0 0U /*!< Synchronization Signal is EXTI0 IT */
-#define HAL_DMAMUX1_SYNC_EXTI1 1U /*!< Synchronization Signal is EXTI1 IT */
-#define HAL_DMAMUX1_SYNC_EXTI2 2U /*!< Synchronization Signal is EXTI2 IT */
-#define HAL_DMAMUX1_SYNC_EXTI3 3U /*!< Synchronization Signal is EXTI3 IT */
-#define HAL_DMAMUX1_SYNC_EXTI4 4U /*!< Synchronization Signal is EXTI4 IT */
-#define HAL_DMAMUX1_SYNC_EXTI5 5U /*!< Synchronization Signal is EXTI5 IT */
-#define HAL_DMAMUX1_SYNC_EXTI6 6U /*!< Synchronization Signal is EXTI6 IT */
-#define HAL_DMAMUX1_SYNC_EXTI7 7U /*!< Synchronization Signal is EXTI7 IT */
-#define HAL_DMAMUX1_SYNC_EXTI8 8U /*!< Synchronization Signal is EXTI8 IT */
-#define HAL_DMAMUX1_SYNC_EXTI9 9U /*!< Synchronization Signal is EXTI9 IT */
-#define HAL_DMAMUX1_SYNC_EXTI10 10U /*!< Synchronization Signal is EXTI10 IT */
-#define HAL_DMAMUX1_SYNC_EXTI11 11U /*!< Synchronization Signal is EXTI11 IT */
-#define HAL_DMAMUX1_SYNC_EXTI12 12U /*!< Synchronization Signal is EXTI12 IT */
-#define HAL_DMAMUX1_SYNC_EXTI13 13U /*!< Synchronization Signal is EXTI13 IT */
-#define HAL_DMAMUX1_SYNC_EXTI14 14U /*!< Synchronization Signal is EXTI14 IT */
-#define HAL_DMAMUX1_SYNC_EXTI15 15U /*!< Synchronization Signal is EXTI15 IT */
-#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */
-#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */
-#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */
-#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */
-#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 20U /*!< Synchronization Signal is LPTIM1 OUT */
-#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 21U /*!< Synchronization Signal is LPTIM2 OUT */
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define HAL_DMAMUX1_SYNC_DSI_TE 22U /*!< Synchronization Signal is DSI Tearing Effect */
-#define HAL_DMAMUX1_SYNC_DSI_EOT 23U /*!< Synchronization Signal is DSI End of refresh */
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-#define HAL_DMAMUX1_SYNC_DMA2D_EOT 24U /*!< Synchronization Signal is DMA2D End of Transfer */
-#define HAL_DMAMUX1_SYNC_LDTC_IT 25U /*!< Synchronization Signal is LDTC IT */
-
-/**
- * @}
- */
-
-/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
- * @{
- */
-#define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */
-#define HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0 /*!< synchronize with rising edge events */
-#define HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1 /*!< synchronize with falling edge events */
-#define HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL /*!< synchronize with rising and falling edge events */
-
-/**
- * @}
- */
-
-/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection
- * @{
- */
-
-#define HAL_DMAMUX1_REQ_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */
-#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */
-#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */
-#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */
-#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */
-#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */
-#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 21U /*!< Request generator Signal is LPTIM2 OUT */
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define HAL_DMAMUX1_REQ_GEN_DSI_TE 22U /*!< Request generator Signal is DSI Tearing Effect */
-#define HAL_DMAMUX1_REQ_GEN_DSI_EOT 23U /*!< Request generator Signal is DSI End of refresh */
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-#define HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 24U /*!< Request generator Signal is DMA2D End of Transfer */
-#define HAL_DMAMUX1_REQ_GEN_LTDC_IT 25U /*!< Request generator Signal is LTDC IT */
-
-/**
- * @}
- */
-
-/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection
- * @{
- */
-#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0U /*!< block request generator events */
-#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */
-#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */
-#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMAEx_Exported_Functions
- * @{
- */
-
-/* IO operation functions *****************************************************/
-/** @addtogroup DMAEx_Exported_Functions_Group1
- * @{
- */
-
-/* ------------------------- REQUEST -----------------------------------------*/
-HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma,
- HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
-HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
-/* -------------------------------------------------------------------------- */
-
-/* ------------------------- SYNCHRO -----------------------------------------*/
-HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
-/* -------------------------------------------------------------------------- */
-
-void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Private defines -----------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
- * @brief DMAEx private macros
- * @{
- */
-
-#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LDTC_IT)
-
-#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
-
-#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
- ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \
- ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \
- ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
-
-#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
-
-#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \
- ((EVENT) == ENABLE))
-
-#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LTDC_IT)
-
-#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
-
-#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
- ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \
- ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
- ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DMAMUX1 */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L4xx_HAL_DMA_H */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h
deleted file mode 100644
index aa70f20..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h
+++ /dev/null
@@ -1,858 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_exti.h
- * @author MCD Application Team
- * @brief Header file of EXTI HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L4xx_HAL_EXTI_H
-#define STM32L4xx_HAL_EXTI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup EXTI EXTI
- * @brief EXTI HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup EXTI_Exported_Types EXTI Exported Types
- * @{
- */
-typedef enum
-{
- HAL_EXTI_COMMON_CB_ID = 0x00U,
- HAL_EXTI_RISING_CB_ID = 0x01U,
- HAL_EXTI_FALLING_CB_ID = 0x02U,
-} EXTI_CallbackIDTypeDef;
-
-
-/**
- * @brief EXTI Handle structure definition
- */
-typedef struct
-{
- uint32_t Line; /*!< Exti line number */
- void (* PendingCallback)(void); /*!< Exti pending callback */
-} EXTI_HandleTypeDef;
-
-/**
- * @brief EXTI Configuration structure definition
- */
-typedef struct
-{
- uint32_t Line; /*!< The Exti line to be configured. This parameter
- can be a value of @ref EXTI_Line */
- uint32_t Mode; /*!< The Exit Mode to be configured for a core.
- This parameter can be a combination of @ref EXTI_Mode */
- uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
- can be a value of @ref EXTI_Trigger */
- uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
- This parameter is only possible for line 0 to 15. It
- can be a value of @ref EXTI_GPIOSel */
-} EXTI_ConfigTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
- * @{
- */
-
-/** @defgroup EXTI_Line EXTI Line
- * @{
- */
-#if defined(STM32L412xx) || defined(STM32L422xx)
-
-#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
-#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
-#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
-#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
-#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
-#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
-#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
-#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
-#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
-#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
-#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
-#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
-#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
-#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
-#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
-#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
-#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
-#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
-#define EXTI_LINE_22 (EXTI_RESERVED | EXTI_REG1 | 0x16u)
-#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
-#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
-#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
-#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
-#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
-#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
-#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du)
-#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
-#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
-#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
-#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
-#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
-#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
-#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
-
-#endif /* STM32L412xx || STM32L422xx */
-
-#if defined(STM32L431xx)
-
-#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
-#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
-#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
-#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
-#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
-#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
-#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
-#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
-#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
-#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
-#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
-#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
-#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
-#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u)
-#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
-#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
-#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
-#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
-#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
-#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
-#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
-#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
-#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
-#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
-#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
-#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du)
-#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
-#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
-#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u)
-#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u)
-#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
-#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
-#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
-
-#endif /* STM32L431xx */
-
-#if defined(STM32L432xx) || defined(STM32L442xx)
-
-#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
-#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
-#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
-#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
-#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
-#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
-#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
-#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
-#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
-#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
-#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
-#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
-#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
-#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
-#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
-#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
-#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
-#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
-#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
-#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
-#define EXTI_LINE_24 (EXTI_RESERVED | EXTI_REG1 | 0x18u)
-#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
-#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
-#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
-#define EXTI_LINE_28 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu)
-#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du)
-#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
-#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
-#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u)
-#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
-#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
-#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u)
-#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
-
-#endif /* STM32L432xx || STM32L442xx */
-
-#if defined(STM32L433xx) || defined(STM32L443xx)
-
-#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
-#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
-#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
-#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
-#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
-#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
-#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
-#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
-#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
-#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
-#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
-#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
-#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
-#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
-#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
-#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
-#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
-#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
-#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
-#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
-#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
-#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
-#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
-#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
-#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
-#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du)
-#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
-#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
-#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u)
-#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
-#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
-#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u)
-#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
-
-#endif /* STM32L433xx || STM32L443xx */
-
-#if defined(STM32L451xx)
-
-#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
-#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
-#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
-#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
-#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
-#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
-#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
-#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
-#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
-#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
-#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
-#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
-#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
-#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u)
-#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
-#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
-#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
-#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
-#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
-#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
-#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
-#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
-#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
-#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
-#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
-#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
-#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
-#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
-#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
-#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u)
-#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
-#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
-#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u)
-
-#endif /* STM32L451xx */
-
-#if defined(STM32L452xx) || defined(STM32L462xx)
-
-#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
-#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
-#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
-#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
-#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
-#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
-#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
-#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
-#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
-#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
-#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
-#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
-#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
-#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
-#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
-#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
-#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
-#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
-#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
-#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
-#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
-#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
-#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
-#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
-#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
-#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
-#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
-#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
-#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
-#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
-#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
-#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
-#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u)
-
-#endif /* STM32L452xx || STM32L462xx */
-
-#if defined(STM32L471xx)
-
-#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
-#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
-#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
-#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
-#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
-#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
-#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
-#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
-#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
-#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
-#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
-#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
-#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
-#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u)
-#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
-#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
-#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
-#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
-#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
-#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
-#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
-#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
-#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
-#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
-#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
-#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
-#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu)
-#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
-#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x02u)
-#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u)
-#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u)
-#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
-#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
-
-#endif /* STM32L471xx */
-
-#if defined(STM32L475xx) || defined(STM32L485xx)
-
-#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
-#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
-#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
-#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
-#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
-#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
-#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
-#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
-#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
-#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
-#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
-#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
-#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
-#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
-#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
-#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
-#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
-#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
-#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
-#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
-#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
-#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
-#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
-#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
-#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
-#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
-#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu)
-#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
-#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x02u)
-#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
-#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u)
-#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
-#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
-
-#endif /* STM32L475xx || STM32L485xx */
-
-#if defined(STM32L476xx) || defined(STM32L486xx)
-
-#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
-#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
-#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
-#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
-#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
-#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
-#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
-#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
-#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
-#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
-#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
-#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
-#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
-#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
-#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
-#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
-#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
-#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
-#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
-#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
-#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
-#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
-#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
-#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
-#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
-#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
-#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu)
-#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
-#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x02u)
-#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
-#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u)
-#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u)
-#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
-
-#endif /* STM32L476xx || STM32L486xx */
-
-#if defined(STM32L496xx) || defined(STM32L4A6xx)
-
-#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
-#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
-#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
-#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
-#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
-#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
-#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
-#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
-#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
-#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
-#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
-#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
-#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
-#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
-#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
-#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
-#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
-#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
-#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
-#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
-#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
-#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
-#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
-#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
-#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
-#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
-#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu)
-#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
-#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u)
-#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
-#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u)
-#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u)
-#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u)
-
-#endif /* STM32L496xx || STM32L4A6xx */
-
-#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-
-#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
-#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
-#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
-#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
-#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
-#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
-#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
-#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
-#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
-#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
-#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
-#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
-#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
-#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
-#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
-#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
-#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
-#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
-#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
-#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
-#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
-#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
-#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
-#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
-#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
-#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
-#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu)
-#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
-#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
-#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
-#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
-#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
-#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u)
-#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
-#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
-#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
-#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u)
-
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_Mode EXTI Mode
- * @{
- */
-#define EXTI_MODE_NONE 0x00000000u
-#define EXTI_MODE_INTERRUPT 0x00000001u
-#define EXTI_MODE_EVENT 0x00000002u
-/**
- * @}
- */
-
-/** @defgroup EXTI_Trigger EXTI Trigger
- * @{
- */
-#define EXTI_TRIGGER_NONE 0x00000000u
-#define EXTI_TRIGGER_RISING 0x00000001u
-#define EXTI_TRIGGER_FALLING 0x00000002u
-#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
-/**
- * @}
- */
-
-/** @defgroup EXTI_GPIOSel EXTI GPIOSel
- * @brief
- * @{
- */
-#define EXTI_GPIOA 0x00000000u
-#define EXTI_GPIOB 0x00000001u
-#define EXTI_GPIOC 0x00000002u
-#define EXTI_GPIOD 0x00000003u
-#define EXTI_GPIOE 0x00000004u
-#define EXTI_GPIOF 0x00000005u
-#define EXTI_GPIOG 0x00000005u
-#define EXTI_GPIOH 0x00000007u
-#define EXTI_GPIOI 0x00000008u
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants --------------------------------------------------------*/
-/** @defgroup EXTI_Private_Constants EXTI Private Constants
- * @{
- */
-/**
- * @brief EXTI Line property definition
- */
-#define EXTI_PROPERTY_SHIFT 24u
-#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
-#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
-#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
-#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
-#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
-
-/**
- * @brief EXTI Event presence definition
- */
-#define EXTI_EVENT_PRESENCE_SHIFT 28u
-#define EXTI_EVENT (0x01uL << EXTI_EVENT_PRESENCE_SHIFT)
-#define EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT)
-
-/**
- * @brief EXTI Register and bit usage
- */
-#define EXTI_REG_SHIFT 16u
-#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
-#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
-#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
-#define EXTI_PIN_MASK 0x0000001Fu
-
-/**
- * @brief EXTI Mask for interrupt & event mode
- */
-#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
-
-/**
- * @brief EXTI Mask for trigger possibilities
- */
-#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
-
-/**
- * @brief EXTI Line number
- */
-#define EXTI_LINE_NB 41u
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup EXTI_Private_Macros EXTI Private Macros
- * @{
- */
-#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
- ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
- (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
- (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
- (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
- (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
-
-#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
- (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
-
-#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
-
-#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
-
-#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
-
-#if defined(STM32L412xx) || defined(STM32L422xx)
-
-#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
- ((__PORT__) == EXTI_GPIOB) || \
- ((__PORT__) == EXTI_GPIOC) || \
- ((__PORT__) == EXTI_GPIOD) || \
- ((__PORT__) == EXTI_GPIOH))
-
-#endif /* STM32L412xx || STM32L422xx */
-
-#if defined(STM32L431xx) || defined(STM32L433xx) || defined(STM32L443xx)
-
-#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
- ((__PORT__) == EXTI_GPIOB) || \
- ((__PORT__) == EXTI_GPIOC) || \
- ((__PORT__) == EXTI_GPIOD) || \
- ((__PORT__) == EXTI_GPIOE) || \
- ((__PORT__) == EXTI_GPIOH))
-
-#endif /* STM32L431xx || STM32L433xx || STM32L443xx */
-
-#if defined(STM32L432xx) || defined(STM32L442xx)
-
-#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
- ((__PORT__) == EXTI_GPIOB) || \
- ((__PORT__) == EXTI_GPIOC) || \
- ((__PORT__) == EXTI_GPIOH))
-
-#endif /* STM32L432xx || STM32L442xx */
-
-#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
-
-#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
- ((__PORT__) == EXTI_GPIOB) || \
- ((__PORT__) == EXTI_GPIOC) || \
- ((__PORT__) == EXTI_GPIOD) || \
- ((__PORT__) == EXTI_GPIOE) || \
- ((__PORT__) == EXTI_GPIOH))
-
-#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
-
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
-
-#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
- ((__PORT__) == EXTI_GPIOB) || \
- ((__PORT__) == EXTI_GPIOC) || \
- ((__PORT__) == EXTI_GPIOD) || \
- ((__PORT__) == EXTI_GPIOE) || \
- ((__PORT__) == EXTI_GPIOF) || \
- ((__PORT__) == EXTI_GPIOG) || \
- ((__PORT__) == EXTI_GPIOH))
-
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
-
-#if defined(STM32L496xx) || defined(STM32L4A6xx)
-
-#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
- ((__PORT__) == EXTI_GPIOB) || \
- ((__PORT__) == EXTI_GPIOC) || \
- ((__PORT__) == EXTI_GPIOD) || \
- ((__PORT__) == EXTI_GPIOE) || \
- ((__PORT__) == EXTI_GPIOF) || \
- ((__PORT__) == EXTI_GPIOG) || \
- ((__PORT__) == EXTI_GPIOH) || \
- ((__PORT__) == EXTI_GPIOI))
-
-#endif /* STM32L496xx || STM32L4A6xx */
-
-#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-
-#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
- ((__PORT__) == EXTI_GPIOB) || \
- ((__PORT__) == EXTI_GPIOC) || \
- ((__PORT__) == EXTI_GPIOD) || \
- ((__PORT__) == EXTI_GPIOE) || \
- ((__PORT__) == EXTI_GPIOF) || \
- ((__PORT__) == EXTI_GPIOG) || \
- ((__PORT__) == EXTI_GPIOH) || \
- ((__PORT__) == EXTI_GPIOI))
-
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
- * @brief EXTI Exported Functions
- * @{
- */
-
-/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
- * @brief Configuration functions
- * @{
- */
-/* Configuration functions ****************************************************/
-HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
-HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
-HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
-HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
-HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
-/**
- * @}
- */
-
-/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- * @{
- */
-/* IO operation functions *****************************************************/
-void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
-uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
-void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
-void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L4xx_HAL_EXTI_H */
-
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h
deleted file mode 100644
index 663a92d..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h
+++ /dev/null
@@ -1,1027 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_flash.h
- * @author MCD Application Team
- * @brief Header file of FLASH HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file in
- * the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L4xx_HAL_FLASH_H
-#define STM32L4xx_HAL_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FLASH
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Types FLASH Exported Types
- * @{
- */
-
-/**
- * @brief FLASH Erase structure definition
- */
-typedef struct
-{
- uint32_t TypeErase; /*!< Mass erase or page erase.
- This parameter can be a value of @ref FLASH_Type_Erase */
- uint32_t Banks; /*!< Select bank to erase.
- This parameter must be a value of @ref FLASH_Banks
- (FLASH_BANK_BOTH should be used only for mass erase) */
- uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled
- This parameter must be a value between 0 and (max number of pages in the bank - 1)
- (eg : 255 for 1MB dual bank) */
- uint32_t NbPages; /*!< Number of pages to be erased.
- This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/
-} FLASH_EraseInitTypeDef;
-
-/**
- * @brief FLASH Option Bytes Program structure definition
- */
-typedef struct
-{
- uint32_t OptionType; /*!< Option byte to be configured.
- This parameter can be a combination of the values of @ref FLASH_OB_Type */
- uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
- Only one WRP area could be programmed at the same time.
- This parameter can be value of @ref FLASH_OB_WRP_Area */
- uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).
- This parameter must be a value between 0 and (max number of pages in the bank - 1)
- (eg : 25 for 1MB dual bank) */
- uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP).
- This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */
- uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP).
- This parameter can be a value of @ref FLASH_OB_Read_Protection */
- uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
- This parameter can be a combination of @ref FLASH_OB_USER_Type */
- uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
- This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
- @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
- @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
- @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
- @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2,
- @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1,
- @ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */
- uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
- This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH)
- and @ref FLASH_OB_PCROP_RDP */
- uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
- This parameter must be a value between begin and end of bank
- => Be careful of the bank swapping for the address */
- uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP).
- This parameter must be a value between PCROP Start address and end of bank */
-} FLASH_OBProgramInitTypeDef;
-
-/**
- * @brief FLASH Procedure structure definition
- */
-typedef enum
-{
- FLASH_PROC_NONE = 0,
- FLASH_PROC_PAGE_ERASE,
- FLASH_PROC_MASS_ERASE,
- FLASH_PROC_PROGRAM,
- FLASH_PROC_PROGRAM_LAST
-} FLASH_ProcedureTypeDef;
-
-/**
- * @brief FLASH Cache structure definition
- */
-typedef enum
-{
- FLASH_CACHE_DISABLED = 0,
- FLASH_CACHE_ICACHE_ENABLED,
- FLASH_CACHE_DCACHE_ENABLED,
- FLASH_CACHE_ICACHE_DCACHE_ENABLED
-} FLASH_CacheTypeDef;
-
-/**
- * @brief FLASH handle Structure definition
- */
-typedef struct
-{
- HAL_LockTypeDef Lock; /* FLASH locking object */
- __IO uint32_t ErrorCode; /* FLASH error code */
- __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
- __IO uint32_t Address; /* Internal variable to save address selected for program in IT context */
- __IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */
- __IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */
- __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */
- __IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */
-}FLASH_ProcessTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
- * @{
- */
-
-/** @defgroup FLASH_Error FLASH Error
- * @{
- */
-#define HAL_FLASH_ERROR_NONE 0x00000000U
-#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR
-#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR
-#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
-#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR
-#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR
-#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
-#define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR
-#define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR
-#define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR
-#define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR
-#define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC
-#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD
-#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
- defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || \
- defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define HAL_FLASH_ERROR_PEMPTY FLASH_FLAG_PEMPTY
-#endif
-/**
- * @}
- */
-
-/** @defgroup FLASH_Type_Erase FLASH Erase Type
- * @{
- */
-#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!> 24) /*!< ECC Correction Interrupt source */
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
- * @brief macros to control FLASH features
- * @{
- */
-
-/**
- * @brief Set the FLASH Latency.
- * @param __LATENCY__ FLASH Latency
- * This parameter can be one of the following values :
- * @arg FLASH_LATENCY_0: FLASH Zero wait state
- * @arg FLASH_LATENCY_1: FLASH One wait state
- * @arg FLASH_LATENCY_2: FLASH Two wait states
- * @arg FLASH_LATENCY_3: FLASH Three wait states
- * @arg FLASH_LATENCY_4: FLASH Four wait states
- * @retval None
- */
-#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)))
-
-/**
- * @brief Get the FLASH Latency.
- * @retval FLASH Latency
- * This parameter can be one of the following values :
- * @arg FLASH_LATENCY_0: FLASH Zero wait state
- * @arg FLASH_LATENCY_1: FLASH One wait state
- * @arg FLASH_LATENCY_2: FLASH Two wait states
- * @arg FLASH_LATENCY_3: FLASH Three wait states
- * @arg FLASH_LATENCY_4: FLASH Four wait states
- */
-#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
-
-/**
- * @brief Enable the FLASH prefetch buffer.
- * @retval None
- */
-#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
-
-/**
- * @brief Disable the FLASH prefetch buffer.
- * @retval None
- */
-#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
-
-/**
- * @brief Enable the FLASH instruction cache.
- * @retval none
- */
-#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
-
-/**
- * @brief Disable the FLASH instruction cache.
- * @retval none
- */
-#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
-
-/**
- * @brief Enable the FLASH data cache.
- * @retval none
- */
-#define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
-
-/**
- * @brief Disable the FLASH data cache.
- * @retval none
- */
-#define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
-
-/**
- * @brief Reset the FLASH instruction Cache.
- * @note This function must be used only when the Instruction Cache is disabled.
- * @retval None
- */
-#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
- } while (0)
-
-/**
- * @brief Reset the FLASH data Cache.
- * @note This function must be used only when the data Cache is disabled.
- * @retval None
- */
-#define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
- } while (0)
-
-/**
- * @brief Enable the FLASH power down during Low-power run mode.
- * @note Writing this bit to 0 this bit, automatically the keys are
- * loss and a new unlock sequence is necessary to re-write it to 1.
- */
-#define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
- WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
- SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
- } while (0)
-
-/**
- * @brief Disable the FLASH power down during Low-power run mode.
- * @note Writing this bit to 0 this bit, automatically the keys are
- * loss and a new unlock sequence is necessary to re-write it to 1.
- */
-#define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
- WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
- } while (0)
-
-/**
- * @brief Enable the FLASH power down during Low-Power sleep mode
- * @retval none
- */
-#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
-
-/**
- * @brief Disable the FLASH power down during Low-Power sleep mode
- * @retval none
- */
-#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Interrupt FLASH Interrupts Macros
- * @brief macros to handle FLASH interrupts
- * @{
- */
-
-/**
- * @brief Enable the specified FLASH interrupt.
- * @param __INTERRUPT__ FLASH interrupt
- * This parameter can be any combination of the following values:
- * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
- * @arg FLASH_IT_OPERR: Error Interrupt
- * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
- * @arg FLASH_IT_ECCC: ECC Correction Interrupt
- * @retval none
- */
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
- if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
- } while(0)
-
-/**
- * @brief Disable the specified FLASH interrupt.
- * @param __INTERRUPT__ FLASH interrupt
- * This parameter can be any combination of the following values:
- * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
- * @arg FLASH_IT_OPERR: Error Interrupt
- * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
- * @arg FLASH_IT_ECCC: ECC Correction Interrupt
- * @retval none
- */
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
- if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
- } while(0)
-
-/**
- * @brief Check whether the specified FLASH flag is set or not.
- * @param __FLAG__ specifies the FLASH flag to check.
- * This parameter can be one of the following values:
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
- * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
- * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
- * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
- * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
- * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
- * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
- * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
- * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
- * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
- * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
- * @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices)
- * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
- * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
- * @retval The new state of FLASH_FLAG (SET or RESET).
- */
-#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \
- (READ_BIT(FLASH->ECCR, (__FLAG__)) != 0U) : \
- (READ_BIT(FLASH->SR, (__FLAG__)) != 0U))
-
-/**
- * @brief Clear the FLASH's pending flags.
- * @param __FLAG__ specifies the FLASH flags to clear.
- * This parameter can be any combination of the following values:
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
- * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
- * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
- * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
- * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
- * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
- * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
- * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
- * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
- * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
- * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
- * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
- * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags
- * @retval None
- */
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\
- if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\
- } while(0)
-/**
- * @}
- */
-
-/* Include FLASH HAL Extended module */
-#include "stm32l4xx_hal_flash_ex.h"
-#include "stm32l4xx_hal_flash_ramfunc.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASH_Exported_Functions
- * @{
- */
-
-/* Program operation functions ***********************************************/
-/** @addtogroup FLASH_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-/* FLASH IRQ handler method */
-void HAL_FLASH_IRQHandler(void);
-/* Callbacks in non blocking modes */
-void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
-void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
-/**
- * @}
- */
-
-/* Peripheral Control functions **********************************************/
-/** @addtogroup FLASH_Exported_Functions_Group2
- * @{
- */
-HAL_StatusTypeDef HAL_FLASH_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_Lock(void);
-/* Option bytes control */
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
-/**
- * @}
- */
-
-/* Peripheral State functions ************************************************/
-/** @addtogroup FLASH_Exported_Functions_Group3
- * @{
- */
-uint32_t HAL_FLASH_GetError(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup FLASH_Private_Variables FLASH Private Variables
- * @{
- */
-extern FLASH_ProcessTypeDef pFlash;
-/**
- * @}
- */
-
-/* Private function ----------------------------------------------------------*/
-/** @addtogroup FLASH_Private_Functions FLASH Private Functions
- * @{
- */
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
-/**
- * @}
- */
-
-/* Private constants --------------------------------------------------------*/
-/** @defgroup FLASH_Private_Constants FLASH Private Constants
- * @{
- */
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \
- defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define FLASH_BANK_SIZE (FLASH_SIZE >> 1U)
-#else
-#define FLASH_BANK_SIZE (FLASH_SIZE)
-#endif
-
-#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define FLASH_PAGE_SIZE ((uint32_t)0x1000)
-#define FLASH_PAGE_SIZE_128_BITS ((uint32_t)0x2000)
-#else
-#define FLASH_PAGE_SIZE ((uint32_t)0x800)
-#endif
-
-#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup FLASH_Private_Macros FLASH Private Macros
- * @{
- */
-
-#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
- ((VALUE) == FLASH_TYPEERASE_MASSERASE))
-
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \
- defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
- ((BANK) == FLASH_BANK_2) || \
- ((BANK) == FLASH_BANK_BOTH))
-
-#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \
- ((BANK) == FLASH_BANK_2))
-#else
-#define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1)
-
-#define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1)
-#endif
-
-#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
- ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \
- ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))
-
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((ADDRESS) <= (FLASH_BASE+0x1FFFFFU)))
-#else
-#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? \
- ((ADDRESS) <= (FLASH_BASE+0xFFFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? \
- ((ADDRESS) <= (FLASH_BASE+0x7FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? \
- ((ADDRESS) <= (FLASH_BASE+0x3FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? \
- ((ADDRESS) <= (FLASH_BASE+0x1FFFFU)) : ((ADDRESS) <= (FLASH_BASE+0xFFFFFU)))))))
-#endif
-
-#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU))
-
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS)))
-
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define IS_FLASH_PAGE(PAGE) ((PAGE) < 256U)
-#elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
-#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? ((PAGE) < 256U) : \
- ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 128U) : \
- ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 64U) : \
- ((PAGE) < 256U)))))
-#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
-#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 256U) : \
- ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \
- ((PAGE) < 256U))))
-#else
-#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \
- ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? ((PAGE) < 64U) : \
- ((PAGE) < 128U))))
-#endif
-
-#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)))
-
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \
- defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
- ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))
-#else
-#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB))
-#endif
-
-#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
- ((LEVEL) == OB_RDP_LEVEL_1)/* ||\
- ((LEVEL) == OB_RDP_LEVEL_2)*/)
-
-#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFFU) && ((TYPE) != 0U))
-#elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
-#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFFU) && ((TYPE) != 0U))
-#else
-#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7FU) && ((TYPE) != 0U) && (((TYPE)&0x0180U) == 0U))
-#endif
-
-#define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
- ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
- ((LEVEL) == OB_BOR_LEVEL_4))
-
-#define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
-
-#define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
-
-#define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
-
-#define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
-
-#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
-
-#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
-
-#define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
-
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \
- defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
-
-#define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL))
-#endif
-
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS))
-#endif
-
-#define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
-
-#define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE))
-
-#define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))
-
-#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \
- defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \
- defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))
-
-#define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET))
-#endif
-
-#define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
-
-#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \
- ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \
- ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \
- ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \
- ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \
- ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \
- ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \
- ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15))
-#else
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
- ((LATENCY) == FLASH_LATENCY_1) || \
- ((LATENCY) == FLASH_LATENCY_2) || \
- ((LATENCY) == FLASH_LATENCY_3) || \
- ((LATENCY) == FLASH_LATENCY_4))
-#endif
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L4xx_HAL_FLASH_H */
-
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h
deleted file mode 100644
index 36ec888..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_flash_ex.h
- * @author MCD Application Team
- * @brief Header file of FLASH HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file in
- * the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L4xx_HAL_FLASH_EX_H
-#define STM32L4xx_HAL_FLASH_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FLASHEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-#if defined (FLASH_CFGR_LVEN)
-/** @addtogroup FLASHEx_Exported_Constants
- * @{
- */
-/** @defgroup FLASHEx_LVE_PIN_CFG FLASHEx LVE pin configuration
- * @{
- */
-#define FLASH_LVE_PIN_CTRL 0x00000000U /*!< LVE FLASH pin controlled by power controller */
-#define FLASH_LVE_PIN_FORCED FLASH_CFGR_LVEN /*!< LVE FLASH pin enforced to low (external SMPS used) */
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* FLASH_CFGR_LVEN */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASHEx_Exported_Functions
- * @{
- */
-
-/* Extended Program operation functions *************************************/
-/** @addtogroup FLASHEx_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
-/**
- * @}
- */
-
-#if defined (FLASH_CFGR_LVEN)
-/** @addtogroup FLASHEx_Exported_Functions_Group2
- * @{
- */
-HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE);
-/**
- * @}
- */
-#endif /* FLASH_CFGR_LVEN */
-
-/**
- * @}
- */
-
-/* Private function ----------------------------------------------------------*/
-/** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions
- * @{
- */
-void FLASH_PageErase(uint32_t Page, uint32_t Banks);
-void FLASH_FlushCaches(void);
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/**
- @cond 0
- */
-#if defined (FLASH_CFGR_LVEN)
-#define IS_FLASH_LVE_PIN(CFG) (((CFG) == FLASH_LVE_PIN_CTRL) || ((CFG) == FLASH_LVE_PIN_FORCED))
-#endif /* FLASH_CFGR_LVEN */
-/**
- @endcond
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L4xx_HAL_FLASH_EX_H */
-
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h
deleted file mode 100644
index b5852fc..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_flash_ramfunc.h
- * @author MCD Application Team
- * @brief Header file of FLASH RAMFUNC driver.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file in
- * the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L4xx_FLASH_RAMFUNC_H
-#define STM32L4xx_FLASH_RAMFUNC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FLASH_RAMFUNC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions
- * @{
- */
-
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
- * @{
- */
-/* Peripheral Control functions ************************************************/
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void);
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void);
-#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig);
-#endif
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L4xx_FLASH_RAMFUNC_H */
-
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h
deleted file mode 100644
index aaa7b6d..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h
+++ /dev/null
@@ -1,323 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_gpio.h
- * @author MCD Application Team
- * @brief Header file of GPIO HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L4xx_HAL_GPIO_H
-#define STM32L4xx_HAL_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup GPIO
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Types GPIO Exported Types
- * @{
- */
-/**
- * @brief GPIO Init structure definition
- */
-typedef struct
-{
- uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_pins */
-
- uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIO_mode */
-
- uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
- This parameter can be a value of @ref GPIO_pull */
-
- uint32_t Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIO_speed */
-
- uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
- This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
-} GPIO_InitTypeDef;
-
-/**
- * @brief GPIO Bit SET and Bit RESET enumeration
- */
-typedef enum
-{
- GPIO_PIN_RESET = 0U,
- GPIO_PIN_SET
-} GPIO_PinState;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
- * @{
- */
-/** @defgroup GPIO_pins GPIO pins
- * @{
- */
-#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
-#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
-#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
-#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
-#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
-#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
-#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
-#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
-#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
-#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
-#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
-#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
-#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
-#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
-#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
-#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
-#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
-
-#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
-/**
- * @}
- */
-
-/** @defgroup GPIO_mode GPIO mode
- * @brief GPIO Configuration Mode
- * Elements values convention: 0x00WX00YZ
- * - W : EXTI trigger detection on 3 bits
- * - X : EXTI mode (IT or Event) on 2 bits
- * - Y : Output type (Push Pull or Open Drain) on 1 bit
- * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
- * @{
- */
-#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
-#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
-#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
-#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
-#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
-#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
-#define GPIO_MODE_ANALOG_ADC_CONTROL (MODE_ANALOG | 0x8uL) /*!< Analog Mode for ADC conversion (0x0000000Bu)*/
-#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
-#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
-#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
-#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
-#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
-/**
- * @}
- */
-
-/** @defgroup GPIO_speed GPIO speed
- * @brief GPIO Output Maximum frequency
- * @{
- */
-#define GPIO_SPEED_FREQ_LOW 0x00000000u /*!< Low speed */
-#define GPIO_SPEED_FREQ_MEDIUM 0x00000001u /*!< Medium speed */
-#define GPIO_SPEED_FREQ_HIGH 0x00000002u /*!< High speed */
-#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003u /*!< Very high speed */
-/**
- * @}
- */
-
-/** @defgroup GPIO_pull GPIO pull
- * @brief GPIO Pull-Up or Pull-Down Activation
- * @{
- */
-#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */
-#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */
-#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
- * @{
- */
-
-/**
- * @brief Check whether the specified EXTI line flag is set or not.
- * @param __EXTI_LINE__ specifies the EXTI line flag to check.
- * This parameter can be GPIO_PIN_x where x can be(0..15)
- * @retval The new state of __EXTI_LINE__ (SET or RESET).
- */
-#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
-
-/**
- * @brief Clear the EXTI's line pending flags.
- * @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
- * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
- * @retval None
- */
-#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
-
-/**
- * @brief Check whether the specified EXTI line is asserted or not.
- * @param __EXTI_LINE__ specifies the EXTI line to check.
- * This parameter can be GPIO_PIN_x where x can be(0..15)
- * @retval The new state of __EXTI_LINE__ (SET or RESET).
- */
-#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
-
-/**
- * @brief Clear the EXTI's line pending bits.
- * @param __EXTI_LINE__ specifies the EXTI lines to clear.
- * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
- * @retval None
- */
-#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
-
-/**
- * @brief Generate a Software interrupt on selected EXTI line.
- * @param __EXTI_LINE__ specifies the EXTI line to check.
- * This parameter can be GPIO_PIN_x where x can be(0..15)
- * @retval None
- */
-#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup GPIO_Private_Constants GPIO Private Constants
- * @{
- */
-#define GPIO_MODE_Pos 0u
-#define GPIO_MODE (0x3uL << GPIO_MODE_Pos)
-#define MODE_INPUT (0x0uL << GPIO_MODE_Pos)
-#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos)
-#define MODE_AF (0x2uL << GPIO_MODE_Pos)
-#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos)
-#define OUTPUT_TYPE_Pos 4u
-#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos)
-#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos)
-#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos)
-#define EXTI_MODE_Pos 16u
-#define EXTI_MODE (0x3uL << EXTI_MODE_Pos)
-#define EXTI_IT (0x1uL << EXTI_MODE_Pos)
-#define EXTI_EVT (0x2uL << EXTI_MODE_Pos)
-#define TRIGGER_MODE_Pos 20u
-#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos)
-#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos)
-#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos)
-
-/**
- * @}
- */
-
-/** @addtogroup GPIO_Private_Macros GPIO Private Macros
- * @{
- */
-#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-
-#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
- (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
-
-#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
- ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
- ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
- ((__MODE__) == GPIO_MODE_AF_PP) ||\
- ((__MODE__) == GPIO_MODE_AF_OD) ||\
- ((__MODE__) == GPIO_MODE_IT_RISING) ||\
- ((__MODE__) == GPIO_MODE_IT_FALLING) ||\
- ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
- ((__MODE__) == GPIO_MODE_EVT_RISING) ||\
- ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
- ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
- ((__MODE__) == GPIO_MODE_ANALOG) ||\
- ((__MODE__) == GPIO_MODE_ANALOG_ADC_CONTROL))
-
-#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
- ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
- ((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\
- ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
-
-#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
- ((__PULL__) == GPIO_PULLUP) || \
- ((__PULL__) == GPIO_PULLDOWN))
-/**
- * @}
- */
-
-/* Include GPIO HAL Extended module */
-#include "stm32l4xx_hal_gpio_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
- * @{
- */
-
-/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
- * @{
- */
-
-/* Initialization and de-initialization functions *****************************/
-void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
-void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
-
-/**
- * @}
- */
-
-/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions
- * @{
- */
-
-/* IO operation functions *****************************************************/
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L4xx_HAL_GPIO_H */
-
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h
deleted file mode 100644
index 550ae96..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h
+++ /dev/null
@@ -1,1059 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_gpio_ex.h
- * @author MCD Application Team
- * @brief Header file of GPIO HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L4xx_HAL_GPIO_EX_H
-#define STM32L4xx_HAL_GPIO_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup GPIOEx GPIOEx
- * @brief GPIO Extended HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
- * @{
- */
-
-/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
- * @{
- */
-
-#if defined(STM32L412xx) || defined(STM32L422xx)
-/*--------------STM32L412xx/STM32L422xx---*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
-#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
-
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART1 Alternate Function mapping */
-#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_COMP1 ((uint8_t)0x06) /* COMP1 Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_USB_FS ((uint8_t)0x0A) /* USB_FS Alternate Function mapping */
-#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
-
-
-/**
- * @brief AF 14 selection
- */
-#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
-#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
-#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
-#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
-
-#endif /* STM32L412xx || STM32L422xx */
-
-#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
-/*--------------STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx---*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#if defined(STM32L433xx) || defined(STM32L443xx)
-#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
-#endif /* STM32L433xx || STM32L443xx */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
-#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
-
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART1 Alternate Function mapping */
-#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
-#define GPIO_AF6_COMP1 ((uint8_t)0x06) /* COMP1 Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
-#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
-#define GPIO_AF10_USB_FS ((uint8_t)0x0A) /* USB_FS Alternate Function mapping */
-#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
-#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */
-
-#if defined(STM32L433xx) || defined(STM32L443xx)
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */
-#endif /* STM32L433xx || STM32L443xx */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_SWPMI1 ((uint8_t)0x0C) /* SWPMI1 Alternate Function mapping */
-#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
-#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
-#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
-
-/**
- * @brief AF 13 selection
- */
-#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
-
-/**
- * @brief AF 14 selection
- */
-#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
-#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
-#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
-#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
-
-#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
-
-#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
-/*--------------STM32L451xx/STM32L452xx/STM32L462xx---------------------------*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
-#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
-
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_I2C4 ((uint8_t)0x02) /* I2C4 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */
-#define GPIO_AF3_CAN1 ((uint8_t)0x03) /* CAN1 Alternate Function mapping */
-#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
-#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
-#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
-#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */
-#define GPIO_AF6_COMP1 ((uint8_t)0x06) /* COMP1 Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
-#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
-#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */
-
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
-#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#if defined(STM32L452xx) || defined(STM32L462xx)
-#define GPIO_AF10_USB_FS ((uint8_t)0x0A) /* USB_FS Alternate Function mapping */
-#endif /* STM32L452xx || STM32L462xx */
-#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */
-#define GPIO_AF10_CAN1 ((uint8_t)0x0A) /* CAN1 Alternate Function mapping */
-
-/**
- * @brief AF 11 selection
- */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
-#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
-#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
-
-/**
- * @brief AF 13 selection
- */
-#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
-
-/**
- * @brief AF 14 selection
- */
-#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
-#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
-#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
-#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */
-#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
-
-#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
-
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
-/*--------------STM32L471xx/STM32L475xx/STM32L476xx/STM32L485xx/STM32L486xx---*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#if defined(STM32L476xx) || defined(STM32L486xx)
-#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
-#endif /* STM32L476xx || STM32L486xx */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */
-#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */
-#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
-#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
-
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
-#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
-#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
-#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
-#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
-
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
-#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
-#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */
-#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
-#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */
-
-#if defined(STM32L476xx) || defined(STM32L486xx)
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */
-#endif /* STM32L476xx || STM32L486xx */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
-#define GPIO_AF12_SWPMI1 ((uint8_t)0x0C) /* SWPMI1 Alternate Function mapping */
-#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
-#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
-#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
-
-/**
- * @brief AF 13 selection
- */
-#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
-#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */
-#define GPIO_AF13_TIM8_COMP2 ((uint8_t)0x0D) /* TIM8/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */
-
-/**
- * @brief AF 14 selection
- */
-#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
-#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
-#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
-#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */
-#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
-#define GPIO_AF14_TIM8_COMP1 ((uint8_t)0x0E) /* TIM8/COMP1 Break in Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
-
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
-
-#if defined(STM32L496xx) || defined(STM32L4A6xx)
-/*--------------------------------STM32L496xx/STM32L4A6xx---------------------*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */
-#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */
-#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
-#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
-
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
-#define GPIO_AF2_I2C4 ((uint8_t)0x02) /* I2C4 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
-#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF3_CAN2 ((uint8_t)0x03) /* CAN2 Alternate Function mapping */
-#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */
-#define GPIO_AF3_QUADSPI ((uint8_t)0x03) /* QUADSPI Alternate Function mapping */
-#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */
-#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
-#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
-#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
-#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */
-#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */
-#define GPIO_AF5_QUADSPI ((uint8_t)0x05) /* QUADSPI Alternate Function mapping */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
-#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */
-#define GPIO_AF6_I2C3 ((uint8_t)0x06) /* I2C3 Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
-#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
-#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
-#define GPIO_AF8_CAN2 ((uint8_t)0x08) /* CAN2 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
-#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */
-#define GPIO_AF10_CAN2 ((uint8_t)0x0A) /* CAN2 Alternate Function mapping */
-#define GPIO_AF10_DCMI ((uint8_t)0x0A) /* DCMI Alternate Function mapping */
-
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
-#define GPIO_AF12_SWPMI1 ((uint8_t)0x0C) /* SWPMI1 Alternate Function mapping */
-#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
-#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
-#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
-#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */
-
-/**
- * @brief AF 13 selection
- */
-#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
-#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */
-#define GPIO_AF13_TIM8_COMP2 ((uint8_t)0x0D) /* TIM8/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */
-
-/**
- * @brief AF 14 selection
- */
-#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
-#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
-#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
-#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */
-#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
-#define GPIO_AF14_TIM8_COMP1 ((uint8_t)0x0E) /* TIM8/COMP1 Break in Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
-
-#endif /* STM32L496xx || STM32L4A6xx */
-
-#if defined (STM32L4P5xx) || defined (STM32L4Q5xx)
-/*---STM32L4P5xx/STM32L4Q5xx--*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */
-#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */
-#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
-#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
-
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */
-#define GPIO_AF3_OCTOSPIM_P1 ((uint8_t)0x03) /* OctoSPI Manager Port 1 Alternate Function mapping */
-#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */
-#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */
-#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
-#define GPIO_AF3_TIM8_COMP1 ((uint8_t)0x03) /* TIM8/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF3_TIM8_COMP2 ((uint8_t)0x03) /* TIM8/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
-#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
-#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */
-#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */
-#define GPIO_AF5_PSSI ((uint8_t)0x05) /* PSSI Alternate Function mapping */
-#define GPIO_AF5_DFSDM1 ((uint8_t)0x05) /* DFSDM1 Alternate Function mapping */
-#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */
-#define GPIO_AF5_OCTOSPIM_P1 ((uint8_t)0x05) /* OctoSPI Manager Port 1 Alternate Function mapping */
-#define GPIO_AF5_OCTOSPIM_P2 ((uint8_t)0x05) /* OctoSPI Manager Port 2 Alternate Function mapping */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */
-#define GPIO_AF6_I2C3 ((uint8_t)0x06) /* I2C3 Alternate Function mapping */
-#define GPIO_AF6_OCTOSPIM_P1 ((uint8_t)0x06) /* OctoSPI Manager Port 1 Alternate Function mapping */
-#define GPIO_AF6_OCTOSPIM_P2 ((uint8_t)0x06) /* OctoSPI Manager Port 2 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_SDMMC2 ((uint8_t)0x07) /* SDMMC2 Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
-#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */
-#define GPIO_AF8_SDMMC2 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */
-#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
-#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
-#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
-#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_DCMI ((uint8_t)0x0A) /* DCMI Alternate Function mapping */
-#define GPIO_AF10_PSSI ((uint8_t)0x0A) /* PSSI Alternate Function mapping */
-#define GPIO_AF10_OCTOSPIM_P1 ((uint8_t)0x0A) /* OctoSPI Manager Port 1 Alternate Function mapping */
-#define GPIO_AF10_OCTOSPIM_P2 ((uint8_t)0x0A) /* OctoSPI Manager Port 2 Alternate Function mapping */
-#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */
-
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_LTDC ((uint8_t)0x0B) /* LTDC Alternate Function mapping */
-#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
-#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
-#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
-#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
-#define GPIO_AF12_SDMMC2 ((uint8_t)0x0C) /* SDMMC2 Alternate Function mapping */
-#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */
-
-/**
- * @brief AF 13 selection
- */
-#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
-#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */
-#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */
-
-/**
- * @brief AF 14 selection
- */
-#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
-#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
-#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */
-#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
-#define GPIO_AF14_TIM8_COMP2 ((uint8_t)0x0E) /* TIM8/COMP2 Break in Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
-
-#endif /* STM32L4P5xx || STM32L4Q5xx */
-
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-/*---STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/STM32L4S5xx/STM32L4S7xx/STM32L4S9xx--*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */
-#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */
-#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
-#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
-
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */
-#define GPIO_AF3_OCTOSPIM_P1 ((uint8_t)0x03) /* OctoSPI Manager Port 1 Alternate Function mapping */
-#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */
-#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */
-#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
-#define GPIO_AF3_TIM8_COMP1 ((uint8_t)0x03) /* TIM8/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF3_TIM8_COMP2 ((uint8_t)0x03) /* TIM8/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
-#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
-#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */
-#define GPIO_AF5_DFSDM1 ((uint8_t)0x05) /* DFSDM1 Alternate Function mapping */
-#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */
-#define GPIO_AF5_OCTOSPIM_P1 ((uint8_t)0x05) /* OctoSPI Manager Port 1 Alternate Function mapping */
-#define GPIO_AF5_OCTOSPIM_P2 ((uint8_t)0x05) /* OctoSPI Manager Port 2 Alternate Function mapping */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */
-#define GPIO_AF6_I2C3 ((uint8_t)0x06) /* I2C3 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
-#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */
-#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
-#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
-#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
-#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_DCMI ((uint8_t)0x0A) /* DCMI Alternate Function mapping */
-#define GPIO_AF10_OCTOSPIM_P1 ((uint8_t)0x0A) /* OctoSPI Manager Port 1 Alternate Function mapping */
-#define GPIO_AF10_OCTOSPIM_P2 ((uint8_t)0x0A) /* OctoSPI Manager Port 2 Alternate Function mapping */
-#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */
-
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_DSI ((uint8_t)0x0B) /* DSI Alternate Function mapping */
-#define GPIO_AF11_LTDC ((uint8_t)0x0B) /* LTDC Alternate Function mapping */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
-#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
-#define GPIO_AF12_DSI ((uint8_t)0x0C) /* DSI Alternate Function mapping */
-#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
-#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
-#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */
-#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */
-#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */
-
-/**
- * @brief AF 13 selection
- */
-#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
-#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */
-#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */
-
-/**
- * @brief AF 14 selection
- */
-#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
-#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
-#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
-#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */
-#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
-#define GPIO_AF14_TIM8_COMP2 ((uint8_t)0x0E) /* TIM8/COMP2 Break in Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
-
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
- * @{
- */
-
-/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index
-* @{
- */
-#if defined(STM32L412xx) || defined(STM32L422xx)
-
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
- ((__GPIOx__) == (GPIOB))? 1uL :\
- ((__GPIOx__) == (GPIOC))? 2uL :\
- ((__GPIOx__) == (GPIOD))? 3uL : 7uL)
-
-#endif /* STM32L412xx || STM32L422xx */
-
-#if defined(STM32L431xx) || defined(STM32L433xx) || defined(STM32L443xx)
-
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
- ((__GPIOx__) == (GPIOB))? 1uL :\
- ((__GPIOx__) == (GPIOC))? 2uL :\
- ((__GPIOx__) == (GPIOD))? 3uL :\
- ((__GPIOx__) == (GPIOE))? 4uL : 7uL)
-
-#endif /* STM32L431xx || STM32L433xx || STM32L443xx */
-
-#if defined(STM32L432xx) || defined(STM32L442xx)
-
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
- ((__GPIOx__) == (GPIOB))? 1uL :\
- ((__GPIOx__) == (GPIOC))? 2uL : 7uL)
-
-#endif /* STM32L432xx || STM32L442xx */
-
-#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
-
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
- ((__GPIOx__) == (GPIOB))? 1uL :\
- ((__GPIOx__) == (GPIOC))? 2uL :\
- ((__GPIOx__) == (GPIOD))? 3uL :\
- ((__GPIOx__) == (GPIOE))? 4uL : 7uL)
-
-#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
-
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
-
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
- ((__GPIOx__) == (GPIOB))? 1uL :\
- ((__GPIOx__) == (GPIOC))? 2uL :\
- ((__GPIOx__) == (GPIOD))? 3uL :\
- ((__GPIOx__) == (GPIOE))? 4uL :\
- ((__GPIOx__) == (GPIOF))? 5uL :\
- ((__GPIOx__) == (GPIOG))? 6uL : 7uL)
-
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
-
-#if defined(STM32L496xx) || defined(STM32L4A6xx)
-
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
- ((__GPIOx__) == (GPIOB))? 1uL :\
- ((__GPIOx__) == (GPIOC))? 2uL :\
- ((__GPIOx__) == (GPIOD))? 3uL :\
- ((__GPIOx__) == (GPIOE))? 4uL :\
- ((__GPIOx__) == (GPIOF))? 5uL :\
- ((__GPIOx__) == (GPIOG))? 6uL :\
- ((__GPIOx__) == (GPIOH))? 7uL : 8uL)
-
-#endif /* STM32L496xx || STM32L4A6xx */
-
-#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
- ((__GPIOx__) == (GPIOB))? 1uL :\
- ((__GPIOx__) == (GPIOC))? 2uL :\
- ((__GPIOx__) == (GPIOD))? 3uL :\
- ((__GPIOx__) == (GPIOE))? 4uL :\
- ((__GPIOx__) == (GPIOF))? 5uL :\
- ((__GPIOx__) == (GPIOG))? 6uL :\
- ((__GPIOx__) == (GPIOH))? 7uL : 8uL)
-
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L4xx_HAL_GPIO_EX_H */
-
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h
deleted file mode 100644
index f291048..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h
+++ /dev/null
@@ -1,835 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_i2c.h
- * @author MCD Application Team
- * @brief Header file of I2C HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L4xx_HAL_I2C_H
-#define STM32L4xx_HAL_I2C_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup I2C
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2C_Exported_Types I2C Exported Types
- * @{
- */
-
-/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
- * @brief I2C Configuration Structure definition
- * @{
- */
-typedef struct
-{
- uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
- This parameter calculated by referring to I2C initialization section
- in Reference manual */
-
- uint32_t OwnAddress1; /*!< Specifies the first device own address.
- This parameter can be a 7-bit or 10-bit address. */
-
- uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
- This parameter can be a value of @ref I2C_ADDRESSING_MODE */
-
- uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
- This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
-
- uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
- This parameter can be a 7-bit address. */
-
- uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
- mode is selected.
- This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
-
- uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
- This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
-
- uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
- This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
-
-} I2C_InitTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup HAL_state_structure_definition HAL state structure definition
- * @brief HAL State structure definition
- * @note HAL I2C State value coding follow below described bitmap :\n
- * b7-b6 Error information\n
- * 00 : No Error\n
- * 01 : Abort (Abort user request on going)\n
- * 10 : Timeout\n
- * 11 : Error\n
- * b5 Peripheral initialization status\n
- * 0 : Reset (peripheral not initialized)\n
- * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
- * b4 (not used)\n
- * x : Should be set to 0\n
- * b3\n
- * 0 : Ready or Busy (No Listen mode ongoing)\n
- * 1 : Listen (peripheral in Address Listen Mode)\n
- * b2 Intrinsic process state\n
- * 0 : Ready\n
- * 1 : Busy (peripheral busy with some configuration or internal operations)\n
- * b1 Rx state\n
- * 0 : Ready (no Rx operation ongoing)\n
- * 1 : Busy (Rx operation ongoing)\n
- * b0 Tx state\n
- * 0 : Ready (no Tx operation ongoing)\n
- * 1 : Busy (Tx operation ongoing)
- * @{
- */
-typedef enum
-{
- HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
- HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
- HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
- HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
- HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
- HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
- HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
- process is ongoing */
- HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
- process is ongoing */
- HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
- HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
- HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
-
-} HAL_I2C_StateTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup HAL_mode_structure_definition HAL mode structure definition
- * @brief HAL Mode structure definition
- * @note HAL I2C Mode value coding follow below described bitmap :\n
- * b7 (not used)\n
- * x : Should be set to 0\n
- * b6\n
- * 0 : None\n
- * 1 : Memory (HAL I2C communication is in Memory Mode)\n
- * b5\n
- * 0 : None\n
- * 1 : Slave (HAL I2C communication is in Slave Mode)\n
- * b4\n
- * 0 : None\n
- * 1 : Master (HAL I2C communication is in Master Mode)\n
- * b3-b2-b1-b0 (not used)\n
- * xxxx : Should be set to 0000
- * @{
- */
-typedef enum
-{
- HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
- HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
- HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
- HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
-
-} HAL_I2C_ModeTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Error_Code_definition I2C Error Code definition
- * @brief I2C Error Code definition
- * @{
- */
-#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
-#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
-#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
-#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
-#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
-#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
-#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
-#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
-/**
- * @}
- */
-
-/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
- * @brief I2C handle Structure definition
- * @{
- */
-typedef struct __I2C_HandleTypeDef
-{
- I2C_TypeDef *Instance; /*!< I2C registers base address */
-
- I2C_InitTypeDef Init; /*!< I2C communication parameters */
-
- uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
-
- uint16_t XferSize; /*!< I2C transfer size */
-
- __IO uint16_t XferCount; /*!< I2C transfer counter */
-
- __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
- be a value of @ref I2C_XFEROPTIONS */
-
- __IO uint32_t PreviousState; /*!< I2C communication Previous state */
-
- HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
- /*!< I2C transfer IRQ handler function pointer */
-
- DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
-
- HAL_LockTypeDef Lock; /*!< I2C locking object */
-
- __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
-
- __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
-
- __IO uint32_t ErrorCode; /*!< I2C Error code */
-
- __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
- /*!< I2C Master Tx Transfer completed callback */
- void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
- /*!< I2C Master Rx Transfer completed callback */
- void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
- /*!< I2C Slave Tx Transfer completed callback */
- void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
- /*!< I2C Slave Rx Transfer completed callback */
- void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
- /*!< I2C Listen Complete callback */
- void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
- /*!< I2C Memory Tx Transfer completed callback */
- void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
- /*!< I2C Memory Rx Transfer completed callback */
- void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
- /*!< I2C Error callback */
- void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
- /*!< I2C Abort callback */
-
- void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
- /*!< I2C Slave Address Match callback */
-
- void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
- /*!< I2C Msp Init callback */
- void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
- /*!< I2C Msp DeInit callback */
-
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-} I2C_HandleTypeDef;
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL I2C Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
- HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
- HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
- HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
- HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
- HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
- HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
- HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
- HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
-
- HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
- HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
-
-} HAL_I2C_CallbackIDTypeDef;
-
-/**
- * @brief HAL I2C Callback pointer definition
- */
-typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
-/*!< pointer to an I2C callback function */
-typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
- uint16_t AddrMatchCode);
-/*!< pointer to an I2C Address Match callback function */
-
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Constants I2C Exported Constants
- * @{
- */
-
-/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
- * @{
- */
-#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
-#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
-#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
-#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
-#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
-#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
-
-/* List of XferOptions in usage of :
- * 1- Restart condition in all use cases (direction change or not)
- */
-#define I2C_OTHER_FRAME (0x000000AAU)
-#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
-/**
- * @}
- */
-
-/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
- * @{
- */
-#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
-#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
-/**
- * @}
- */
-
-/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
- * @{
- */
-#define I2C_DUALADDRESS_DISABLE (0x00000000U)
-#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
-/**
- * @}
- */
-
-/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
- * @{
- */
-#define I2C_OA2_NOMASK ((uint8_t)0x00U)
-#define I2C_OA2_MASK01 ((uint8_t)0x01U)
-#define I2C_OA2_MASK02 ((uint8_t)0x02U)
-#define I2C_OA2_MASK03 ((uint8_t)0x03U)
-#define I2C_OA2_MASK04 ((uint8_t)0x04U)
-#define I2C_OA2_MASK05 ((uint8_t)0x05U)
-#define I2C_OA2_MASK06 ((uint8_t)0x06U)
-#define I2C_OA2_MASK07 ((uint8_t)0x07U)
-/**
- * @}
- */
-
-/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
- * @{
- */
-#define I2C_GENERALCALL_DISABLE (0x00000000U)
-#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
-/**
- * @}
- */
-
-/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
- * @{
- */
-#define I2C_NOSTRETCH_DISABLE (0x00000000U)
-#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
-/**
- * @}
- */
-
-/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
- * @{
- */
-#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
-#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
-/**
- * @}
- */
-
-/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
- * @{
- */
-#define I2C_DIRECTION_TRANSMIT (0x00000000U)
-#define I2C_DIRECTION_RECEIVE (0x00000001U)
-/**
- * @}
- */
-
-/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
- * @{
- */
-#define I2C_RELOAD_MODE I2C_CR2_RELOAD
-#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
-#define I2C_SOFTEND_MODE (0x00000000U)
-/**
- * @}
- */
-
-/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
- * @{
- */
-#define I2C_NO_STARTSTOP (0x00000000U)
-#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
-#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
-#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
-/**
- * @}
- */
-
-/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
- * @brief I2C Interrupt definition
- * Elements values convention: 0xXXXXXXXX
- * - XXXXXXXX : Interrupt control mask
- * @{
- */
-#define I2C_IT_ERRI I2C_CR1_ERRIE
-#define I2C_IT_TCI I2C_CR1_TCIE
-#define I2C_IT_STOPI I2C_CR1_STOPIE
-#define I2C_IT_NACKI I2C_CR1_NACKIE
-#define I2C_IT_ADDRI I2C_CR1_ADDRIE
-#define I2C_IT_RXI I2C_CR1_RXIE
-#define I2C_IT_TXI I2C_CR1_TXIE
-/**
- * @}
- */
-
-/** @defgroup I2C_Flag_definition I2C Flag definition
- * @{
- */
-#define I2C_FLAG_TXE I2C_ISR_TXE
-#define I2C_FLAG_TXIS I2C_ISR_TXIS
-#define I2C_FLAG_RXNE I2C_ISR_RXNE
-#define I2C_FLAG_ADDR I2C_ISR_ADDR
-#define I2C_FLAG_AF I2C_ISR_NACKF
-#define I2C_FLAG_STOPF I2C_ISR_STOPF
-#define I2C_FLAG_TC I2C_ISR_TC
-#define I2C_FLAG_TCR I2C_ISR_TCR
-#define I2C_FLAG_BERR I2C_ISR_BERR
-#define I2C_FLAG_ARLO I2C_ISR_ARLO
-#define I2C_FLAG_OVR I2C_ISR_OVR
-#define I2C_FLAG_PECERR I2C_ISR_PECERR
-#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
-#define I2C_FLAG_ALERT I2C_ISR_ALERT
-#define I2C_FLAG_BUSY I2C_ISR_BUSY
-#define I2C_FLAG_DIR I2C_ISR_DIR
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Macros I2C Exported Macros
- * @{
- */
-
-/** @brief Reset I2C handle state.
- * @param __HANDLE__ specifies the I2C Handle.
- * @retval None
- */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_I2C_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-
-/** @brief Enable the specified I2C interrupt.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __INTERRUPT__ specifies the interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg @ref I2C_IT_ERRI Errors interrupt enable
- * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
- * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
- * @arg @ref I2C_IT_NACKI NACK received interrupt enable
- * @arg @ref I2C_IT_ADDRI Address match interrupt enable
- * @arg @ref I2C_IT_RXI RX interrupt enable
- * @arg @ref I2C_IT_TXI TX interrupt enable
- *
- * @retval None
- */
-#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
-
-/** @brief Disable the specified I2C interrupt.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __INTERRUPT__ specifies the interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg @ref I2C_IT_ERRI Errors interrupt enable
- * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
- * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
- * @arg @ref I2C_IT_NACKI NACK received interrupt enable
- * @arg @ref I2C_IT_ADDRI Address match interrupt enable
- * @arg @ref I2C_IT_RXI RX interrupt enable
- * @arg @ref I2C_IT_TXI TX interrupt enable
- *
- * @retval None
- */
-#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
-
-/** @brief Check whether the specified I2C interrupt source is enabled or not.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __INTERRUPT__ specifies the I2C interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref I2C_IT_ERRI Errors interrupt enable
- * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
- * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
- * @arg @ref I2C_IT_NACKI NACK received interrupt enable
- * @arg @ref I2C_IT_ADDRI Address match interrupt enable
- * @arg @ref I2C_IT_RXI RX interrupt enable
- * @arg @ref I2C_IT_TXI TX interrupt enable
- *
- * @retval The new state of __INTERRUPT__ (SET or RESET).
- */
-#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
- (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Check whether the specified I2C flag is set or not.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref I2C_FLAG_TXE Transmit data register empty
- * @arg @ref I2C_FLAG_TXIS Transmit interrupt status
- * @arg @ref I2C_FLAG_RXNE Receive data register not empty
- * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
- * @arg @ref I2C_FLAG_AF Acknowledge failure received flag
- * @arg @ref I2C_FLAG_STOPF STOP detection flag
- * @arg @ref I2C_FLAG_TC Transfer complete (master mode)
- * @arg @ref I2C_FLAG_TCR Transfer complete reload
- * @arg @ref I2C_FLAG_BERR Bus error
- * @arg @ref I2C_FLAG_ARLO Arbitration lost
- * @arg @ref I2C_FLAG_OVR Overrun/Underrun
- * @arg @ref I2C_FLAG_PECERR PEC error in reception
- * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
- * @arg @ref I2C_FLAG_ALERT SMBus alert
- * @arg @ref I2C_FLAG_BUSY Bus busy
- * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
- *
- * @retval The new state of __FLAG__ (SET or RESET).
- */
-#define I2C_FLAG_MASK (0x0001FFFFU)
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
- (__FLAG__)) == (__FLAG__)) ? SET : RESET)
-
-/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg @ref I2C_FLAG_TXE Transmit data register empty
- * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
- * @arg @ref I2C_FLAG_AF Acknowledge failure received flag
- * @arg @ref I2C_FLAG_STOPF STOP detection flag
- * @arg @ref I2C_FLAG_BERR Bus error
- * @arg @ref I2C_FLAG_ARLO Arbitration lost
- * @arg @ref I2C_FLAG_OVR Overrun/Underrun
- * @arg @ref I2C_FLAG_PECERR PEC error in reception
- * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
- * @arg @ref I2C_FLAG_ALERT SMBus alert
- *
- * @retval None
- */
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
- ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
- ((__HANDLE__)->Instance->ICR = (__FLAG__)))
-
-/** @brief Enable the specified I2C peripheral.
- * @param __HANDLE__ specifies the I2C Handle.
- * @retval None
- */
-#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief Disable the specified I2C peripheral.
- * @param __HANDLE__ specifies the I2C Handle.
- * @retval None
- */
-#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
- * @param __HANDLE__ specifies the I2C Handle.
- * @retval None
- */
-#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
-/**
- * @}
- */
-
-/* Include I2C HAL Extended module */
-#include "stm32l4xx_hal_i2c_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2C_Exported_Functions
- * @{
- */
-
-/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-/* Initialization and de-initialization functions******************************/
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
-
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
- pI2C_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-/* IO operation functions ****************************************************/
-/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
- uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
- uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
- uint32_t Timeout);
-
-/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
- uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
- uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
-
-/******* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
- uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
- uint32_t XferOptions);
-/**
- * @}
- */
-
-/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
-/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
-void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
-/**
- * @}
- */
-
-/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
- * @{
- */
-/* Peripheral State, Mode and Error functions *********************************/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Constants I2C Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Macro I2C Private Macros
- * @{
- */
-
-#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
- ((MODE) == I2C_ADDRESSINGMODE_10BIT))
-
-#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
- ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
-
-#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
- ((MASK) == I2C_OA2_MASK01) || \
- ((MASK) == I2C_OA2_MASK02) || \
- ((MASK) == I2C_OA2_MASK03) || \
- ((MASK) == I2C_OA2_MASK04) || \
- ((MASK) == I2C_OA2_MASK05) || \
- ((MASK) == I2C_OA2_MASK06) || \
- ((MASK) == I2C_OA2_MASK07))
-
-#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
- ((CALL) == I2C_GENERALCALL_ENABLE))
-
-#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
- ((STRETCH) == I2C_NOSTRETCH_ENABLE))
-
-#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
- ((SIZE) == I2C_MEMADD_SIZE_16BIT))
-
-#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
- ((MODE) == I2C_AUTOEND_MODE) || \
- ((MODE) == I2C_SOFTEND_MODE))
-
-#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
- ((REQUEST) == I2C_GENERATE_START_READ) || \
- ((REQUEST) == I2C_GENERATE_START_WRITE) || \
- ((REQUEST) == I2C_NO_STARTSTOP))
-
-#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
- ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
- ((REQUEST) == I2C_NEXT_FRAME) || \
- ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
- ((REQUEST) == I2C_LAST_FRAME) || \
- ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
- IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
-
-#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
- ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
-
-#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
- (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
- I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
- I2C_CR2_RD_WRN)))
-
-#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
- >> 16U))
-#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
- >> 16U))
-#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
-#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
-#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
-
-#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
- (uint16_t)(0xFF00U))) >> 8U)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
-
-#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
- (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
- (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
- (~I2C_CR2_RD_WRN)) : \
- (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
- (I2C_CR2_ADD10) | (I2C_CR2_START)) & \
- (~I2C_CR2_RD_WRN)))
-
-#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
- ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
-#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
-/**
- * @}
- */
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Functions I2C Private Functions
- * @{
- */
-/* Private functions are defined in stm32l4xx_hal_i2c.c file */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32L4xx_HAL_I2C_H */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h
deleted file mode 100644
index 15ed69a..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_i2c_ex.h
- * @author MCD Application Team
- * @brief Header file of I2C HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L4xx_HAL_I2C_EX_H
-#define STM32L4xx_HAL_I2C_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup I2CEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
- * @{
- */
-
-/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
- * @{
- */
-#define I2C_ANALOGFILTER_ENABLE 0x00000000U
-#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
-/**
- * @}
- */
-
-/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
- * @{
- */
-#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
-#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
-#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
-#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
-#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
-#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
-#else
-#define I2C_FASTMODEPLUS_PB8 (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported */
-#define I2C_FASTMODEPLUS_PB9 (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported */
-#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
-#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
-#if defined(SYSCFG_CFGR1_I2C2_FMP)
-#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
-#else
-#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */
-#endif /* SYSCFG_CFGR1_I2C2_FMP */
-#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
-#if defined(SYSCFG_CFGR1_I2C4_FMP)
-#define I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
-#else
-#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */
-#endif /* SYSCFG_CFGR1_I2C4_FMP */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
- * @{
- */
-
-/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
- * @{
- */
-/* Peripheral Control functions ************************************************/
-HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
-HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
-/**
- * @}
- */
-
-/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
- * @{
- */
-HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
-/**
- * @}
- */
-
-/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
- * @{
- */
-void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
-void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
- * @{
- */
-#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
- ((FILTER) == I2C_ANALOGFILTER_DISABLE))
-
-#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
-
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
- ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
- (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
- (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
- (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
- (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
- (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
- (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3) || \
- (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))
-/**
- * @}
- */
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
- * @{
- */
-/* Private functions are defined in stm32l4xx_hal_i2c_ex.c file */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L4xx_HAL_I2C_EX_H */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h
deleted file mode 100644
index e90fcb7..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h
+++ /dev/null
@@ -1,411 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_pwr.h
- * @author MCD Application Team
- * @brief Header file of PWR HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L4xx_HAL_PWR_H
-#define STM32L4xx_HAL_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PWR
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Types PWR Exported Types
- * @{
- */
-
-/**
- * @brief PWR PVD configuration structure definition
- */
-typedef struct
-{
- uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
- This parameter can be a value of @ref PWR_PVD_detection_level. */
-
- uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref PWR_PVD_Mode. */
-}PWR_PVDTypeDef;
-
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Constants PWR Exported Constants
- * @{
- */
-
-
-/** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels
- * @{
- */
-#define PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0 /*!< PVD threshold around 2.0 V */
-#define PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1 /*!< PVD threshold around 2.2 V */
-#define PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2 /*!< PVD threshold around 2.4 V */
-#define PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3 /*!< PVD threshold around 2.5 V */
-#define PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4 /*!< PVD threshold around 2.6 V */
-#define PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5 /*!< PVD threshold around 2.8 V */
-#define PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6 /*!< PVD threshold around 2.9 V */
-#define PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7 /*!< External input analog voltage (compared internally to VREFINT) */
-/**
- * @}
- */
-
-/** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode
- * @{
- */
-#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */
-#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
-/**
- * @}
- */
-
-
-
-
-/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode
- * @{
- */
-#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) /*!< Regulator in main mode */
-#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR /*!< Regulator in low-power mode */
-/**
- * @}
- */
-
-/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
- * @{
- */
-#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode */
-#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */
-/**
- * @}
- */
-
-/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
- * @{
- */
-#define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */
-#define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */
-/**
- * @}
- */
-
-
-/** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line
- * @{
- */
-#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
-/**
- * @}
- */
-
-/** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line
- * @{
- */
-#define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000) /*!< Event line 16 Connected to the PVD Event Line */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PWR_Exported_Macros PWR Exported Macros
- * @{
- */
-
-/** @brief Check whether or not a specific PWR flag is set.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
- * was received from the WKUP pin 1.
- * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
- * was received from the WKUP pin 2.
- * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
- * was received from the WKUP pin 3.
- * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
- * was received from the WKUP pin 4.
- * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
- * was received from the WKUP pin 5.
- * @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system
- * entered StandBy mode.
- * @arg @ref PWR_FLAG_EXT_SMPS External SMPS Ready Flag. When available on device, indicates
- * that external switch can be closed to connect to the external SMPS, when the Range 2
- * of internal regulator is ready.
- * @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on
- * the internal wakeup line.
- * @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the
- * low-power regulator is ready.
- * @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the
- * regulator is ready in main mode or is in low-power mode.
- * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready
- * in the selected voltage range or is still changing to the required voltage level.
- * @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is
- * below or above the selected PVD threshold.
- * @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is
- * is below or above PVM1 threshold (applicable when USB feature is supported).
- @if STM32L486xx
- * @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is
- * is below or above PVM2 threshold (applicable when VDDIO2 is present on device).
- @endif
- * @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
- * is below or above PVM3 threshold.
- * @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is
- * is below or above PVM4 threshold.
- *
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1) ?\
- (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
- (PWR->SR2 & (1U << ((__FLAG__) & 31U))) )
-
-/** @brief Clear a specific PWR flag.
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
- * was received from the WKUP pin 1.
- * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
- * was received from the WKUP pin 2.
- * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
- * was received from the WKUP pin 3.
- * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
- * was received from the WKUP pin 4.
- * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
- * was received from the WKUP pin 5.
- * @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.
- * @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system
- * entered Standby mode.
- * @retval None
- */
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
- (PWR->SCR = (__FLAG__)) :\
- (PWR->SCR = (1U << ((__FLAG__) & 31U))) )
-/**
- * @brief Enable the PVD Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Disable the PVD Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Enable the PVD Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
-
-/**
- * @brief Disable the PVD Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
-
-/**
- * @brief Enable the PVD Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Disable the PVD Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Enable the PVD Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
-
-
-/**
- * @brief Disable the PVD Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
-
-
-/**
- * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0)
-
-/**
- * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0)
-
-/**
- * @brief Generate a Software interrupt on selected EXTI line.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Check whether or not the PVD EXTI interrupt flag is set.
- * @retval EXTI PVD Line Status.
- */
-#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Clear the PVD EXTI interrupt flag.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
-
-/**
- * @}
- */
-
-
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup PWR_Private_Macros PWR Private Macros
- * @{
- */
-
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
- ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
- ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
- ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
-
-#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\
- ((MODE) == PWR_PVD_MODE_IT_RISING) ||\
- ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\
- ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\
- ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\
- ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\
- ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))
-
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
- ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
-
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
-
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
-
-/**
- * @}
- */
-
-/* Include PWR HAL Extended module */
-#include "stm32l4xx_hal_pwr_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup PWR_Exported_Functions PWR Exported Functions
- * @{
- */
-
-/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization and de-initialization functions *******************************/
-void HAL_PWR_DeInit(void);
-void HAL_PWR_EnableBkUpAccess(void);
-void HAL_PWR_DisableBkUpAccess(void);
-
-/**
- * @}
- */
-
-/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
- * @{
- */
-
-/* Peripheral Control functions ************************************************/
-HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
-void HAL_PWR_EnablePVD(void);
-void HAL_PWR_DisablePVD(void);
-
-
-/* WakeUp pins configuration functions ****************************************/
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
-
-/* Low Power modes configuration functions ************************************/
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-void HAL_PWR_EnterSTANDBYMode(void);
-
-void HAL_PWR_EnableSleepOnExit(void);
-void HAL_PWR_DisableSleepOnExit(void);
-void HAL_PWR_EnableSEVOnPend(void);
-void HAL_PWR_DisableSEVOnPend(void);
-
-void HAL_PWR_PVDCallback(void);
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32L4xx_HAL_PWR_H */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h
deleted file mode 100644
index 71dbbb3..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h
+++ /dev/null
@@ -1,929 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_pwr_ex.h
- * @author MCD Application Team
- * @brief Header file of PWR HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L4xx_HAL_PWR_EX_H
-#define STM32L4xx_HAL_PWR_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PWREx
- * @{
- */
-
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
- * @{
- */
-
-
-/**
- * @brief PWR PVM configuration structure definition
- */
-typedef struct
-{
- uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold.
- This parameter can be a value of @ref PWREx_PVM_Type.
- @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported).
-@if STM32L486xx
- @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device).
-@endif
- @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V.
- @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */
-
- uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref PWREx_PVM_Mode. */
-}PWR_PVMTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
- * @{
- */
-
-/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
- * @{
- */
-#define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polariry */
-/**
- * @}
- */
-
-
-/** @defgroup PWREx_WakeUp_Pins PWR wake-up pins
- * @{
- */
-#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
-#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
-#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
-#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
-#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
-#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
-#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
-#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
-#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
-#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
-#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<IMR2, PWR_EXTI_LINE_PVM1)
-
-/**
- * @brief Disable the PVM1 Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
-
-/**
- * @brief Enable the PVM1 Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
-
-/**
- * @brief Disable the PVM1 Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
-
-/**
- * @brief Enable the PVM1 Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
-
-/**
- * @brief Disable the PVM1 Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
-
-/**
- * @brief Enable the PVM1 Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
-
-
-/**
- * @brief Disable the PVM1 Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
-
-
-/**
- * @brief PVM1 EXTI line configuration: set rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0)
-
-/**
- * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0)
-
-/**
- * @brief Generate a Software interrupt on selected EXTI line.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
-
-/**
- * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
- * @retval EXTI PVM1 Line Status.
- */
-#define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
-
-/**
- * @brief Clear the PVM1 EXTI flag.
- * @retval None
- */
-#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
-
-#endif /* PWR_CR2_PVME1 */
-
-
-#if defined(PWR_CR2_PVME2)
-/**
- * @brief Enable the PVM2 Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
-
-/**
- * @brief Disable the PVM2 Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
-
-/**
- * @brief Enable the PVM2 Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
-
-/**
- * @brief Disable the PVM2 Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
-
-/**
- * @brief Enable the PVM2 Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
-
-/**
- * @brief Disable the PVM2 Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
-
-/**
- * @brief Enable the PVM2 Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
-
-
-/**
- * @brief Disable the PVM2 Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
-
-
-/**
- * @brief PVM2 EXTI line configuration: set rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0)
-
-/**
- * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0)
-
-/**
- * @brief Generate a Software interrupt on selected EXTI line.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
-
-/**
- * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.
- * @retval EXTI PVM2 Line Status.
- */
-#define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
-
-/**
- * @brief Clear the PVM2 EXTI flag.
- * @retval None
- */
-#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
-
-#endif /* PWR_CR2_PVME2 */
-
-
-/**
- * @brief Enable the PVM3 Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
-
-/**
- * @brief Disable the PVM3 Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
-
-/**
- * @brief Enable the PVM3 Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
-
-/**
- * @brief Disable the PVM3 Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
-
-/**
- * @brief Enable the PVM3 Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
-
-/**
- * @brief Disable the PVM3 Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
-
-/**
- * @brief Enable the PVM3 Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
-
-
-/**
- * @brief Disable the PVM3 Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
-
-
-/**
- * @brief PVM3 EXTI line configuration: set rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0)
-
-/**
- * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0)
-
-/**
- * @brief Generate a Software interrupt on selected EXTI line.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
-
-/**
- * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
- * @retval EXTI PVM3 Line Status.
- */
-#define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
-
-/**
- * @brief Clear the PVM3 EXTI flag.
- * @retval None
- */
-#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
-
-
-
-
-/**
- * @brief Enable the PVM4 Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
-
-/**
- * @brief Disable the PVM4 Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
-
-/**
- * @brief Enable the PVM4 Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
-
-/**
- * @brief Disable the PVM4 Event Line.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
-
-/**
- * @brief Enable the PVM4 Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
-
-/**
- * @brief Disable the PVM4 Extended Interrupt Rising Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
-
-/**
- * @brief Enable the PVM4 Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
-
-
-/**
- * @brief Disable the PVM4 Extended Interrupt Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
-
-
-/**
- * @brief PVM4 EXTI line configuration: set rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0)
-
-/**
- * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0)
-
-/**
- * @brief Generate a Software interrupt on selected EXTI line.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
-
-/**
- * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.
- * @retval EXTI PVM4 Line Status.
- */
-#define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
-
-/**
- * @brief Clear the PVM4 EXTI flag.
- * @retval None
- */
-#define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
-
-
-/**
- * @brief Configure the main internal regulator output voltage.
- * @param __REGULATOR__ specifies the regulator output voltage to achieve
- * a tradeoff between performance and power consumption.
- * This parameter can be one of the following values:
- * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
- * typical output voltage at 1.2 V,
- * system frequency up to 80 MHz.
- * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
- * typical output voltage at 1.0 V,
- * system frequency up to 26 MHz.
- * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
- * whether or not VOSF flag is cleared when moving from range 2 to range 1. User
- * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
- * @retval None
- */
-#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
- __IO uint32_t tmpreg; \
- MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
- UNUSED(tmpreg); \
- } while(0)
-
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
- * @{
- */
-
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
- ((PIN) == PWR_WAKEUP_PIN2) || \
- ((PIN) == PWR_WAKEUP_PIN3) || \
- ((PIN) == PWR_WAKEUP_PIN4) || \
- ((PIN) == PWR_WAKEUP_PIN5) || \
- ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
- ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
- ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
- ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
- ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
- ((PIN) == PWR_WAKEUP_PIN1_LOW) || \
- ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
- ((PIN) == PWR_WAKEUP_PIN3_LOW) || \
- ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
- ((PIN) == PWR_WAKEUP_PIN5_LOW))
-
-#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
- ((TYPE) == PWR_PVM_2) ||\
- ((TYPE) == PWR_PVM_3) ||\
- ((TYPE) == PWR_PVM_4))
-#elif defined (STM32L471xx)
-#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\
- ((TYPE) == PWR_PVM_3) ||\
- ((TYPE) == PWR_PVM_4))
-#endif
-
-#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx)
-#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
- ((TYPE) == PWR_PVM_3) ||\
- ((TYPE) == PWR_PVM_4))
-#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L442xx) || defined (STM32L451xx)
-#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\
- ((TYPE) == PWR_PVM_4))
-#endif
-
-#define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\
- ((MODE) == PWR_PVM_MODE_IT_RISING) ||\
- ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\
- ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\
- ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\
- ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\
- ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
-
-#if defined(PWR_CR5_R1MODE)
-#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \
- ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
- ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
-#else
-#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
- ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
-#endif
-
-
-#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
- ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
-
-#define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
- ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
-
-#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
-
-
-#if defined (STM32L412xx) || defined (STM32L422xx)
-#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
- ((GPIO) == PWR_GPIO_B) ||\
- ((GPIO) == PWR_GPIO_C) ||\
- ((GPIO) == PWR_GPIO_D) ||\
- ((GPIO) == PWR_GPIO_H))
-#elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \
- defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
-#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
- ((GPIO) == PWR_GPIO_B) ||\
- ((GPIO) == PWR_GPIO_C) ||\
- ((GPIO) == PWR_GPIO_D) ||\
- ((GPIO) == PWR_GPIO_E) ||\
- ((GPIO) == PWR_GPIO_H))
-#elif defined (STM32L432xx) || defined (STM32L442xx)
-#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
- ((GPIO) == PWR_GPIO_B) ||\
- ((GPIO) == PWR_GPIO_C) ||\
- ((GPIO) == PWR_GPIO_H))
-#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
-#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
- ((GPIO) == PWR_GPIO_B) ||\
- ((GPIO) == PWR_GPIO_C) ||\
- ((GPIO) == PWR_GPIO_D) ||\
- ((GPIO) == PWR_GPIO_E) ||\
- ((GPIO) == PWR_GPIO_F) ||\
- ((GPIO) == PWR_GPIO_G) ||\
- ((GPIO) == PWR_GPIO_H))
-#elif defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
- ((GPIO) == PWR_GPIO_B) ||\
- ((GPIO) == PWR_GPIO_C) ||\
- ((GPIO) == PWR_GPIO_D) ||\
- ((GPIO) == PWR_GPIO_E) ||\
- ((GPIO) == PWR_GPIO_F) ||\
- ((GPIO) == PWR_GPIO_G) ||\
- ((GPIO) == PWR_GPIO_H) ||\
- ((GPIO) == PWR_GPIO_I))
-#endif
-
-#if defined (STM32L4P5xx) || defined (STM32L4Q5xx)
-#define IS_PWR_SRAM2_RETENTION(SRAM2) (((SRAM2) == PWR_NO_SRAM2_RETENTION) ||\
- ((SRAM2) == PWR_FULL_SRAM2_RETENTION) ||\
- ((SRAM2) == PWR_4KBYTES_SRAM2_RETENTION))
-#else
-#define IS_PWR_SRAM2_RETENTION(SRAM2) (((SRAM2) == PWR_NO_SRAM2_RETENTION) ||\
- ((SRAM2) == PWR_FULL_SRAM2_RETENTION))
-#endif
-
-/**
- * @}
- */
-
-
-/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
- * @{
- */
-
-/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
- * @{
- */
-
-
-/* Peripheral Control functions **********************************************/
-uint32_t HAL_PWREx_GetVoltageRange(void);
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
-void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
-void HAL_PWREx_DisableBatteryCharging(void);
-#if defined(PWR_CR2_USV)
-void HAL_PWREx_EnableVddUSB(void);
-void HAL_PWREx_DisableVddUSB(void);
-#endif /* PWR_CR2_USV */
-#if defined(PWR_CR2_IOSV)
-void HAL_PWREx_EnableVddIO2(void);
-void HAL_PWREx_DisableVddIO2(void);
-#endif /* PWR_CR2_IOSV */
-void HAL_PWREx_EnableInternalWakeUpLine(void);
-void HAL_PWREx_DisableInternalWakeUpLine(void);
-HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
-HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
-HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
-HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
-void HAL_PWREx_EnablePullUpPullDownConfig(void);
-void HAL_PWREx_DisablePullUpPullDownConfig(void);
-void HAL_PWREx_EnableSRAM2ContentRetention(void);
-void HAL_PWREx_DisableSRAM2ContentRetention(void);
-HAL_StatusTypeDef HAL_PWREx_SetSRAM2ContentRetention(uint32_t SRAM2Size);
-#if defined(PWR_CR1_RRSTP)
-void HAL_PWREx_EnableSRAM3ContentRetention(void);
-void HAL_PWREx_DisableSRAM3ContentRetention(void);
-#endif /* PWR_CR1_RRSTP */
-#if defined(PWR_CR3_DSIPDEN)
-void HAL_PWREx_EnableDSIPinsPDActivation(void);
-void HAL_PWREx_DisableDSIPinsPDActivation(void);
-#endif /* PWR_CR3_DSIPDEN */
-#if defined(PWR_CR2_PVME1)
-void HAL_PWREx_EnablePVM1(void);
-void HAL_PWREx_DisablePVM1(void);
-#endif /* PWR_CR2_PVME1 */
-#if defined(PWR_CR2_PVME2)
-void HAL_PWREx_EnablePVM2(void);
-void HAL_PWREx_DisablePVM2(void);
-#endif /* PWR_CR2_PVME2 */
-void HAL_PWREx_EnablePVM3(void);
-void HAL_PWREx_DisablePVM3(void);
-void HAL_PWREx_EnablePVM4(void);
-void HAL_PWREx_DisablePVM4(void);
-HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
-#if defined(PWR_CR3_ENULP)
-void HAL_PWREx_EnableBORPVD_ULP(void);
-void HAL_PWREx_DisableBORPVD_ULP(void);
-#endif /* PWR_CR3_ENULP */
-#if defined(PWR_CR4_EXT_SMPS_ON)
-void HAL_PWREx_EnableExtSMPS_0V95(void);
-void HAL_PWREx_DisableExtSMPS_0V95(void);
-#endif /* PWR_CR4_EXT_SMPS_ON */
-
-
-/* Low Power modes configuration functions ************************************/
-void HAL_PWREx_EnableLowPowerRunMode(void);
-HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
-void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
-void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
-void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
-void HAL_PWREx_EnterSHUTDOWNMode(void);
-
-void HAL_PWREx_PVD_PVM_IRQHandler(void);
-#if defined(PWR_CR2_PVME1)
-void HAL_PWREx_PVM1Callback(void);
-#endif /* PWR_CR2_PVME1 */
-#if defined(PWR_CR2_PVME2)
-void HAL_PWREx_PVM2Callback(void);
-#endif /* PWR_CR2_PVME2 */
-void HAL_PWREx_PVM3Callback(void);
-void HAL_PWREx_PVM4Callback(void);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32L4xx_HAL_PWR_EX_H */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h
deleted file mode 100644
index 260918d..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h
+++ /dev/null
@@ -1,4883 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_rcc.h
- * @author MCD Application Team
- * @brief Header file of RCC HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file in
- * the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L4xx_HAL_RCC_H
-#define STM32L4xx_HAL_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RCC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RCC_Exported_Types RCC Exported Types
- * @{
- */
-
-/**
- * @brief RCC PLL configuration structure definition
- */
-typedef struct
-{
- uint32_t PLLState; /*!< The new state of the PLL.
- This parameter can be a value of @ref RCC_PLL_Config */
-
- uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
- This parameter must be a value of @ref RCC_PLL_Clock_Source */
-
- uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
- This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.
- This parameter must be a number between Min_Data = 1 and Max_Data = 8 on the other devices */
-
- uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
- This parameter must be a number between Min_Data = 8 and Max_Data = 86 */
-
-#if defined(RCC_PLLP_SUPPORT)
- uint32_t PLLP; /*!< PLLP: Division factor for SAI clock.
- This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
-#endif /* RCC_PLLP_SUPPORT */
-
- uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks.
- This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
-
- uint32_t PLLR; /*!< PLLR: Division for the main system clock.
- User have to set the PLLR parameter correctly to not exceed max frequency 120MHZ
- on STM32L4Rx/STM32L4Sx devices else 80MHz on the other devices.
- This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
-
-}RCC_PLLInitTypeDef;
-
-/**
- * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition
- */
-typedef struct
-{
- uint32_t OscillatorType; /*!< The oscillators to be configured.
- This parameter can be a value of @ref RCC_Oscillator_Type */
-
- uint32_t HSEState; /*!< The new state of the HSE.
- This parameter can be a value of @ref RCC_HSE_Config */
-
- uint32_t LSEState; /*!< The new state of the LSE.
- This parameter can be a value of @ref RCC_LSE_Config */
-
- uint32_t HSIState; /*!< The new state of the HSI.
- This parameter can be a value of @ref RCC_HSI_Config */
-
- uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
- This parameter must be a number between Min_Data = 0 and Max_Data = 31 on
- STM32L43x/STM32L44x/STM32L47x/STM32L48x devices.
- This parameter must be a number between Min_Data = 0 and Max_Data = 127 on
- the other devices */
-
- uint32_t LSIState; /*!< The new state of the LSI.
- This parameter can be a value of @ref RCC_LSI_Config */
-#if defined(RCC_CSR_LSIPREDIV)
-
- uint32_t LSIDiv; /*!< The division factor of the LSI.
- This parameter can be a value of @ref RCC_LSI_Div */
-#endif /* RCC_CSR_LSIPREDIV */
-
- uint32_t MSIState; /*!< The new state of the MSI.
- This parameter can be a value of @ref RCC_MSI_Config */
-
- uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
-
- uint32_t MSIClockRange; /*!< The MSI frequency range.
- This parameter can be a value of @ref RCC_MSI_Clock_Range */
-
- uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices).
- This parameter can be a value of @ref RCC_HSI48_Config */
-
- RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */
-
-}RCC_OscInitTypeDef;
-
-/**
- * @brief RCC System, AHB and APB busses clock configuration structure definition
- */
-typedef struct
-{
- uint32_t ClockType; /*!< The clock to be configured.
- This parameter can be a value of @ref RCC_System_Clock_Type */
-
- uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
- This parameter can be a value of @ref RCC_System_Clock_Source */
-
- uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
- This parameter can be a value of @ref RCC_AHB_Clock_Source */
-
- uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-
- uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-
-}RCC_ClkInitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_Exported_Constants RCC Exported Constants
- * @{
- */
-
-/** @defgroup RCC_Timeout_Value Timeout Values
- * @{
- */
-#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
-/**
- * @}
- */
-
-/** @defgroup RCC_Oscillator_Type Oscillator Type
- * @{
- */
-#define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */
-#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */
-#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */
-#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */
-#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */
-#define RCC_OSCILLATORTYPE_MSI 0x00000010U /*!< MSI to configure */
-#if defined(RCC_HSI48_SUPPORT)
-#define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */
-#endif /* RCC_HSI48_SUPPORT */
-/**
- * @}
- */
-
-/** @defgroup RCC_HSE_Config HSE Config
- * @{
- */
-#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */
-#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
-#define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_Config LSE Config
- * @{
- */
-#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */
-#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
-#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */
-#if defined(RCC_BDCR_LSESYSDIS)
-#define RCC_LSE_ON_RTC_ONLY (RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< LSE clock activation without propagation to system */
-#define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< External clock source for LSE clock without propagation to system */
-#endif /* RCC_BDCR_LSESYSDIS */
-/**
- * @}
- */
-
-/** @defgroup RCC_HSI_Config HSI Config
- * @{
- */
-#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */
-#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
-
-#if defined(RCC_ICSCR_HSITRIM_6)
-#define RCC_HSICALIBRATION_DEFAULT 0x40U /*!< Default HSI calibration trimming value 64 on devices other than STM32L43x/STM32L44x/STM32L47x/STM32L48x */
-#else
-#define RCC_HSICALIBRATION_DEFAULT 0x10U /*!< Default HSI calibration trimming value 16 on STM32L43x/STM32L44x/STM32L47x/STM32L48x devices */
-#endif /* RCC_ICSCR_HSITRIM_6 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LSI_Config LSI Config
- * @{
- */
-#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */
-#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
-/**
- * @}
- */
-#if defined(RCC_CSR_LSIPREDIV)
-
-/** @defgroup RCC_LSI_Div LSI Div
- * @{
- */
-#define RCC_LSI_DIV1 0x00000000U /*!< LSI clock not divided */
-#define RCC_LSI_DIV128 RCC_CSR_LSIPREDIV /*!< LSI clock divided by 128 */
-/**
- * @}
- */
-#endif /* RCC_CSR_LSIPREDIV */
-
-/** @defgroup RCC_MSI_Config MSI Config
- * @{
- */
-#define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */
-#define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */
-
-#define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */
-/**
- * @}
- */
-
-#if defined(RCC_HSI48_SUPPORT)
-/** @defgroup RCC_HSI48_Config HSI48 Config
- * @{
- */
-#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */
-#define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */
-/**
- * @}
- */
-#else
-/** @defgroup RCC_HSI48_Config HSI48 Config
- * @{
- */
-#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */
-/**
- * @}
- */
-#endif /* RCC_HSI48_SUPPORT */
-
-/** @defgroup RCC_PLL_Config PLL Config
- * @{
- */
-#define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */
-#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */
-#define RCC_PLL_ON 0x00000002U /*!< PLL activation */
-/**
- * @}
- */
-
-#if defined(RCC_PLLP_SUPPORT)
-/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
- * @{
- */
-#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
-#define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */
-#define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */
-#define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */
-#define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */
-#define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */
-#define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */
-#define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */
-#define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */
-#define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */
-#define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */
-#define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */
-#define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */
-#define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */
-#define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */
-#define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */
-#define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */
-#define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */
-#define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */
-#define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */
-#define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */
-#define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */
-#define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */
-#define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */
-#define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */
-#define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */
-#define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */
-#define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */
-#define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */
-#define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */
-#define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */
-#else
-#define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */
-#define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */
-#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
-/**
- * @}
- */
-#endif /* RCC_PLLP_SUPPORT */
-
-/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
- * @{
- */
-#define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */
-#define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */
-#define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */
-#define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */
-/**
- * @}
- */
-
-/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
- * @{
- */
-#define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */
-#define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */
-#define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */
-#define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
- * @{
- */
-#define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */
-#define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */
-#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */
-#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Clock_Output PLL Clock Output
- * @{
- */
-#if defined(RCC_PLLSAI2_SUPPORT)
-#define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */
-#elif defined(RCC_PLLSAI1_SUPPORT)
-#define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */
-#endif /* RCC_PLLSAI2_SUPPORT */
-#define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */
-#define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */
-/**
- * @}
- */
-#if defined(RCC_PLLSAI1_SUPPORT)
-
-/** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output
- * @{
- */
-#define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */
-#define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */
-#define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */
-/**
- * @}
- */
-#endif /* RCC_PLLSAI1_SUPPORT */
-
-#if defined(RCC_PLLSAI2_SUPPORT)
-
-/** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output
- * @{
- */
-#define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */
-#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
-#define RCC_PLLSAI2_DSICLK RCC_PLLSAI2CFGR_PLLSAI2QEN /*!< PLLDSICLK selection from PLLSAI2 */
-#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
-#define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */
-#else
-#define RCC_PLLSAI2_LTDCCLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLLTDCCLK selection from PLLSAI2 */
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
-/**
- * @}
- */
-
-#endif /* RCC_PLLSAI2_SUPPORT */
-
-/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
- * @{
- */
-#define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */
-#define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */
-#define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */
-#define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */
-#define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */
-#define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */
-#define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */
-#define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */
-#define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */
-#define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */
-#define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */
-#define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Type System Clock Type
- * @{
- */
-#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */
-#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */
-#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */
-#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source System Clock Source
- * @{
- */
-#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */
-#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
-#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
-#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
- * @{
- */
-#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
- * @{
- */
-#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
-#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
-#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
-#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
-#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
-#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
-#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
-#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
-#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
- * @{
- */
-#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
-#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
-#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
-#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
-#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
-/**
- * @}
- */
-
-/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
- * @{
- */
-#define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_MCO_Index MCO Index
- * @{
- */
-#define RCC_MCO1 0x00000000U
-#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
-/**
- * @}
- */
-
-/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
- * @{
- */
-#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */
-#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
-#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */
-#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
-#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
-#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */
-#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
-#define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
-#if defined(RCC_HSI48_SUPPORT)
-#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */
-#endif /* RCC_HSI48_SUPPORT */
-/**
- * @}
- */
-
-/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
- * @{
- */
-#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
-#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
-#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
-#define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
-#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
-/**
- * @}
- */
-
-/** @defgroup RCC_Interrupt Interrupts
- * @{
- */
-#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
-#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
-#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */
-#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */
-#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
-#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
-#if defined(RCC_PLLSAI1_SUPPORT)
-#define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */
-#endif /* RCC_PLLSAI1_SUPPORT */
-#if defined(RCC_PLLSAI2_SUPPORT)
-#define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */
-#endif /* RCC_PLLSAI2_SUPPORT */
-#define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
-#define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
-#if defined(RCC_HSI48_SUPPORT)
-#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
-#endif /* RCC_HSI48_SUPPORT */
-/**
- * @}
- */
-
-/** @defgroup RCC_Flag Flags
- * Elements values convention: XXXYYYYYb
- * - YYYYY : Flag position in the register
- * - XXX : Register index
- * - 001: CR register
- * - 010: BDCR register
- * - 011: CSR register
- * - 100: CRRCR register
- * @{
- */
-/* Flags in the CR register */
-#define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */
-#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */
-#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */
-#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */
-#if defined(RCC_PLLSAI1_SUPPORT)
-#define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */
-#endif /* RCC_PLLSAI1_SUPPORT */
-#if defined(RCC_PLLSAI2_SUPPORT)
-#define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */
-#endif /* RCC_PLLSAI2_SUPPORT */
-
-/* Flags in the BDCR register */
-#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */
-#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */
-
-/* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */
-#define RCC_FLAG_FWRST ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos) /*!< Firewall reset flag */
-#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */
-#define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */
-#define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */
-#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */
-#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */
-#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */
-#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */
-
-#if defined(RCC_HSI48_SUPPORT)
-/* Flags in the CRRCR register */
-#define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */
-#endif /* RCC_HSI48_SUPPORT */
-/**
- * @}
- */
-
-/** @defgroup RCC_LSEDrive_Config LSE Drive Config
- * @{
- */
-#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */
-#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */
-#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */
-#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */
-/**
- * @}
- */
-
-/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock
- * @{
- */
-#define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */
-#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Macros RCC Exported Macros
- * @{
- */
-
-/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
- * @brief Enable or disable the AHB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#if defined(DMAMUX1)
-#define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* DMAMUX1 */
-
-#define __HAL_RCC_FLASH_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_CRC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_TSC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#if defined(DMA2D)
-#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* DMA2D */
-
-#if defined(GFXMMU)
-#define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* GFXMMU */
-
-
-#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
-
-#define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
-
-#if defined(DMAMUX1)
-#define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN)
-#endif /* DMAMUX1 */
-
-#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
-
-#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
-
-#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
-
-#if defined(DMA2D)
-#define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN)
-#endif /* DMA2D */
-
-#if defined(GFXMMU)
-#define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN)
-#endif /* GFXMMU */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
- * @brief Enable or disable the AHB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#if defined(GPIOD)
-#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* GPIOD */
-
-#if defined(GPIOE)
-#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* GPIOE */
-
-#if defined(GPIOF)
-#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* GPIOF */
-
-#if defined(GPIOG)
-#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* GPIOG */
-
-#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#if defined(GPIOI)
-#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* GPIOI */
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#if defined(DCMI)
-#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* DCMI */
-
-#if defined(PKA)
-#define __HAL_RCC_PKA_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* PKA */
-
-#if defined(AES)
-#define __HAL_RCC_AES_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* AES */
-
-#if defined(HASH)
-#define __HAL_RCC_HASH_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* HASH */
-
-#define __HAL_RCC_RNG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#if defined(OCTOSPIM)
-#define __HAL_RCC_OSPIM_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* OCTOSPIM */
-
-#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)
-#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */
-
-#if defined(SDMMC2)
-#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* SDMMC2 */
-
-
-#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
-
-#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
-
-#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
-
-#if defined(GPIOD)
-#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
-#endif /* GPIOD */
-
-#if defined(GPIOE)
-#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
-#endif /* GPIOE */
-
-#if defined(GPIOF)
-#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
-#endif /* GPIOF */
-
-#if defined(GPIOG)
-#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
-#endif /* GPIOG */
-
-#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
-
-#if defined(GPIOI)
-#define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN)
-#endif /* GPIOI */
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
-
-#if defined(DCMI)
-#define __HAL_RCC_DCMI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN)
-#endif /* DCMI */
-
-#if defined(PKA)
-#define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN)
-#endif /* PKA */
-
-#if defined(AES)
-#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
-#endif /* AES */
-
-#if defined(HASH)
-#define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN)
-#endif /* HASH */
-
-#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
-
-#if defined(OCTOSPIM)
-#define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN)
-#endif /* OCTOSPIM */
-
-#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)
-#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN)
-#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */
-
-#if defined(SDMMC2)
-#define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN)
-#endif /* SDMMC2 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
- * @brief Enable or disable the AHB3 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* FMC_BANK1 */
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* QUADSPI */
-
-#if defined(OCTOSPI1)
-#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* OCTOSPI1 */
-
-#if defined(OCTOSPI2)
-#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* OCTOSPI2 */
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
-#endif /* FMC_BANK1 */
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
-#endif /* QUADSPI */
-
-#if defined(OCTOSPI1)
-#define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN)
-#endif /* OCTOSPI1 */
-
-#if defined(OCTOSPI2)
-#define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN)
-#endif /* OCTOSPI2 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
- * @brief Enable or disable the APB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#if defined(TIM3)
-#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* TIM3 */
-
-#if defined(TIM4)
-#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* TIM4 */
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#if defined(TIM7)
-#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* TIM7 */
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* LCD */
-
-#if defined(RCC_APB1ENR1_RTCAPBEN)
-#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* RCC_APB1ENR1_RTCAPBEN */
-
-#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#if defined(SPI2)
-#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* SPI2 */
-
-#if defined(SPI3)
-#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* SPI3 */
-
-#define __HAL_RCC_USART2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#if defined(USART3)
-#define __HAL_RCC_USART3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* USART3 */
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#if defined(I2C2)
-#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* I2C2 */
-
-#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* I2C4 */
-
-#if defined(CRS)
-#define __HAL_RCC_CRS_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* CRS */
-
-#if defined(CAN1)
-#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* CAN1 */
-
-#if defined(CAN2)
-#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* CAN2 */
-
-#if defined(USB)
-#define __HAL_RCC_USB_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* USB */
-
-#define __HAL_RCC_PWR_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#if defined(DAC1)
-#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* DAC1 */
-
-#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#if defined(SWPMI1)
-#define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* SWPMI1 */
-
-#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
- UNUSED(tmpreg); \
- } while(0)
-
-
-#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
-
-#if defined(TIM3)
-#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
-#endif /* TIM3 */
-
-#if defined(TIM4)
-#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
-#endif /* TIM4 */
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
-
-#if defined(TIM7)
-#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
-#endif /* TIM7 */
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);
-#endif /* LCD */
-
-#if defined(RCC_APB1ENR1_RTCAPBEN)
-#define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
-#endif /* RCC_APB1ENR1_RTCAPBEN */
-
-#if defined(SPI2)
-#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
-#endif /* SPI2 */
-
-#if defined(SPI3)
-#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
-#endif /* SPI3 */
-
-#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
-
-#if defined(USART3)
-#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
-#endif /* USART3 */
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
-
-#if defined(I2C2)
-#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
-#endif /* I2C2 */
-
-#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
-#endif /* I2C4 */
-
-#if defined(CRS)
-#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
-#endif /* CRS */
-
-#if defined(CAN1)
-#define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)
-#endif /* CAN1 */
-
-#if defined(CAN2)
-#define __HAL_RCC_CAN2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN)
-#endif /* CAN2 */
-
-#if defined(USB)
-#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN);
-#endif /* USB */
-
-#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
-
-#if defined(DAC1)
-#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)
-#endif /* DAC1 */
-
-#define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)
-
-#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
-
-#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
-
-#if defined(SWPMI1)
-#define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)
-#endif /* SWPMI1 */
-
-#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
- * @brief Enable or disable the APB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
-#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
-
-#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#if defined(TIM8)
-#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* TIM8 */
-
-#define __HAL_RCC_USART1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
- UNUSED(tmpreg); \
- } while(0)
-
-
-#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
- UNUSED(tmpreg); \
- } while(0)
-
-#if defined(TIM17)
-#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* TIM17 */
-
-#if defined(SAI1)
-#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* SAI1 */
-
-#if defined(SAI2)
-#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* SAI2 */
-
-#if defined(DFSDM1_Filter0)
-#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* DFSDM1_Filter0 */
-
-#if defined(LTDC)
-#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* LTDC */
-
-#if defined(DSI)
-#define __HAL_RCC_DSI_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \
- UNUSED(tmpreg); \
- } while(0)
-#endif /* DSI */
-
-
-#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
-
-#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
-#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)
-#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
-
-#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
-
-#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
-
-#if defined(TIM8)
-#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
-#endif /* TIM8 */
-
-#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
-
-#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
-
-#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
-
-#if defined(TIM17)
-#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
-#endif /* TIM17 */
-
-#if defined(SAI1)
-#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
-#endif /* SAI1 */
-
-#if defined(SAI2)
-#define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
-#endif /* SAI2 */
-
-#if defined(DFSDM1_Filter0)
-#define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN)
-#endif /* DFSDM1_Filter0 */
-
-#if defined(LTDC)
-#define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN)
-#endif /* LTDC */
-
-#if defined(DSI)
-#define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN)
-#endif /* DSI */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
- * @brief Check whether the AHB1 peripheral clock is enabled or not.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U)
-
-#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U)
-
-#if defined(DMAMUX1)
-#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U)
-#endif /* DMAMUX1 */
-
-#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)
-
-#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U)
-
-#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U)
-
-#if defined(DMA2D)
-#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U)
-#endif /* DMA2D */
-
-#if defined(GFXMMU)
-#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != 0U)
-#endif /* GFXMMU */
-
-
-#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U)
-
-#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U)
-
-#if defined(DMAMUX1)
-#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U)
-#endif /* DMAMUX1 */
-
-#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)
-
-#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U)
-
-#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U)
-
-#if defined(DMA2D)
-#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U)
-#endif /* DMA2D */
-
-#if defined(GFXMMU)
-#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == 0U)
-#endif /* GFXMMU */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
- * @brief Check whether the AHB2 peripheral clock is enabled or not.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U)
-
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U)
-
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U)
-
-#if defined(GPIOD)
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U)
-#endif /* GPIOD */
-
-#if defined(GPIOE)
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U)
-#endif /* GPIOE */
-
-#if defined(GPIOF)
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U)
-#endif /* GPIOF */
-
-#if defined(GPIOG)
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U)
-#endif /* GPIOG */
-
-#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U)
-
-#if defined(GPIOI)
-#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != 0U)
-#endif /* GPIOI */
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != 0U)
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U)
-
-#if defined(DCMI)
-#define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != 0U)
-#endif /* DCMI */
-
-#if defined(PKA)
-#define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) != 0U)
-#endif /* PKA */
-
-#if defined(AES)
-#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U)
-#endif /* AES */
-
-#if defined(HASH)
-#define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U)
-#endif /* HASH */
-
-#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U)
-
-#if defined(OCTOSPIM)
-#define __HAL_RCC_OSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN) != 0U)
-#endif /* OCTOSPIM */
-
-#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) != 0U)
-#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */
-
-#if defined(SDMMC2)
-#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN) != 0U)
-#endif /* SDMMC2 */
-
-
-#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U)
-
-#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U)
-
-#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U)
-
-#if defined(GPIOD)
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U)
-#endif /* GPIOD */
-
-#if defined(GPIOE)
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U)
-#endif /* GPIOE */
-
-#if defined(GPIOF)
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U)
-#endif /* GPIOF */
-
-#if defined(GPIOG)
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U)
-#endif /* GPIOG */
-
-#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == 0U)
-
-#if defined(GPIOI)
-#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == 0U)
-#endif /* GPIOI */
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == 0U)
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == 0U)
-
-#if defined(DCMI)
-#define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == 0U)
-#endif /* DCMI */
-
-#if defined(PKA)
-#define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) == 0U)
-#endif /* PKA */
-
-#if defined(AES)
-#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U)
-#endif /* AES */
-
-#if defined(HASH)
-#define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == 0U)
-#endif /* HASH */
-
-#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U)
-
-#if defined(OCTOSPIM)
-#define __HAL_RCC_OSPIM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN) == 0U)
-#endif /* OCTOSPIM */
-
-#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) == 0U)
-#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */
-
-#if defined(SDMMC2)
-#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN) == 0U)
-#endif /* SDMMC2 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
- * @brief Check whether the AHB3 peripheral clock is enabled or not.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U)
-#endif /* FMC_BANK1 */
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U)
-#endif /* QUADSPI */
-
-#if defined(OCTOSPI1)
-#define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) != 0U)
-#endif /* OCTOSPI1 */
-
-#if defined(OCTOSPI2)
-#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN) != 0U)
-#endif /* OCTOSPI2 */
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
-#endif /* FMC_BANK1 */
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U)
-#endif /* QUADSPI */
-
-#if defined(OCTOSPI1)
-#define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) == 0U)
-#endif /* OCTOSPI1 */
-
-#if defined(OCTOSPI2)
-#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN) == 0U)
-#endif /* OCTOSPI2 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
- * @brief Check whether the APB1 peripheral clock is enabled or not.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U)
-
-#if defined(TIM3)
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U)
-#endif /* TIM3 */
-
-#if defined(TIM4)
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U)
-#endif /* TIM4 */
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U)
-
-#if defined(TIM7)
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U)
-#endif /* TIM7 */
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != 0U)
-#endif /* LCD */
-
-#if defined(RCC_APB1ENR1_RTCAPBEN)
-#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U)
-#endif /* RCC_APB1ENR1_RTCAPBEN */
-
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U)
-
-#if defined(SPI2)
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)
-#endif /* SPI2 */
-
-#if defined(SPI3)
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U)
-#endif /* SPI3 */
-
-#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)
-
-#if defined(USART3)
-#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)
-#endif /* USART3 */
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U)
-
-#if defined(I2C2)
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U)
-#endif /* I2C2 */
-
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U)
-#endif /* I2C4 */
-
-#if defined(CRS)
-#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U)
-#endif /* CRS */
-
-#if defined(CAN1)
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != 0U)
-#endif /* CAN1 */
-
-#if defined(CAN2)
-#define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != 0U)
-#endif /* CAN2 */
-
-#if defined(USB)
-#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != 0U)
-#endif /* USB */
-
-#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U)
-
-#if defined(DAC1)
-#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != 0U)
-#endif /* DAC1 */
-
-#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != 0U)
-
-#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U)
-
-#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U)
-
-#if defined(SWPMI1)
-#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != 0U)
-#endif /* SWPMI1 */
-
-#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U)
-
-
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U)
-
-#if defined(TIM3)
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U)
-#endif /* TIM3 */
-
-#if defined(TIM4)
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U)
-#endif /* TIM4 */
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U)
-
-#if defined(TIM7)
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U)
-#endif /* TIM7 */
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == 0U)
-#endif /* LCD */
-
-#if defined(RCC_APB1ENR1_RTCAPBEN)
-#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U)
-#endif /* RCC_APB1ENR1_RTCAPBEN */
-
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U)
-
-#if defined(SPI2)
-#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U)
-#endif /* SPI2 */
-
-#if defined(SPI3)
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U)
-#endif /* SPI3 */
-
-#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U)
-
-#if defined(USART3)
-#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U)
-#endif /* USART3 */
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U)
-
-#if defined(I2C2)
-#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U)
-#endif /* I2C2 */
-
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U)
-#endif /* I2C4 */
-
-#if defined(CRS)
-#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U)
-#endif /* CRS */
-
-#if defined(CAN1)
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == 0U)
-#endif /* CAN1 */
-
-#if defined(CAN2)
-#define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == 0U)
-#endif /* CAN2 */
-
-#if defined(USB)
-#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == 0U)
-#endif /* USB */
-
-#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U)
-
-#if defined(DAC1)
-#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == 0U)
-#endif /* DAC1 */
-
-#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == 0U)
-
-#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U)
-
-#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U)
-
-#if defined(SWPMI1)
-#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == 0U)
-#endif /* SWPMI1 */
-
-#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
- * @brief Check whether the APB2 peripheral clock is enabled or not.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)
-
-#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != 0U)
-
-#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != 0U)
-#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
-
-#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)
-
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)
-
-#if defined(TIM8)
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U)
-#endif /* TIM8 */
-
-#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)
-
-#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U)
-
-#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U)
-
-#if defined(TIM17)
-#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U)
-#endif /* TIM17 */
-
-#if defined(SAI1)
-#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)
-#endif /* SAI1 */
-
-#if defined(SAI2)
-#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U)
-#endif /* SAI2 */
-
-#if defined(DFSDM1_Filter0)
-#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != 0U)
-#endif /* DFSDM1_Filter0 */
-
-#if defined(LTDC)
-#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U)
-#endif /* LTDC */
-
-#if defined(DSI)
-#define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != 0U)
-#endif /* DSI */
-
-
-#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)
-
-#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == 0U)
-#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
-
-#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U)
-
-#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U)
-
-#if defined(TIM8)
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U)
-#endif /* TIM8 */
-
-#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U)
-
-#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U)
-
-#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U)
-
-#if defined(TIM17)
-#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U)
-#endif /* TIM17 */
-
-#if defined(SAI1)
-#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U)
-#endif /* SAI1 */
-
-#if defined(SAI2)
-#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U)
-#endif /* SAI2 */
-
-#if defined(DFSDM1_Filter0)
-#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == 0U)
-#endif /* DFSDM1_Filter0 */
-
-#if defined(LTDC)
-#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U)
-#endif /* LTDC */
-
-#if defined(DSI)
-#define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == 0U)
-#endif /* DSI */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
- * @brief Force or release AHB1 peripheral reset.
- * @{
- */
-#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFUL)
-
-#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
-
-#define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
-
-#if defined(DMAMUX1)
-#define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
-#endif /* DMAMUX1 */
-
-#define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
-
-#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
-
-#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
-
-#if defined(DMA2D)
-#define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
-#endif /* DMA2D */
-
-#if defined(GFXMMU)
-#define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST)
-#endif /* GFXMMU */
-
-
-#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000UL)
-
-#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
-
-#define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
-
-#if defined(DMAMUX1)
-#define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
-#endif /* DMAMUX1 */
-
-#define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
-
-#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
-
-#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
-
-#if defined(DMA2D)
-#define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
-#endif /* DMA2D */
-
-#if defined(GFXMMU)
-#define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST)
-#endif /* GFXMMU */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
- * @brief Force or release AHB2 peripheral reset.
- * @{
- */
-#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFUL)
-
-#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
-
-#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
-
-#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
-
-#if defined(GPIOD)
-#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
-#endif /* GPIOD */
-
-#if defined(GPIOE)
-#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
-#endif /* GPIOE */
-
-#if defined(GPIOF)
-#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
-#endif /* GPIOF */
-
-#if defined(GPIOG)
-#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
-#endif /* GPIOG */
-
-#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
-
-#if defined(GPIOI)
-#define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)
-#endif /* GPIOI */
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
-
-#if defined(DCMI)
-#define __HAL_RCC_DCMI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)
-#endif /* DCMI */
-
-#if defined(PKA)
-#define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST)
-#endif /* PKA */
-
-#if defined(AES)
-#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
-#endif /* AES */
-
-#if defined(HASH)
-#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)
-#endif /* HASH */
-
-#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
-
-#if defined(OCTOSPIM)
-#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST)
-#endif /* OCTOSPIM */
-
-#if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST)
-#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST)
-#endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */
-
-#if defined(SDMMC2)
-#define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC2RST)
-#endif /* SDMMC2 */
-
-
-#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000UL)
-
-#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
-
-#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
-
-#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
-
-#if defined(GPIOD)
-#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
-#endif /* GPIOD */
-
-#if defined(GPIOE)
-#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
-#endif /* GPIOE */
-
-#if defined(GPIOF)
-#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
-#endif /* GPIOF */
-
-#if defined(GPIOG)
-#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
-#endif /* GPIOG */
-
-#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
-
-#if defined(GPIOI)
-#define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)
-#endif /* GPIOI */
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
-
-#if defined(DCMI)
-#define __HAL_RCC_DCMI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)
-#endif /* DCMI */
-
-#if defined(PKA)
-#define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST)
-#endif /* PKA */
-
-#if defined(AES)
-#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
-#endif /* AES */
-
-#if defined(HASH)
-#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)
-#endif /* HASH */
-
-#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
-
-#if defined(OCTOSPIM)
-#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST)
-#endif /* OCTOSPIM */
-
-#if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST)
-#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST)
-#endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */
-
-#if defined(SDMMC2)
-#define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC2RST)
-#endif /* SDMMC2 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
- * @brief Force or release AHB3 peripheral reset.
- * @{
- */
-#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFUL)
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
-#endif /* FMC_BANK1 */
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
-#endif /* QUADSPI */
-
-#if defined(OCTOSPI1)
-#define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST)
-#endif /* OCTOSPI1 */
-
-#if defined(OCTOSPI2)
-#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST)
-#endif /* OCTOSPI2 */
-
-#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000UL)
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
-#endif /* FMC_BANK1 */
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
-#endif /* QUADSPI */
-
-#if defined(OCTOSPI1)
-#define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST)
-#endif /* OCTOSPI1 */
-
-#if defined(OCTOSPI2)
-#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST)
-#endif /* OCTOSPI2 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
- * @brief Force or release APB1 peripheral reset.
- * @{
- */
-#define __HAL_RCC_APB1_FORCE_RESET() do { \
- WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFUL); \
- WRITE_REG(RCC->APB1RSTR2, 0xFFFFFFFFUL); \
- } while(0)
-
-#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
-
-#if defined(TIM3)
-#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
-#endif /* TIM3 */
-
-#if defined(TIM4)
-#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
-#endif /* TIM4 */
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
-
-#if defined(TIM7)
-#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
-#endif /* TIM7 */
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
-#endif /* LCD */
-
-#if defined(SPI2)
-#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
-#endif /* SPI2 */
-
-#if defined(SPI3)
-#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
-#endif /* SPI3 */
-
-#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
-
-#if defined(USART3)
-#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
-#endif /* USART3 */
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
-
-#if defined(I2C2)
-#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
-#endif /* I2C2 */
-
-#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
-#endif /* I2C4 */
-
-#if defined(CRS)
-#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
-#endif /* CRS */
-
-#if defined(CAN1)
-#define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
-#endif /* CAN1 */
-
-#if defined(CAN2)
-#define __HAL_RCC_CAN2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)
-#endif /* CAN2 */
-
-#if defined(USB)
-#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
-#endif /* USB */
-
-#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
-
-#if defined(DAC1)
-#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
-#endif /* DAC1 */
-
-#define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
-
-#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
-
-#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
-
-#if defined(SWPMI1)
-#define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
-#endif /* SWPMI1 */
-
-#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
-
-
-#define __HAL_RCC_APB1_RELEASE_RESET() do { \
- WRITE_REG(RCC->APB1RSTR1, 0x00000000UL); \
- WRITE_REG(RCC->APB1RSTR2, 0x00000000UL); \
- } while(0)
-
-#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
-
-#if defined(TIM3)
-#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
-#endif /* TIM3 */
-
-#if defined(TIM4)
-#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
-#endif /* TIM4 */
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
-
-#if defined(TIM7)
-#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
-#endif /* TIM7 */
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
-#endif /* LCD */
-
-#if defined(SPI2)
-#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
-#endif /* SPI2 */
-
-#if defined(SPI3)
-#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
-#endif /* SPI3 */
-
-#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
-
-#if defined(USART3)
-#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
-#endif /* USART3 */
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
-
-#if defined(I2C2)
-#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
-#endif /* I2C2 */
-
-#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
-#endif /* I2C4 */
-
-#if defined(CRS)
-#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
-#endif /* CRS */
-
-#if defined(CAN1)
-#define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
-#endif /* CAN1 */
-
-#if defined(CAN2)
-#define __HAL_RCC_CAN2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)
-#endif /* CAN2 */
-
-#if defined(USB)
-#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
-#endif /* USB */
-
-#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
-
-#if defined(DAC1)
-#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
-#endif /* DAC1 */
-
-#define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
-
-#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
-
-#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
-
-#if defined(SWPMI1)
-#define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
-#endif /* SWPMI1 */
-
-#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
- * @brief Force or release APB2 peripheral reset.
- * @{
- */
-#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFUL)
-
-#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
-
-#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)
-#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
-#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */
-
-#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
-
-#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
-
-#if defined(TIM8)
-#define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
-#endif /* TIM8 */
-
-#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
-
-#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
-
-#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
-
-#if defined(TIM17)
-#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
-#endif /* TIM17 */
-
-#if defined(SAI1)
-#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
-#endif /* SAI1 */
-
-#if defined(SAI2)
-#define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
-#endif /* SAI2 */
-
-#if defined(DFSDM1_Filter0)
-#define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
-#endif /* DFSDM1_Filter0 */
-
-#if defined(LTDC)
-#define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST)
-#endif /* LTDC */
-
-#if defined(DSI)
-#define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST)
-#endif /* DSI */
-
-
-#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000UL)
-
-#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
-
-#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)
-#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
-#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */
-
-#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
-
-#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
-
-#if defined(TIM8)
-#define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
-#endif /* TIM8 */
-
-#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
-
-#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
-
-#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
-
-#if defined(TIM17)
-#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
-#endif /* TIM17 */
-
-#if defined(SAI1)
-#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
-#endif /* SAI1 */
-
-#if defined(SAI2)
-#define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
-#endif /* SAI2 */
-
-#if defined(DFSDM1_Filter0)
-#define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
-#endif /* DFSDM1_Filter0 */
-
-#if defined(LTDC)
-#define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST)
-#endif /* LTDC */
-
-#if defined(DSI)
-#define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST)
-#endif /* DSI */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
- * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
-
-#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
-
-#if defined(DMAMUX1)
-#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
-#endif /* DMAMUX1 */
-
-#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
-
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
-
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
-
-#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
-
-#if defined(DMA2D)
-#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
-#endif /* DMA2D */
-
-#if defined(GFXMMU)
-#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN)
-#endif /* GFXMMU */
-
-
-#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
-
-#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
-
-#if defined(DMAMUX1)
-#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
-#endif /* DMAMUX1 */
-
-#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
-
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
-
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
-
-#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
-
-#if defined(DMA2D)
-#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
-#endif /* DMA2D */
-
-#if defined(GFXMMU)
-#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN)
-#endif /* GFXMMU */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
- * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
-
-#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
-
-#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
-
-#if defined(GPIOD)
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
-#endif /* GPIOD */
-
-#if defined(GPIOE)
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
-#endif /* GPIOE */
-
-#if defined(GPIOF)
-#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
-#endif /* GPIOF */
-
-#if defined(GPIOG)
-#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
-#endif /* GPIOG */
-
-#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
-
-#if defined(GPIOI)
-#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)
-#endif /* GPIOI */
-
-#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
-
-#if defined(SRAM3)
-#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN)
-#endif /* SRAM3 */
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
-
-#if defined(DCMI)
-#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)
-#endif /* DCMI */
-
-#if defined(PKA)
-#define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN)
-#endif /* PKA */
-
-#if defined(AES)
-#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
-#endif /* AES */
-
-#if defined(HASH)
-#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)
-#endif /* HASH */
-
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
-
-#if defined(OCTOSPIM)
-#define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN)
-#endif /* OCTOSPIM */
-
-#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN)
-#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */
-
-#if defined(SDMMC2)
-#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC2SMEN)
-#endif /* SDMMC2 */
-
-
-#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
-
-#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
-
-#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
-
-#if defined(GPIOD)
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
-#endif /* GPIOD */
-
-#if defined(GPIOE)
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
-#endif /* GPIOE */
-
-#if defined(GPIOF)
-#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
-#endif /* GPIOF */
-
-#if defined(GPIOG)
-#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
-#endif /* GPIOG */
-
-#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
-
-#if defined(GPIOI)
-#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)
-#endif /* GPIOI */
-
-#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
-
-#if defined(SRAM3)
-#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN)
-#endif /* SRAM3 */
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
-
-#if defined(DCMI)
-#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)
-#endif /* DCMI */
-
-#if defined(PKA)
-#define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN)
-#endif /* PKA */
-
-#if defined(AES)
-#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
-#endif /* AES */
-
-#if defined(HASH)
-#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)
-#endif /* HASH */
-
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
-
-#if defined(OCTOSPIM)
-#define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN)
-#endif /* OCTOSPIM */
-
-#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN)
-#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */
-
-#if defined(SDMMC2)
-#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC2SMEN)
-#endif /* SDMMC2 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
- * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
-#endif /* QUADSPI */
-
-#if defined(OCTOSPI1)
-#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN)
-#endif /* OCTOSPI1 */
-
-#if defined(OCTOSPI2)
-#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN)
-#endif /* OCTOSPI2 */
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
-#endif /* FMC_BANK1 */
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
-#endif /* QUADSPI */
-
-#if defined(OCTOSPI1)
-#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN)
-#endif /* OCTOSPI1 */
-
-#if defined(OCTOSPI2)
-#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN)
-#endif /* OCTOSPI2 */
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
-#endif /* FMC_BANK1 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
- * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
-
-#if defined(TIM3)
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
-#endif /* TIM3 */
-
-#if defined(TIM4)
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
-#endif /* TIM4 */
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
-
-#if defined(TIM7)
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
-#endif /* TIM7 */
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
-#endif /* LCD */
-
-#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
-#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
-
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
-
-#if defined(SPI2)
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
-#endif /* SPI2 */
-
-#if defined(SPI3)
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
-#endif /* SPI3 */
-
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
-
-#if defined(USART3)
-#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
-#endif /* USART3 */
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
-
-#if defined(I2C2)
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
-#endif /* I2C2 */
-
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
-#endif /* I2C4 */
-
-#if defined(CRS)
-#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
-#endif /* CRS */
-
-#if defined(CAN1)
-#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
-#endif /* CAN1 */
-
-#if defined(CAN2)
-#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)
-#endif /* CAN2 */
-
-#if defined(USB)
-#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
-#endif /* USB */
-
-#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
-
-#if defined(DAC1)
-#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
-#endif /* DAC1 */
-
-#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
-
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
-
-#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
-
-#if defined(SWPMI1)
-#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
-#endif /* SWPMI1 */
-
-#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
-
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
-
-#if defined(TIM3)
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
-#endif /* TIM3 */
-
-#if defined(TIM4)
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
-#endif /* TIM4 */
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
-
-#if defined(TIM7)
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
-#endif /* TIM7 */
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
-#endif /* LCD */
-
-#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
-#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
-
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
-
-#if defined(SPI2)
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
-#endif /* SPI2 */
-
-#if defined(SPI3)
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
-#endif /* SPI3 */
-
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
-
-#if defined(USART3)
-#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
-#endif /* USART3 */
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
-
-#if defined(I2C2)
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
-#endif /* I2C2 */
-
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
-#endif /* I2C4 */
-
-#if defined(CRS)
-#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
-#endif /* CRS */
-
-#if defined(CAN1)
-#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
-#endif /* CAN1 */
-
-#if defined(CAN2)
-#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)
-#endif /* CAN2 */
-
-#if defined(USB)
-#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
-#endif /* USB */
-
-#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
-
-#if defined(DAC1)
-#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
-#endif /* DAC1 */
-
-#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
-
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
-
-#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
-
-#if defined(SWPMI1)
-#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
-#endif /* SWPMI1 */
-
-#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
- * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
-
-#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
-#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
-
-#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
-
-#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
-
-#if defined(TIM8)
-#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
-#endif /* TIM8 */
-
-#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
-
-#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
-
-#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
-
-#if defined(TIM17)
-#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
-#endif /* TIM17 */
-
-#if defined(SAI1)
-#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
-#endif /* SAI1 */
-
-#if defined(SAI2)
-#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
-#endif /* SAI2 */
-
-#if defined(DFSDM1_Filter0)
-#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
-#endif /* DFSDM1_Filter0 */
-
-#if defined(LTDC)
-#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN)
-#endif /* LTDC */
-
-#if defined(DSI)
-#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN)
-#endif /* DSI */
-
-
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
-
-#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
-#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
-
-#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
-
-#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
-
-#if defined(TIM8)
-#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
-#endif /* TIM8 */
-
-#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
-
-#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
-
-#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
-
-#if defined(TIM17)
-#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
-#endif /* TIM17 */
-
-#if defined(SAI1)
-#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
-#endif /* SAI1 */
-
-#if defined(SAI2)
-#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
-#endif /* SAI2 */
-
-#if defined(DFSDM1_Filter0)
-#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
-#endif /* DFSDM1_Filter0 */
-
-#if defined(LTDC)
-#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN)
-#endif /* LTDC */
-
-#if defined(DSI)
-#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN)
-#endif /* DSI */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
- * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U)
-
-#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U)
-
-#if defined(DMAMUX1)
-#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U)
-#endif /* DMAMUX1 */
-
-#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U)
-
-#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U)
-
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U)
-
-#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U)
-
-#if defined(DMA2D)
-#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != 0U)
-#endif /* DMA2D */
-
-#if defined(GFXMMU)
-#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != 0U)
-#endif /* GFXMMU */
-
-
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U)
-
-#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U)
-
-#if defined(DMAMUX1)
-#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U)
-#endif /* DMAMUX1 */
-
-#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U)
-
-#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U)
-
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U)
-
-#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == 0U)
-
-#if defined(DMA2D)
-#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == 0U)
-#endif /* DMA2D */
-
-#if defined(GFXMMU)
-#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == 0U)
-#endif /* GFXMMU */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
- * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U)
-
-#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U)
-
-#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U)
-
-#if defined(GPIOD)
-#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U)
-#endif /* GPIOD */
-
-#if defined(GPIOE)
-#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U)
-#endif /* GPIOE */
-
-#if defined(GPIOF)
-#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U)
-#endif /* GPIOF */
-
-#if defined(GPIOG)
-#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U)
-#endif /* GPIOG */
-
-#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != 0U)
-
-#if defined(GPIOI)
-#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != 0U)
-#endif /* GPIOI */
-
-#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U)
-
-#if defined(SRAM3)
-#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != 0U)
-#endif /* SRAM3 */
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != 0U)
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != 0U)
-
-#if defined(DCMI)
-#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != 0U)
-#endif /* DCMI */
-
-#if defined(PKA)
-#define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) != 0U)
-#endif /* PKA */
-
-#if defined(AES)
-#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U)
-#endif /* AES */
-
-#if defined(HASH)
-#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != 0U)
-#endif /* HASH */
-
-#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U)
-
-#if defined(OCTOSPIM)
-#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != 0U)
-#endif /* OCTOSPIM */
-
-#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)
-#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != 0U)
-#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */
-
-#if defined(SDMMC2)
-#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC2SMEN) != 0U)
-#endif /* SDMMC2 */
-
-
-#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U)
-
-#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U)
-
-#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U)
-
-#if defined(GPIOD)
-#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U)
-#endif /* GPIOD */
-
-#if defined(GPIOE)
-#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U)
-#endif /* GPIOE */
-
-#if defined(GPIOF)
-#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U)
-#endif /* GPIOF */
-
-#if defined(GPIOG)
-#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U)
-#endif /* GPIOG */
-
-#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == 0U)
-
-#if defined(GPIOI)
-#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == 0U)
-#endif /* GPIOI */
-
-#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U)
-
-#if defined(SRAM3)
-#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == 0U)
-#endif /* SRAM3 */
-
-#if defined(USB_OTG_FS)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == 0U)
-#endif /* USB_OTG_FS */
-
-#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == 0U)
-
-#if defined(DCMI)
-#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == 0U)
-#endif /* DCMI */
-
-#if defined(PKA)
-#define __HAL_RCC_PKA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) == 0U)
-#endif /* PKA */
-
-#if defined(AES)
-#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U)
-#endif /* AES */
-
-#if defined(HASH)
-#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == 0U)
-#endif /* HASH */
-
-#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U)
-
-#if defined(OCTOSPIM)
-#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == 0U)
-#endif /* OCTOSPIM */
-
-#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)
-#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == 0U)
-#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */
-
-#if defined(SDMMC2)
-#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC2SMEN) == 0U)
-#endif /* SDMMC2 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
- * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U)
-#endif /* QUADSPI */
-
-#if defined(OCTOSPI1)
-#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != 0U)
-#endif /* OCTOSPI1 */
-
-#if defined(OCTOSPI2)
-#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != 0U)
-#endif /* OCTOSPI2 */
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U)
-#endif /* FMC_BANK1 */
-
-
-#if defined(QUADSPI)
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U)
-#endif /* QUADSPI */
-
-#if defined(OCTOSPI1)
-#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == 0U)
-#endif /* OCTOSPI1 */
-
-#if defined(OCTOSPI2)
-#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == 0U)
-#endif /* OCTOSPI2 */
-
-#if defined(FMC_BANK1)
-#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U)
-#endif /* FMC_BANK1 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
- * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U)
-
-#if defined(TIM3)
-#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U)
-#endif /* TIM3 */
-
-#if defined(TIM4)
-#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U)
-#endif /* TIM4 */
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U)
-
-#if defined(TIM7)
-#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U)
-#endif /* TIM7 */
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != 0U)
-#endif /* LCD */
-
-#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
-#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U)
-#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
-
-#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U)
-
-#if defined(SPI2)
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U)
-#endif /* SPI2 */
-
-#if defined(SPI3)
-#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U)
-#endif /* SPI3 */
-
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U)
-
-#if defined(USART3)
-#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U)
-#endif /* USART3 */
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U)
-
-#if defined(I2C2)
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U)
-#endif /* I2C2 */
-
-#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U)
-#endif /* I2C4 */
-
-#if defined(CRS)
-#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U)
-#endif /* CRS */
-
-#if defined(CAN1)
-#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != 0U)
-#endif /* CAN1 */
-
-#if defined(CAN2)
-#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != 0U)
-#endif /* CAN2 */
-
-#if defined(USB)
-#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != 0U)
-#endif /* USB */
-
-#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U)
-
-#if defined(DAC1)
-#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != 0U)
-#endif /* DAC1 */
-
-#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != 0U)
-
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U)
-
-#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U)
-
-#if defined(SWPMI1)
-#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != 0U)
-#endif /* SWPMI1 */
-
-#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != 0U)
-
-
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U)
-
-#if defined(TIM3)
-#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U)
-#endif /* TIM3 */
-
-#if defined(TIM4)
-#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U)
-#endif /* TIM4 */
-
-#if defined(TIM5)
-#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U)
-#endif /* TIM5 */
-
-#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U)
-
-#if defined(TIM7)
-#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U)
-#endif /* TIM7 */
-
-#if defined(LCD)
-#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == 0U)
-#endif /* LCD */
-
-#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
-#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U)
-#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
-
-#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U)
-
-#if defined(SPI2)
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U)
-#endif /* SPI2 */
-
-#if defined(SPI3)
-#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U)
-#endif /* SPI3 */
-
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U)
-
-#if defined(USART3)
-#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U)
-#endif /* USART3 */
-
-#if defined(UART4)
-#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U)
-#endif /* UART4 */
-
-#if defined(UART5)
-#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U)
-#endif /* UART5 */
-
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U)
-
-#if defined(I2C2)
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U)
-#endif /* I2C2 */
-
-#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U)
-
-#if defined(I2C4)
-#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U)
-#endif /* I2C4 */
-
-#if defined(CRS)
-#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U)
-#endif /* CRS */
-
-#if defined(CAN1)
-#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == 0U)
-#endif /* CAN1 */
-
-#if defined(CAN2)
-#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == 0U)
-#endif /* CAN2 */
-
-#if defined(USB)
-#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == 0U)
-#endif /* USB */
-
-#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U)
-
-#if defined(DAC1)
-#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == 0U)
-#endif /* DAC1 */
-
-#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == 0U)
-
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U)
-
-#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U)
-
-#if defined(SWPMI1)
-#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == 0U)
-#endif /* SWPMI1 */
-
-#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == 0U)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
- * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-
-#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)
-
-#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
-#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != 0U)
-#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
-
-#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U)
-
-#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U)
-
-#if defined(TIM8)
-#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U)
-#endif /* TIM8 */
-
-#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U)
-
-#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U)
-
-#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U)
-
-#if defined(TIM17)
-#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U)
-#endif /* TIM17 */
-
-#if defined(SAI1)
-#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U)
-#endif /* SAI1 */
-
-#if defined(SAI2)
-#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != 0U)
-#endif /* SAI2 */
-
-#if defined(DFSDM1_Filter0)
-#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != 0U)
-#endif /* DFSDM1_Filter0 */
-
-#if defined(LTDC)
-#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != 0U)
-#endif /* LTDC */
-
-#if defined(DSI)
-#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != 0U)
-#endif /* DSI */
-
-
-#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)
-
-#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
-#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == 0U)
-#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
-
-#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U)
-
-#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U)
-
-#if defined(TIM8)
-#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U)
-#endif /* TIM8 */
-
-#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U)
-
-#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U)
-
-#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U)
-
-#if defined(TIM17)
-#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U)
-#endif /* TIM17 */
-
-#if defined(SAI1)
-#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U)
-#endif /* SAI1 */
-
-#if defined(SAI2)
-#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == 0U)
-#endif /* SAI2 */
-
-#if defined(DFSDM1_Filter0)
-#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == 0U)
-#endif /* DFSDM1_Filter0 */
-
-#if defined(LTDC)
-#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == 0U)
-#endif /* LTDC */
-
-#if defined(DSI)
-#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == 0U)
-#endif /* DSI */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
- * @{
- */
-
-/** @brief Macros to force or release the Backup domain reset.
- * @note This function resets the RTC peripheral (including the backup registers)
- * and the RTC clock source selection in RCC_CSR register.
- * @note The BKPSRAM is not affected by this reset.
- * @retval None
- */
-#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
-
-#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
- * @{
- */
-
-/** @brief Macros to enable or disable the RTC clock.
- * @note As the RTC is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
- * HAL_PWR_EnableBkUpAccess() function before to configure the RTC
- * (to be done once after reset).
- * @note These macros must be used after the RTC clock source was selected.
- * @retval None
- */
-#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
-
-#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
-
-/**
- * @}
- */
-
-/** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * It is used (enabled by hardware) as system clock source after startup
- * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
- * of the HSE used directly or indirectly as system clock (if the Clock
- * Security System CSS is enabled).
- * @note HSI can not be stopped if it is used as system clock source. In this case,
- * you have to select another source of the system clock then stop the HSI.
- * @note After enabling the HSI, the application software should wait on HSIRDY
- * flag to be set indicating that HSI clock is stable and can be used as
- * system clock source.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- * @retval None
- */
-#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
-
-#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
-
-/** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value
- * (default is RCC_HSICALIBRATION_DEFAULT).
- * This parameter must be a number between 0 and 31 on STM32L43x/STM32L44x/STM32L47x/STM32L48x
- * or between 0 and 127 on other devices.
- * @retval None
- */
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
- MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
-
-/**
- * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
- * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
- * @note The enable of this function has not effect on the HSION bit.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS)
-
-#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
-
-/**
- * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
- * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
- * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
- * speed because of the HSI startup time.
- * @note The enable of this function has not effect on the HSION bit.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
-
-#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
-
-/**
- * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
- * @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
- * It is used (enabled by hardware) as system clock source after
- * startup from Reset, wakeup from STOP and STANDBY mode, or in case
- * of failure of the HSE used directly or indirectly as system clock
- * (if the Clock Security System CSS is enabled).
- * @note MSI can not be stopped if it is used as system clock source.
- * In this case, you have to select another source of the system
- * clock then stop the MSI.
- * @note After enabling the MSI, the application software should wait on
- * MSIRDY flag to be set indicating that MSI clock is stable and can
- * be used as system clock source.
- * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
- * clock cycles.
- * @retval None
- */
-#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
-
-#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
-
-/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal MSI RC.
- * Refer to the Application Note AN3300 for more details on how to
- * calibrate the MSI.
- * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value
- * (default is RCC_MSICALIBRATION_DEFAULT).
- * This parameter must be a number between 0 and 255.
- * @retval None
- */
-#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
- MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos)
-
-/**
- * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
- * @note After restart from Reset , the MSI clock is around 4 MHz.
- * After stop the startup clock can be MSI (at any of its possible
- * frequencies, the one that was used before entering stop mode) or HSI.
- * After Standby its frequency can be selected between 4 possible values
- * (1, 2, 4 or 8 MHz).
- * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
- * (MSIRDY=1).
- * @note The MSI clock range after reset can be modified on the fly.
- * @param __MSIRANGEVALUE__ specifies the MSI clock range.
- * This parameter must be one of the following values:
- * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
- * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
- * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
- * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
- * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
- * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
- * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
- * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
- * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz
- * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz
- * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz
- * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
- * @retval None
- */
-#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \
- do { \
- SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \
- MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
- } while(0)
-
-/**
- * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
- * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
- * @param __MSIRANGEVALUE__ specifies the MSI clock range.
- * This parameter must be one of the following values:
- * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
- * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
- * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
- * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
- * @retval None
- */
-#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \
- MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
-
-/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
- * @retval MSI clock range.
- * This parameter must be one of the following values:
- * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
- * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
- * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
- * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
- * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
- * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
- * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
- * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
- * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz
- * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz
- * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz
- * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
- */
-#define __HAL_RCC_GET_MSI_RANGE() \
- ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ? \
- READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \
- (READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U))
-
-/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
- * @note After enabling the LSI, the application software should wait on
- * LSIRDY flag to be set indicating that LSI clock is stable and can
- * be used to clock the IWDG and/or the RTC.
- * @note LSI can not be disabled if the IWDG is running.
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
- * clock cycles.
- * @retval None
- */
-#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
-
-#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
-
-/**
- * @brief Macro to configure the External High Speed oscillator (HSE).
- * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
- * supported by this macro. User should request a transition to HSE Off
- * first and then HSE On or HSE Bypass.
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
- * software should wait on HSERDY flag to be set indicating that HSE clock
- * is stable and can be used to clock the PLL and/or system clock.
- * @note HSE state can not be changed if it is used directly or through the
- * PLL as system clock. In this case, you have to select another source
- * of the system clock then change the HSE state (ex. disable it).
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
- * @note This function reset the CSSON bit, so if the clock security system(CSS)
- * was previously enabled you have to enable it again after calling this
- * function.
- * @param __STATE__ specifies the new state of the HSE.
- * This parameter can be one of the following values:
- * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after
- * 6 HSE oscillator clock cycles.
- * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator.
- * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock.
- * @retval None
- */
-#define __HAL_RCC_HSE_CONFIG(__STATE__) \
- do { \
- if((__STATE__) == RCC_HSE_ON) \
- { \
- SET_BIT(RCC->CR, RCC_CR_HSEON); \
- } \
- else if((__STATE__) == RCC_HSE_BYPASS) \
- { \
- SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
- SET_BIT(RCC->CR, RCC_CR_HSEON); \
- } \
- else \
- { \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
- } \
- } while(0)
-
-/**
- * @brief Macro to configure the External Low Speed oscillator (LSE).
- * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
- * supported by this macro. User should request a transition to LSE Off
- * first and then LSE On or LSE Bypass.
- * @note As the LSE is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
- * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
- * (to be done once after reset).
- * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
- * software should wait on LSERDY flag to be set indicating that LSE clock
- * is stable and can be used to clock the RTC.
- * @param __STATE__ specifies the new state of the LSE.
- * This parameter can be one of the following values:
- * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after
- * 6 LSE oscillator clock cycles.
- * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.
- * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
- * @retval None
- */
-#define __HAL_RCC_LSE_CONFIG(__STATE__) \
- do { \
- if((__STATE__) == RCC_LSE_ON) \
- { \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- } \
- else if((__STATE__) == RCC_LSE_BYPASS) \
- { \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- } \
- else \
- { \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
- } \
- } while(0)
-
-#if defined(RCC_HSI48_SUPPORT)
-
-/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
- * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
- * @note After enabling the HSI48, the application software should wait on HSI48RDY
- * flag to be set indicating that HSI48 clock is stable.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
-
-#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
-
-#endif /* RCC_HSI48_SUPPORT */
-
-/** @brief Macros to configure the RTC clock (RTCCLK).
- * @note As the RTC clock configuration bits are in the Backup domain and write
- * access is denied to this domain after reset, you have to enable write
- * access using the Power Backup Access macro before to configure
- * the RTC clock source (to be done once after reset).
- * @note Once the RTC clock is configured it cannot be changed unless the
- * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
- * a Power On Reset (POR).
- *
- * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
- * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
- * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
- * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
- *
- * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
- * work in STOP and STANDBY modes, and can be used as wakeup source.
- * However, when the HSE clock is used as RTC clock source, the RTC
- * cannot be used in STOP and STANDBY modes.
- * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
- * RTC clock source).
- * @retval None
- */
-#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
- MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
-
-
-/** @brief Macro to get the RTC clock source.
- * @retval The returned value can be one of the following:
- * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
- * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
- * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
- * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
- */
-#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
-
-/** @brief Macros to enable or disable the main PLL.
- * @note After enabling the main PLL, the application software should wait on
- * PLLRDY flag to be set indicating that PLL clock is stable and can
- * be used as system clock source.
- * @note The main PLL can not be disabled if it is used as system clock source
- * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
- * @retval None
- */
-#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
-
-#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
-
-/** @brief Macro to configure the PLL clock source.
- * @note This function must be used only when the main PLL is disabled.
- * @param __PLLSOURCE__ specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
- * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
- * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
- * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
- * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
- * @retval None
- *
- */
-#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
-
-/** @brief Macro to configure the PLL source division factor M.
- * @note This function must be used only when the main PLL is disabled.
- * @param __PLLM__ specifies the division factor for PLL VCO input clock
- * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.
- * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices.
- * @note You have to set the PLLM parameter correctly to ensure that the VCO input
- * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
- * of 16 MHz to limit PLL jitter.
- * @retval None
- *
- */
-#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
-
-/**
- * @brief Macro to configure the main PLL clock source, multiplication and division factors.
- * @note This function must be used only when the main PLL is disabled.
- *
- * @param __PLLSOURCE__ specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
- * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
- * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
- * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
- * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
- *
- * @param __PLLM__ specifies the division factor for PLL VCO input clock.
- * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.
- * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices.
- * @note You have to set the PLLM parameter correctly to ensure that the VCO input
- * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
- * of 16 MHz to limit PLL jitter.
- *
- * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock.
- * This parameter must be a number between 8 and 86.
- * @note You have to set the PLLN parameter correctly to ensure that the VCO
- * output frequency is between 64 and 344 MHz.
- *
- * @param __PLLP__ specifies the division factor for SAI clock when SAI available on device.
- * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x
- * else (2 to 31).
- *
- * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
- * This parameter must be in the range (2, 4, 6 or 8).
- * @note If the USB OTG FS is used in your application, you have to set the
- * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
- * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
- * correctly.
- * @param __PLLR__ specifies the division factor for the main system clock.
- * @note You have to set the PLLR parameter correctly to not exceed 80MHZ.
- * This parameter must be in the range (2, 4, 6 or 8).
- * @retval None
- */
-#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
-
-#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
- MODIFY_REG(RCC->PLLCFGR, \
- (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
- RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLPDIV), \
- ((__PLLSOURCE__) | \
- (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \
- ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
- ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
- ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \
- ((uint32_t)(__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos)))
-
-#elif defined(RCC_PLLP_SUPPORT)
-
-#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
- MODIFY_REG(RCC->PLLCFGR, \
- (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
- RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP), \
- ((__PLLSOURCE__) | \
- (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \
- ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
- ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
- ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \
- (((__PLLP__) >> 4U) << RCC_PLLCFGR_PLLP_Pos)))
-
-#else
-
-#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLQ__,__PLLR__ ) \
- MODIFY_REG(RCC->PLLCFGR, \
- (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
- RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR), \
- ((__PLLSOURCE__) | \
- (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \
- ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
- ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
- ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
-
-#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
-
-/** @brief Macro to get the oscillator used as PLL clock source.
- * @retval The oscillator used as PLL clock source. The returned value can be one
- * of the following:
- * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
- * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
- * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
- * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
- */
-#define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))
-
-/**
- * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
- * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime
- * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
- * be stopped if used as System Clock.
- * @param __PLLCLOCKOUT__ specifies the PLL clock to be output.
- * This parameter can be one or a combination of the following values:
- * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
- * high-quality audio performance on SAI interface in case.
- * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),
- * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
- * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
- * @retval None
- */
-#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
-
-#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
-
-/**
- * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
- * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked.
- * This parameter can be one of the following values:
- * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
- * high-quality audio performance on SAI interface in case.
- * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),
- * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
- * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
- * @retval SET / RESET
- */
-#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
-
-/**
- * @brief Macro to configure the system clock source.
- * @param __SYSCLKSOURCE__ specifies the system clock source.
- * This parameter can be one of the following values:
- * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
- * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
- * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
- * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
- * @retval None
- */
-#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
-
-/** @brief Macro to get the clock source used as system clock.
- * @retval The clock source used as system clock. The returned value can be one
- * of the following:
- * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
- * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
- * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
- * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
- */
-#define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))
-
-/**
- * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
- * @note As the LSE is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
- * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
- * (to be done once after reset).
- * @param __LSEDRIVE__ specifies the new state of the LSE drive capability.
- * This parameter can be one of the following values:
- * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
- * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
- * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
- * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
- * @retval None
- */
-#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
- MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))
-
-/**
- * @brief Macro to configure the wake up from stop clock.
- * @param __STOPWUCLK__ specifies the clock source used after wake up from stop.
- * This parameter can be one of the following values:
- * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source
- * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source
- * @retval None
- */
-#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
-
-
-/** @brief Macro to configure the MCO clock.
- * @param __MCOCLKSOURCE__ specifies the MCO clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled
- * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
- * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
- @if STM32L443xx
- * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
- @endif
- @if STM32L4A6xx
- * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
- @endif
- * @param __MCODIV__ specifies the MCO clock prescaler.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
- * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
- * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
- * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
- * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
- */
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
- MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
-
-/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
- * @brief macros to manage the specified RCC Flags and interrupts.
- * @{
- */
-
-/** @brief Enable RCC interrupt(s).
- * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt
- * @arg @ref RCC_IT_MSIRDY HSI ready interrupt
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
- * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1
- * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
- * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
- @if STM32L443xx
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
- @endif
- @if STM32L4A6xx
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
- @endif
- * @retval None
- */
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
-
-/** @brief Disable RCC interrupt(s).
- * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt
- * @arg @ref RCC_IT_MSIRDY HSI ready interrupt
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
- * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1
- * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
- * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
- @if STM32L443xx
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
- @endif
- @if STM32L4A6xx
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
- @endif
- * @retval None
- */
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
-
-/** @brief Clear the RCC's interrupt pending bits.
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt
- * @arg @ref RCC_IT_MSIRDY MSI ready interrupt
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
- * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1
- * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
- * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
- * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
- @if STM32L443xx
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
- @endif
- @if STM32L4A6xx
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
- @endif
- * @retval None
- */
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__))
-
-/** @brief Check whether the RCC interrupt has occurred or not.
- * @param __INTERRUPT__ specifies the RCC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt
- * @arg @ref RCC_IT_MSIRDY MSI ready interrupt
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
- * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1
- * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
- * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
- * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
- @if STM32L443xx
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
- @endif
- @if STM32L4A6xx
- * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
- @endif
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Set RMVF bit to clear the reset flags.
- * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
- * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
- * @retval None
- */
-#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF)
-
-/** @brief Check whether the selected RCC flag is set or not.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready
- * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
- * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
- * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready
- * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready for devices with PLLSAI1
- * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2
- @if STM32L443xx
- * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
- @endif
- @if STM32L4A6xx
- * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
- @endif
- * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
- * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
- * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
- * @arg @ref RCC_FLAG_BORRST BOR reset
- * @arg @ref RCC_FLAG_OBLRST OBLRST reset
- * @arg @ref RCC_FLAG_PINRST Pin reset
- * @arg @ref RCC_FLAG_FWRST FIREWALL reset
- * @arg @ref RCC_FLAG_SFTRST Software reset
- * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
- * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
- * @arg @ref RCC_FLAG_LPWRRST Low Power reset
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#if defined(RCC_HSI48_SUPPORT)
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
- ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \
- ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
- ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \
- (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U)
-#else
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
- ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
- ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \
- (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U)
-#endif /* RCC_HSI48_SUPPORT */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RCC_Private_Constants RCC Private Constants
- * @{
- */
-/* Defines used for Flags */
-#define CR_REG_INDEX 1U
-#define BDCR_REG_INDEX 2U
-#define CSR_REG_INDEX 3U
-#if defined(RCC_HSI48_SUPPORT)
-#define CRRCR_REG_INDEX 4U
-#endif /* RCC_HSI48_SUPPORT */
-
-#define RCC_FLAG_MASK 0x1FU
-
-/* Defines Oscillator Masks */
-#if defined(RCC_HSI48_SUPPORT)
-#define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */
-#else
-#define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */
-#endif /* RCC_HSI48_SUPPORT */
-
-/** @defgroup RCC_Reset_Flag Reset Flag
- * @{
- */
-#define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */
-#define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */
-#define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */
-#define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */
-#define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
-#define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
-#define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */
-#define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \
- RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \
- RCC_RESET_FLAG_LPWR)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCC_Private_Macros
- * @{
- */
-
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
- (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U))
-
-#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
- ((__HSE__) == RCC_HSE_BYPASS))
-
-#if defined(RCC_BDCR_LSESYSDIS)
-#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \
- ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || ((__LSE__) == RCC_LSE_BYPASS))
-#else
-#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
- ((__LSE__) == RCC_LSE_BYPASS))
-#endif /* RCC_BDCR_LSESYSDIS */
-
-#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
-
-#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))
-
-#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
-
-#if defined(RCC_CSR_LSIPREDIV)
-#define IS_RCC_LSIDIV(__LSIDIV__) (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128))
-#endif /* RCC_CSR_LSIPREDIV */
-
-#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
-
-#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U)
-
-#if defined(RCC_HSI48_SUPPORT)
-#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
-#endif /* RCC_HSI48_SUPPORT */
-
-#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
- ((__PLL__) == RCC_PLL_ON))
-
-#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
- ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \
- ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
- ((__SOURCE__) == RCC_PLLSOURCE_HSE))
-
-#if defined(RCC_PLLM_DIV_1_16_SUPPORT)
-#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
-#else
-#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
-#endif /*RCC_PLLM_DIV_1_16_SUPPORT */
-
-#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
-
-#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
-#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
-#else
-#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
-#endif /*RCC_PLLP_DIV_2_31_SUPPORT */
-
-#define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
- ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
-
-#define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
- ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
-
-#if defined(RCC_PLLSAI1_SUPPORT)
-#define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \
- (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \
- (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \
- (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U))
-#endif /* RCC_PLLSAI1_SUPPORT */
-
-#if defined(RCC_PLLSAI2_SUPPORT)
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
-#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \
- (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \
- (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U))
-#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \
- (((__VALUE__) & RCC_PLLSAI2_DSICLK) == RCC_PLLSAI2_DSICLK) || \
- (((__VALUE__) & RCC_PLLSAI2_LTDCCLK) == RCC_PLLSAI2_LTDCCLK)) && \
- (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_DSICLK|RCC_PLLSAI2_LTDCCLK)) == 0U))
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
-#endif /* RCC_PLLSAI2_SUPPORT */
-
-#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \
- ((__RANGE__) == RCC_MSIRANGE_1) || \
- ((__RANGE__) == RCC_MSIRANGE_2) || \
- ((__RANGE__) == RCC_MSIRANGE_3) || \
- ((__RANGE__) == RCC_MSIRANGE_4) || \
- ((__RANGE__) == RCC_MSIRANGE_5) || \
- ((__RANGE__) == RCC_MSIRANGE_6) || \
- ((__RANGE__) == RCC_MSIRANGE_7) || \
- ((__RANGE__) == RCC_MSIRANGE_8) || \
- ((__RANGE__) == RCC_MSIRANGE_9) || \
- ((__RANGE__) == RCC_MSIRANGE_10) || \
- ((__RANGE__) == RCC_MSIRANGE_11))
-
-#define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \
- ((__RANGE__) == RCC_MSIRANGE_5) || \
- ((__RANGE__) == RCC_MSIRANGE_6) || \
- ((__RANGE__) == RCC_MSIRANGE_7))
-
-#define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U))
-
-#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
-
-#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
- ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
- ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
- ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
- ((__HCLK__) == RCC_SYSCLK_DIV512))
-
-#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
- ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
- ((__PCLK__) == RCC_HCLK_DIV16))
-
-#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
-
-#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
-
-#if defined(RCC_HSI48_SUPPORT)
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
-#else
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
-#endif /* RCC_HSI48_SUPPORT */
-
-#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
- ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
- ((__DIV__) == RCC_MCODIV_16))
-
-#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
- ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
- ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
- ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
-
-#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \
- ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
-/**
- * @}
- */
-
-/* Include RCC HAL Extended module */
-#include "stm32l4xx_hal_rcc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCC_Exported_Functions
- * @{
- */
-
-
-/** @addtogroup RCC_Exported_Functions_Group1
- * @{
- */
-
-/* Initialization and de-initialization functions ******************************/
-HAL_StatusTypeDef HAL_RCC_DeInit(void);
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_Exported_Functions_Group2
- * @{
- */
-
-/* Peripheral Control functions ************************************************/
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
-void HAL_RCC_EnableCSS(void);
-uint32_t HAL_RCC_GetSysClockFreq(void);
-uint32_t HAL_RCC_GetHCLKFreq(void);
-uint32_t HAL_RCC_GetPCLK1Freq(void);
-uint32_t HAL_RCC_GetPCLK2Freq(void);
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
-/* CSS NMI IRQ handler */
-void HAL_RCC_NMI_IRQHandler(void);
-/* User Callbacks in non blocking mode (IT mode) */
-void HAL_RCC_CSSCallback(void);
-
-uint32_t HAL_RCC_GetResetSource(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L4xx_HAL_RCC_H */
-
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h
deleted file mode 100644
index e0db863..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h
+++ /dev/null
@@ -1,3045 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_rcc_ex.h
- * @author MCD Application Team
- * @brief Header file of RCC HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file in
- * the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L4xx_HAL_RCC_EX_H
-#define STM32L4xx_HAL_RCC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RCCEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
- * @{
- */
-
-#if defined(RCC_PLLSAI1_SUPPORT)
-/**
- * @brief PLLSAI1 Clock structure definition
- */
-typedef struct
-{
-
- uint32_t PLLSAI1Source; /*!< PLLSAI1Source: PLLSAI1 entry clock source.
- This parameter must be a value of @ref RCC_PLL_Clock_Source */
-
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
- uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock.
- This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
-#else
- uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock.
- This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
-#endif
-
- uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock.
- This parameter must be a number between 8 and 86 or 127 depending on devices. */
-
- uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock.
- This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
-
- uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock.
- This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
-
- uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock.
- This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
-
- uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled.
- This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */
-}RCC_PLLSAI1InitTypeDef;
-#endif /* RCC_PLLSAI1_SUPPORT */
-
-#if defined(RCC_PLLSAI2_SUPPORT)
-/**
- * @brief PLLSAI2 Clock structure definition
- */
-typedef struct
-{
-
- uint32_t PLLSAI2Source; /*!< PLLSAI2Source: PLLSAI2 entry clock source.
- This parameter must be a value of @ref RCC_PLL_Clock_Source */
-
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
- uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock.
- This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
-#else
- uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock.
- This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
-#endif
-
- uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock.
- This parameter must be a number between 8 and 86 or 127 depending on devices. */
-
- uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock.
- This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
-
-#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
- uint32_t PLLSAI2Q; /*!< PLLSAI2Q: specifies the division factor for DSI clock.
- This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
-#endif
-
- uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock.
- This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
-
- uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled.
- This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */
-}RCC_PLLSAI2InitTypeDef;
-
-#endif /* RCC_PLLSAI2_SUPPORT */
-
-/**
- * @brief RCC extended clocks structure definition
- */
-typedef struct
-{
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
- This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-#if defined(RCC_PLLSAI1_SUPPORT)
-
- RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters.
- This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */
-#endif /* RCC_PLLSAI1_SUPPORT */
-#if defined(RCC_PLLSAI2_SUPPORT)
-
- RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters.
- This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */
-
-#endif /* RCC_PLLSAI2_SUPPORT */
-
- uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source.
- This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
-
- uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source.
- This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
-
-#if defined(USART3)
-
- uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source.
- This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
-
-#endif /* USART3 */
-
-#if defined(UART4)
-
- uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source.
- This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
-
-#endif /* UART4 */
-
-#if defined(UART5)
-
- uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source.
- This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
-
-#endif /* UART5 */
-
- uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source.
- This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
-
- uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source.
- This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
-
-#if defined(I2C2)
-
- uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source.
- This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
-
-#endif /* I2C2 */
-
- uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source.
- This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
-
-#if defined(I2C4)
-
- uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source.
- This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
-
-#endif /* I2C4 */
-
- uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source.
- This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
-
- uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source.
- This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */
-#if defined(SAI1)
-
- uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source.
- This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
-#endif /* SAI1 */
-
-#if defined(SAI2)
-
- uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source.
- This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
-
-#endif /* SAI2 */
-
-#if defined(USB_OTG_FS) || defined(USB)
-
- uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG).
- This parameter can be a value of @ref RCCEx_USB_Clock_Source */
-
-#endif /* USB_OTG_FS || USB */
-
-#if defined(SDMMC1)
-
- uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG).
- This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
-
-#endif /* SDMMC1 */
-
- uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1).
- This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
-
-#if !defined(STM32L412xx) && !defined(STM32L422xx)
- uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source.
- This parameter can be a value of @ref RCCEx_ADC_Clock_Source */
-#endif /* !STM32L412xx && !STM32L422xx */
-
-#if defined(SWPMI1)
-
- uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 clock source.
- This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */
-
-#endif /* SWPMI1 */
-
-#if defined(DFSDM1_Filter0)
-
- uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 clock source.
- This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */
-
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
- uint32_t Dfsdm1AudioClockSelection; /*!< Specifies DFSDM1 audio clock source.
- This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */
-
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-#endif /* DFSDM1_Filter0 */
-
-#if defined(LTDC)
-
- uint32_t LtdcClockSelection; /*!< Specifies LTDC clock source.
- This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */
-
-#endif /* LTDC */
-
-#if defined(DSI)
-
- uint32_t DsiClockSelection; /*!< Specifies DSI clock source.
- This parameter can be a value of @ref RCCEx_DSI_Clock_Source */
-
-#endif /* DSI */
-
-#if defined(OCTOSPI1) || defined(OCTOSPI2)
-
- uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source.
- This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */
-
-#endif
-
- uint32_t RTCClockSelection; /*!< Specifies RTC clock source.
- This parameter can be a value of @ref RCC_RTC_Clock_Source */
-}RCC_PeriphCLKInitTypeDef;
-
-#if defined(CRS)
-
-/**
- * @brief RCC_CRS Init structure definition
- */
-typedef struct
-{
- uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
- This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
-
- uint32_t Source; /*!< Specifies the SYNC signal source.
- This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
-
- uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
- This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
-
- uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
- It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
- This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
-
- uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
- This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
-
- uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
- This parameter must be a number between 0 and 0x7F for STM32L412xx/L422xx, between 0 and 0x3F otherwise,
- or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
-
-}RCC_CRSInitTypeDef;
-
-/**
- * @brief RCC_CRS Synchronization structure definition
- */
-typedef struct
-{
- uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
- This parameter must be a number between 0 and 0xFFFF */
-
- uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
- This parameter must be a number between 0 and 0x7F for STM32L412xx/L422xx, between 0 and 0x3F otherwise */
-
- uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
- value latched in the time of the last SYNC event.
- This parameter must be a number between 0 and 0xFFFF */
-
- uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
- frequency error counter latched in the time of the last SYNC event.
- It shows whether the actual frequency is below or above the target.
- This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
-
-}RCC_CRSSynchroInfoTypeDef;
-
-#endif /* CRS */
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
- * @{
- */
-
-/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
- * @{
- */
-#define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */
-#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
- * @{
- */
-#define RCC_PERIPHCLK_USART1 0x00000001U
-#define RCC_PERIPHCLK_USART2 0x00000002U
-#if defined(USART3)
-#define RCC_PERIPHCLK_USART3 0x00000004U
-#endif
-#if defined(UART4)
-#define RCC_PERIPHCLK_UART4 0x00000008U
-#endif
-#if defined(UART5)
-#define RCC_PERIPHCLK_UART5 0x00000010U
-#endif
-#define RCC_PERIPHCLK_LPUART1 0x00000020U
-#define RCC_PERIPHCLK_I2C1 0x00000040U
-#if defined(I2C2)
-#define RCC_PERIPHCLK_I2C2 0x00000080U
-#endif
-#define RCC_PERIPHCLK_I2C3 0x00000100U
-#define RCC_PERIPHCLK_LPTIM1 0x00000200U
-#define RCC_PERIPHCLK_LPTIM2 0x00000400U
-#if defined(SAI1)
-#define RCC_PERIPHCLK_SAI1 0x00000800U
-#endif
-#if defined(SAI2)
-#define RCC_PERIPHCLK_SAI2 0x00001000U
-#endif
-#if defined(USB_OTG_FS) || defined(USB)
-#define RCC_PERIPHCLK_USB 0x00002000U
-#endif
-#define RCC_PERIPHCLK_ADC 0x00004000U
-#if defined(SWPMI1)
-#define RCC_PERIPHCLK_SWPMI1 0x00008000U
-#endif
-#if defined(DFSDM1_Filter0)
-#define RCC_PERIPHCLK_DFSDM1 0x00010000U
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define RCC_PERIPHCLK_DFSDM1AUDIO 0x00200000U
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-#endif
-#define RCC_PERIPHCLK_RTC 0x00020000U
-#define RCC_PERIPHCLK_RNG 0x00040000U
-#if defined(SDMMC1)
-#define RCC_PERIPHCLK_SDMMC1 0x00080000U
-#endif
-#if defined(I2C4)
-#define RCC_PERIPHCLK_I2C4 0x00100000U
-#endif
-#if defined(LTDC)
-#define RCC_PERIPHCLK_LTDC 0x00400000U
-#endif
-#if defined(DSI)
-#define RCC_PERIPHCLK_DSI 0x00800000U
-#endif
-#if defined(OCTOSPI1) || defined(OCTOSPI2)
-#define RCC_PERIPHCLK_OSPI 0x01000000U
-#endif
-/**
- * @}
- */
-
-
-/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
- * @{
- */
-#define RCC_USART1CLKSOURCE_PCLK2 0x00000000U
-#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
-#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
-#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
-/**
- * @}
- */
-
-/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
- * @{
- */
-#define RCC_USART2CLKSOURCE_PCLK1 0x00000000U
-#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
-#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
-#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
-/**
- * @}
- */
-
-#if defined(USART3)
-/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
- * @{
- */
-#define RCC_USART3CLKSOURCE_PCLK1 0x00000000U
-#define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
-#define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
-#define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
-/**
- * @}
- */
-#endif /* USART3 */
-
-#if defined(UART4)
-/** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
- * @{
- */
-#define RCC_UART4CLKSOURCE_PCLK1 0x00000000U
-#define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
-#define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
-#define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
-/**
- * @}
- */
-#endif /* UART4 */
-
-#if defined(UART5)
-/** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
- * @{
- */
-#define RCC_UART5CLKSOURCE_PCLK1 0x00000000U
-#define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0
-#define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1
-#define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
-/**
- * @}
- */
-#endif /* UART5 */
-
-/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
- * @{
- */
-#define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U
-#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
-#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
-#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
- * @{
- */
-#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U
-#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
-#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
-/**
- * @}
- */
-
-#if defined(I2C2)
-/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
- * @{
- */
-#define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U
-#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
-#define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1
-/**
- * @}
- */
-#endif /* I2C2 */
-
-/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
- * @{
- */
-#define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U
-#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
-#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
-/**
- * @}
- */
-
-#if defined(I2C4)
-/** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source
- * @{
- */
-#define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U
-#define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0
-#define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1
-/**
- * @}
- */
-#endif /* I2C4 */
-
-#if defined(SAI1)
-/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
- * @{
- */
-#define RCC_SAI1CLKSOURCE_PLLSAI1 0x00000000U
-#if defined(RCC_PLLSAI2_SUPPORT)
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI1SEL_0
-#else
-#define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-#endif /* RCC_PLLSAI2_SUPPORT */
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR2_SAI1SEL_1
-#define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)
-#define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2
-#else
-#define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1
-#define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-/**
- * @}
- */
-#endif /* SAI1 */
-
-#if defined(SAI2)
-/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
- * @{
- */
-#define RCC_SAI2CLKSOURCE_PLLSAI1 0x00000000U
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI2SEL_0
-#define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1
-#define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0)
-#define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2
-#else
-#define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0
-#define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1
-#define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-/**
- * @}
- */
-#endif /* SAI2 */
-
-/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
- * @{
- */
-#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
-#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
-#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
-#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
-/**
- * @}
- */
-
-/** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source
- * @{
- */
-#define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U
-#define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0
-#define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1
-#define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL
-/**
- * @}
- */
-
-#if defined(SDMMC1)
-/** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source
- * @{
- */
-#if defined(RCC_HSI48_SUPPORT)
-#define RCC_SDMMC1CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock selected as SDMMC1 clock */
-#else
-#define RCC_SDMMC1CLKSOURCE_NONE 0x00000000U /*!< No clock selected as SDMMC1 clock */
-#endif /* RCC_HSI48_SUPPORT */
-#define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 "Q" clock selected as SDMMC1 clock */
-#define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL "Q" clock selected as SDMMC1 clock */
-#define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock selected as SDMMC1 clock */
-#if defined(RCC_CCIPR2_SDMMCSEL)
-#define RCC_SDMMC1CLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLL "P" clock selected as SDMMC1 kernel clock */
-#endif /* RCC_CCIPR2_SDMMCSEL */
-/**
- * @}
- */
-#endif /* SDMMC1 */
-
-/** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
- * @{
- */
-#if defined(RCC_HSI48_SUPPORT)
-#define RCC_RNGCLKSOURCE_HSI48 0x00000000U
-#else
-#define RCC_RNGCLKSOURCE_NONE 0x00000000U
-#endif /* RCC_HSI48_SUPPORT */
-#if defined(RCC_PLLSAI1_SUPPORT)
-#define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
-#endif /* RCC_PLLSAI1_SUPPORT */
-#define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
-#define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
-/**
- * @}
- */
-
-#if defined(USB_OTG_FS) || defined(USB)
-/** @defgroup RCCEx_USB_Clock_Source USB Clock Source
- * @{
- */
-#if defined(RCC_HSI48_SUPPORT)
-#define RCC_USBCLKSOURCE_HSI48 0x00000000U
-#else
-#define RCC_USBCLKSOURCE_NONE 0x00000000U
-#endif /* RCC_HSI48_SUPPORT */
-#if defined(RCC_PLLSAI1_SUPPORT)
-#define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
-#endif /* RCC_PLLSAI1_SUPPORT */
-#define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
-#define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
-/**
- * @}
- */
-#endif /* USB_OTG_FS || USB */
-
-/** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
- * @{
- */
-#define RCC_ADCCLKSOURCE_NONE 0x00000000U
-#if defined(RCC_PLLSAI1_SUPPORT)
-#define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0
-#endif /* RCC_PLLSAI1_SUPPORT */
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
-#define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
-#if defined(RCC_CCIPR_ADCSEL)
-#define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL
-#else
-#define RCC_ADCCLKSOURCE_SYSCLK 0x30000000U
-#endif /* RCC_CCIPR_ADCSEL */
-/**
- * @}
- */
-
-#if defined(SWPMI1)
-/** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source
- * @{
- */
-#define RCC_SWPMI1CLKSOURCE_PCLK1 0x00000000U
-#define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL
-/**
- * @}
- */
-#endif /* SWPMI1 */
-
-#if defined(DFSDM1_Filter0)
-/** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source
- * @{
- */
-#define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL
-#else
-#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-/**
- * @}
- */
-
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source DFSDM1 Audio Clock Source
- * @{
- */
-#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 0x00000000U
-#define RCC_DFSDM1AUDIOCLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0
-#define RCC_DFSDM1AUDIOCLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1
-/**
- * @}
- */
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-#endif /* DFSDM1_Filter0 */
-
-#if defined(LTDC)
-/** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source
- * @{
- */
-#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 0x00000000U
-#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0
-#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1
-#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 RCC_CCIPR2_PLLSAI2DIVR
-/**
- * @}
- */
-#endif /* LTDC */
-
-#if defined(DSI)
-/** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source
- * @{
- */
-#define RCC_DSICLKSOURCE_DSIPHY 0x00000000U
-#define RCC_DSICLKSOURCE_PLLSAI2 RCC_CCIPR2_DSISEL
-/**
- * @}
- */
-#endif /* DSI */
-
-#if defined(OCTOSPI1) || defined(OCTOSPI2)
-/** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source
- * @{
- */
-#define RCC_OSPICLKSOURCE_SYSCLK 0x00000000U
-#define RCC_OSPICLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0
-#define RCC_OSPICLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1
-/**
- * @}
- */
-#endif /* OCTOSPI1 || OCTOSPI2 */
-
-/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
- * @{
- */
-#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
-/**
- * @}
- */
-
-#if defined(CRS)
-
-/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
- * @{
- */
-#define RCC_CRS_NONE 0x00000000U
-#define RCC_CRS_TIMEOUT 0x00000001U
-#define RCC_CRS_SYNCOK 0x00000002U
-#define RCC_CRS_SYNCWARN 0x00000004U
-#define RCC_CRS_SYNCERR 0x00000008U
-#define RCC_CRS_SYNCMISS 0x00000010U
-#define RCC_CRS_TRIMOVF 0x00000020U
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
- * @{
- */
-#define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */
-#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
-#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
- * @{
- */
-#define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */
-#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
-#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
-#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
-#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
-#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
-#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
-#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
- * @{
- */
-#define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */
-#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
- * @{
- */
-#define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds
- to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
- * @{
- */
-#define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
- * @{
- */
-#if defined(STM32L412xx) || defined(STM32L422xx)
-#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval.
- The trimming step is specified in the product datasheet. A higher TRIM value
- corresponds to a higher output frequency */
-#else
-#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval.
- The trimming step is specified in the product datasheet. A higher TRIM value
- corresponds to a higher output frequency */
-#endif
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
- * @{
- */
-#define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */
-#define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
- * @{
- */
-#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */
-#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */
-#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */
-#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */
-#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */
-#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */
-#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
- * @{
- */
-#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */
-#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */
-#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */
-#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */
-#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
-#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
-#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
-
-/**
- * @}
- */
-
-#endif /* CRS */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
- * @{
- */
-
-#if defined(RCC_PLLSAI1_SUPPORT)
-
-/**
- * @brief Macro to configure the PLLSAI1 clock multiplication and division factors.
- *
- * @note This function must be used only when the PLLSAI1 is disabled.
- * @note PLLSAI1 clock source is common with the main PLL (configured through
- * __HAL_RCC_PLL_CONFIG() macro)
- *
- @if STM32L4S9xx
- * @param __PLLSAI1M__ specifies the division factor of PLLSAI1 input clock.
- * This parameter must be a number between Min_Data = 1 and Max_Data = 16.
- *
- @endif
- * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
- * This parameter must be a number between 8 and 86 or 127 depending on devices.
- * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO
- * output frequency is between 64 and 344 MHz.
- * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
- *
- * @param __PLLSAI1P__ specifies the division factor for SAI clock.
- * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
- * else (2 to 31).
- * SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
- *
- * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
- * This parameter must be in the range (2, 4, 6 or 8).
- * USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
- *
- * @param __PLLSAI1R__ specifies the division factor for SAR ADC clock.
- * This parameter must be in the range (2, 4, 6 or 8).
- * ADC clock frequency = f(PLLSAI1) / PLLSAI1R
- *
- * @retval None
- */
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
-
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
-
-#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, \
- (RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \
- RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1PDIV), \
- ((((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \
- ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \
- ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \
- ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \
- ((uint32_t)(__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)))
-
-#else
-
-#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, \
- (RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \
- RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R), \
- ((((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \
- ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \
- ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \
- ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \
- (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)))
-
-#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
-
-#else
-
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
-
-#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, \
- (RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \
- RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1PDIV), \
- (((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \
- ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \
- ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \
- ((uint32_t)(__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)))
-
-#else
-
-#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, \
- (RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \
- RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R), \
- (((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \
- ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \
- ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \
- (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)))
-
-#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
-
-#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
-
-/**
- * @brief Macro to configure the PLLSAI1 clock multiplication factor N.
- *
- * @note This function must be used only when the PLLSAI1 is disabled.
- * @note PLLSAI1 clock source is common with the main PLL (configured through
- * __HAL_RCC_PLL_CONFIG() macro)
- *
- * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
- * This parameter must be a number between 8 and 86 or 127 depending on devices.
- * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO
- * output frequency is between 64 and 344 MHz.
- * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
- *
- * @retval None
- */
-#define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
-
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
-
-/** @brief Macro to configure the PLLSAI1 input clock division factor M.
- *
- * @note This function must be used only when the PLLSAI1 is disabled.
- * @note PLLSAI1 clock source is common with the main PLL (configured through
- * __HAL_RCC_PLL_CONFIG() macro)
- *
- * @param __PLLSAI1M__ specifies the division factor for PLLSAI1 clock.
- * This parameter must be a number between Min_Data = 1 and Max_Data = 16.
- *
- * @retval None
- */
-
-#define __HAL_RCC_PLLSAI1_DIVM_CONFIG(__PLLSAI1M__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)
-
-#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
-
-/** @brief Macro to configure the PLLSAI1 clock division factor P.
- *
- * @note This function must be used only when the PLLSAI1 is disabled.
- * @note PLLSAI1 clock source is common with the main PLL (configured through
- * __HAL_RCC_PLL_CONFIG() macro)
- *
- * @param __PLLSAI1P__ specifies the division factor for SAI clock.
- * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
- * else (2 to 31).
- * Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
- *
- * @retval None
- */
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
-
-#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
-
-#else
-
-#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)
-
-#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
-
-/** @brief Macro to configure the PLLSAI1 clock division factor Q.
- *
- * @note This function must be used only when the PLLSAI1 is disabled.
- * @note PLLSAI1 clock source is common with the main PLL (configured through
- * __HAL_RCC_PLL_CONFIG() macro)
- *
- * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
- * This parameter must be in the range (2, 4, 6 or 8).
- * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
- *
- * @retval None
- */
-#define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
-
-/** @brief Macro to configure the PLLSAI1 clock division factor R.
- *
- * @note This function must be used only when the PLLSAI1 is disabled.
- * @note PLLSAI1 clock source is common with the main PLL (configured through
- * __HAL_RCC_PLL_CONFIG() macro)
- *
- * @param __PLLSAI1R__ specifies the division factor for ADC clock.
- * This parameter must be in the range (2, 4, 6 or 8)
- * Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R
- *
- * @retval None
- */
-#define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
-
-/**
- * @brief Macros to enable or disable the PLLSAI1.
- * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.
- * @retval None
- */
-
-#define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
-
-#define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
-
-/**
- * @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
- * @note Enabling and disabling those clocks can be done without the need to stop the PLL.
- * This is mainly used to save Power.
- * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
- * This parameter can be one or a combination of the following values:
- * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve
- * high-quality audio performance on SAI interface in case.
- * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz),
- * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
- * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.
- * @retval None
- */
-
-#define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
-
-#define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
-
-/**
- * @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
- * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
- * This parameter can be one of the following values:
- * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve
- * high-quality audio performance on SAI interface in case.
- * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz),
- * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
- * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.
- * @retval SET / RESET
- */
-#define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
-
-#endif /* RCC_PLLSAI1_SUPPORT */
-
-#if defined(RCC_PLLSAI2_SUPPORT)
-
-/**
- * @brief Macro to configure the PLLSAI2 clock multiplication and division factors.
- *
- * @note This function must be used only when the PLLSAI2 is disabled.
- * @note PLLSAI2 clock source is common with the main PLL (configured through
- * __HAL_RCC_PLL_CONFIG() macro)
- *
- @if STM32L4S9xx
- * @param __PLLSAI2M__ specifies the division factor of PLLSAI2 input clock.
- * This parameter must be a number between Min_Data = 1 and Max_Data = 16.
- *
- @endif
- * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
- * This parameter must be a number between 8 and 86.
- * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO
- * output frequency is between 64 and 344 MHz.
- *
- * @param __PLLSAI2P__ specifies the division factor for SAI clock.
- * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
- * else (2 to 31).
- * SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P
- *
- @if STM32L4S9xx
- * @param __PLLSAI2Q__ specifies the division factor for DSI clock.
- * This parameter must be in the range (2, 4, 6 or 8).
- * DSI clock frequency = f(PLLSAI2) / PLLSAI2Q
- *
- @endif
- * @param __PLLSAI2R__ specifies the division factor for SAR ADC clock.
- * This parameter must be in the range (2, 4, 6 or 8).
- *
- * @retval None
- */
-
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
-
-# if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT)
-
-#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \
- MODIFY_REG(RCC->PLLSAI2CFGR, \
- (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \
- RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \
- ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \
- ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
- ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \
- ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \
- ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)))
-
-# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
-
-#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
- MODIFY_REG(RCC->PLLSAI2CFGR, \
- (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \
- RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \
- ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \
- ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
- ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \
- ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)))
-
-# else
-
-#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
- MODIFY_REG(RCC->PLLSAI2CFGR, \
- (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \
- RCC_PLLSAI2CFGR_PLLSAI2R), \
- ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \
- ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
- ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \
- (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)))
-
-# endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */
-
-#else
-
-# if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT)
-
-#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \
- MODIFY_REG(RCC->PLLSAI2CFGR, \
- (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \
- RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \
- (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
- ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \
- ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \
- ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)))
-
-# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
-
-#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
- MODIFY_REG(RCC->PLLSAI2CFGR, \
- (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \
- RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \
- (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
- ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \
- ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)))
-
-# else
-
-#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
- MODIFY_REG(RCC->PLLSAI2CFGR, \
- (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \
- RCC_PLLSAI2CFGR_PLLSAI2R), \
- (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
- ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \
- (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)))
-
-# endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */
-
-#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
-
-
-/**
- * @brief Macro to configure the PLLSAI2 clock multiplication factor N.
- *
- * @note This function must be used only when the PLLSAI2 is disabled.
- * @note PLLSAI2 clock source is common with the main PLL (configured through
- * __HAL_RCC_PLL_CONFIG() macro)
- *
- * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
- * This parameter must be a number between 8 and 86.
- * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO
- * output frequency is between 64 and 344 MHz.
- * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N
- *
- * @retval None
- */
-#define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \
- MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
-
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
-
-/** @brief Macro to configure the PLLSAI2 input clock division factor M.
- *
- * @note This function must be used only when the PLLSAI2 is disabled.
- * @note PLLSAI2 clock source is common with the main PLL (configured through
- * __HAL_RCC_PLL_CONFIG() macro)
- *
- * @param __PLLSAI2M__ specifies the division factor for PLLSAI2 clock.
- * This parameter must be a number between Min_Data = 1 and Max_Data = 16.
- *
- * @retval None
- */
-
-#define __HAL_RCC_PLLSAI2_DIVM_CONFIG(__PLLSAI2M__) \
- MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M, ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)
-
-#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
-
-/** @brief Macro to configure the PLLSAI2 clock division factor P.
- *
- * @note This function must be used only when the PLLSAI2 is disabled.
- * @note PLLSAI2 clock source is common with the main PLL (configured through
- * __HAL_RCC_PLL_CONFIG() macro)
- *
- * @param __PLLSAI2P__ specifies the division factor.
- * This parameter must be a number in the range (7 or 17).
- * Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__
- *
- * @retval None
- */
-#define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \
- MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)
-
-#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
-
-/** @brief Macro to configure the PLLSAI2 clock division factor Q.
- *
- * @note This function must be used only when the PLLSAI2 is disabled.
- * @note PLLSAI2 clock source is common with the main PLL (configured through
- * __HAL_RCC_PLL_CONFIG() macro)
- *
- * @param __PLLSAI2Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
- * This parameter must be in the range (2, 4, 6 or 8).
- * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI2) / PLLSAI2Q
- *
- * @retval None
- */
-#define __HAL_RCC_PLLSAI2_DIVQ_CONFIG(__PLLSAI2Q__) \
- MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q, (((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos)
-
-#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
-
-/** @brief Macro to configure the PLLSAI2 clock division factor R.
- *
- * @note This function must be used only when the PLLSAI2 is disabled.
- * @note PLLSAI2 clock source is common with the main PLL (configured through
- * __HAL_RCC_PLL_CONFIG() macro)
- *
- * @param __PLLSAI2R__ specifies the division factor.
- * This parameter must be in the range (2, 4, 6 or 8).
- * Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__
- *
- * @retval None
- */
-#define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \
- MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
-
-/**
- * @brief Macros to enable or disable the PLLSAI2.
- * @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes.
- * @retval None
- */
-
-#define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
-
-#define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
-
-/**
- * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK).
- * @note Enabling and disabling those clocks can be done without the need to stop the PLL.
- * This is mainly used to save Power.
- * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
- * This parameter can be one or a combination of the following values:
- @if STM32L486xx
- * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
- * high-quality audio performance on SAI interface in case.
- * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
- @endif
- @if STM32L4A6xx
- * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
- * high-quality audio performance on SAI interface in case.
- * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
- @endif
- @if STM32L4S9xx
- * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
- * high-quality audio performance on SAI interface in case.
- * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral.
- @endif
- * @retval None
- */
-
-#define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
-
-#define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
-
-/**
- * @brief Macro to get clock output enable status (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK).
- * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
- * This parameter can be one of the following values:
- @if STM32L486xx
- * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
- * high-quality audio performance on SAI interface in case.
- * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
- @endif
- @if STM32L4A6xx
- * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
- * high-quality audio performance on SAI interface in case.
- * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
- @endif
- @if STM32L4S9xx
- * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
- * high-quality audio performance on SAI interface in case.
- * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral.
- @endif
- * @retval SET / RESET
- */
-#define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
-
-#endif /* RCC_PLLSAI2_SUPPORT */
-
-#if defined(SAI1)
-
-/**
- * @brief Macro to configure the SAI1 clock source.
- * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived
- * from the PLLSAI1, system PLL or external clock (through a dedicated pin).
- * This parameter can be one of the following values:
- * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
- @if STM32L486xx
- * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
- @endif
- * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
- * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
- @if STM32L4S9xx
- * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16
- @endif
- *
- @if STM32L443xx
- * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2.
- @endif
- *
- * @retval None
- */
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
- MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (__SAI1_CLKSOURCE__))
-#else
-#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-/** @brief Macro to get the SAI1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
- @if STM32L486xx
- * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
- @endif
- * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
- * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
- *
- * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1
- * clock source when PLLs are disabled for devices without PLLSAI2.
- *
- */
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL))
-#else
-#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-#endif /* SAI1 */
-
-#if defined(SAI2)
-
-/**
- * @brief Macro to configure the SAI2 clock source.
- * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived
- * from the PLLSAI2, system PLL or external clock (through a dedicated pin).
- * This parameter can be one of the following values:
- * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
- * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
- * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
- * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
- @if STM32L4S9xx
- * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16
- @endif
- *
- * @retval None
- */
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
- MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (__SAI2_CLKSOURCE__))
-#else
-#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (__SAI2_CLKSOURCE__))
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-/** @brief Macro to get the SAI2 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
- * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
- * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
- * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
- */
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL))
-#else
-#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL))
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-#endif /* SAI2 */
-
-/** @brief Macro to configure the I2C1 clock (I2C1CLK).
- *
- * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
- * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
- * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
- * @retval None
- */
-#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__))
-
-/** @brief Macro to get the I2C1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
- * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
- * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
- */
-#define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))
-
-#if defined(I2C2)
-
-/** @brief Macro to configure the I2C2 clock (I2C2CLK).
- *
- * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
- * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
- * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
- * @retval None
- */
-#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__))
-
-/** @brief Macro to get the I2C2 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
- * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
- * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
- */
-#define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))
-
-#endif /* I2C2 */
-
-/** @brief Macro to configure the I2C3 clock (I2C3CLK).
- *
- * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
- * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
- * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
- * @retval None
- */
-#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__))
-
-/** @brief Macro to get the I2C3 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
- * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
- * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
- */
-#define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))
-
-#if defined(I2C4)
-
-/** @brief Macro to configure the I2C4 clock (I2C4CLK).
- *
- * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
- * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
- * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock
- * @retval None
- */
-#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__))
-
-/** @brief Macro to get the I2C4 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
- * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
- * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock
- */
-#define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL))
-
-#endif /* I2C4 */
-
-
-/** @brief Macro to configure the USART1 clock (USART1CLK).
- *
- * @param __USART1_CLKSOURCE__ specifies the USART1 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
- * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
- * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
- * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock
- * @retval None
- */
-#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__))
-
-/** @brief Macro to get the USART1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
- * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
- * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
- * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
- */
-#define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))
-
-/** @brief Macro to configure the USART2 clock (USART2CLK).
- *
- * @param __USART2_CLKSOURCE__ specifies the USART2 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
- * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
- * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
- * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
- * @retval None
- */
-#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__))
-
-/** @brief Macro to get the USART2 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
- * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
- * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
- * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
- */
-#define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))
-
-#if defined(USART3)
-
-/** @brief Macro to configure the USART3 clock (USART3CLK).
- *
- * @param __USART3_CLKSOURCE__ specifies the USART3 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
- * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
- * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
- * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
- * @retval None
- */
-#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__))
-
-/** @brief Macro to get the USART3 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
- * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
- * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
- * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
- */
-#define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))
-
-#endif /* USART3 */
-
-#if defined(UART4)
-
-/** @brief Macro to configure the UART4 clock (UART4CLK).
- *
- * @param __UART4_CLKSOURCE__ specifies the UART4 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
- * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
- * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
- * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
- * @retval None
- */
-#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__))
-
-/** @brief Macro to get the UART4 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
- * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
- * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
- * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
- */
-#define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))
-
-#endif /* UART4 */
-
-#if defined(UART5)
-
-/** @brief Macro to configure the UART5 clock (UART5CLK).
- *
- * @param __UART5_CLKSOURCE__ specifies the UART5 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
- * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
- * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
- * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
- * @retval None
- */
-#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__))
-
-/** @brief Macro to get the UART5 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
- * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
- * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
- * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
- */
-#define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))
-
-#endif /* UART5 */
-
-/** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
- *
- * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
- * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
- * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
- * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
- * @retval None
- */
-#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__))
-
-/** @brief Macro to get the LPUART1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
- * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
- * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
- * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
- */
-#define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))
-
-/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
- *
- * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock
- * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
- * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
- * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
- * @retval None
- */
-#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__))
-
-/** @brief Macro to get the LPTIM1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
- * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock
- * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock
- * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock
- */
-#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))
-
-/** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK).
- *
- * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock
- * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock
- * @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock
- * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock
- * @retval None
- */
-#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (__LPTIM2_CLKSOURCE__))
-
-/** @brief Macro to get the LPTIM2 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
- * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPUART1 clock
- * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock
- * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock
- */
-#define __HAL_RCC_GET_LPTIM2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL))
-
-#if defined(SDMMC1)
-
-/** @brief Macro to configure the SDMMC1 clock.
- *
- @if STM32L486xx
- * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
- @endif
- *
- @if STM32L443xx
- * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
- @endif
- *
- * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source.
- * This parameter can be one of the following values:
- @if STM32L486xx
- * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48
- * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
- * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock
- @endif
- @if STM32L443xx
- * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
- * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
- * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock
- @endif
- @if STM32L4S9xx
- * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
- * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
- * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock
- * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" Clock selected as SDMMC1 clock
- @endif
- * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" Clock selected as SDMMC1 clock
- * @retval None
- */
-#if defined(RCC_CCIPR2_SDMMCSEL)
-#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
- do \
- { \
- if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \
- { \
- SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \
- } \
- else \
- { \
- CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)); \
- } \
- } while(0)
-#else
-#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__))
-#endif /* RCC_CCIPR2_SDMMCSEL */
-
-/** @brief Macro to get the SDMMC1 clock.
- * @retval The clock source can be one of the following values:
- @if STM32L486xx
- * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48
- * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
- * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
- @endif
- @if STM32L443xx
- * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
- * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
- * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
- @endif
- @if STM32L4S9xx
- * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
- * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
- * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
- * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" clock (PLLSAI3CLK) selected as SDMMC1 kernel clock
- @endif
- * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
- */
-#if defined(RCC_CCIPR2_SDMMCSEL)
-#define __HAL_RCC_GET_SDMMC1_SOURCE() \
- ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != 0U) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
-#else
-#define __HAL_RCC_GET_SDMMC1_SOURCE() \
- (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
-#endif /* RCC_CCIPR2_SDMMCSEL */
-
-#endif /* SDMMC1 */
-
-/** @brief Macro to configure the RNG clock.
- *
- * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
- *
- * @param __RNG_CLKSOURCE__ specifies the RNG clock source.
- * This parameter can be one of the following values:
- @if STM32L486xx
- * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48
- @endif
- @if STM32L443xx
- * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
- @endif
- * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
- * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as RNG clock
- * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock
- * @retval None
- */
-#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__))
-
-/** @brief Macro to get the RNG clock.
- * @retval The clock source can be one of the following values:
- @if STM32L486xx
- * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48
- @endif
- @if STM32L443xx
- * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
- @endif
- * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
- * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock
- * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock
- */
-#define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
-
-#if defined(USB_OTG_FS) || defined(USB)
-
-/** @brief Macro to configure the USB clock (USBCLK).
- *
- * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
- *
- * @param __USB_CLKSOURCE__ specifies the USB clock source.
- * This parameter can be one of the following values:
- @if STM32L486xx
- * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48
- @endif
- @if STM32L443xx
- * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
- @endif
- * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock
- * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
- * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
- * @retval None
- */
-#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__))
-
-/** @brief Macro to get the USB clock source.
- * @retval The clock source can be one of the following values:
- @if STM32L486xx
- * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48
- @endif
- @if STM32L443xx
- * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
- @endif
- * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock
- * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
- * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
- */
-#define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
-
-#endif /* USB_OTG_FS || USB */
-
-#if defined(RCC_CCIPR_ADCSEL)
-
-/** @brief Macro to configure the ADC interface clock.
- * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
- * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
- @if STM32L486xx
- * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
- @endif
- * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
- * @retval None
- */
-#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (__ADC_CLKSOURCE__))
-
-/** @brief Macro to get the ADC clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
- * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
- @if STM32L486xx
- * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
- @endif
- * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
- */
-#define __HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))
-#else
-
-/** @brief Macro to get the ADC clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
- * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
- */
-#define __HAL_RCC_GET_ADC_SOURCE() ((__HAL_RCC_ADC_IS_CLK_ENABLED() != 0U) ? RCC_ADCCLKSOURCE_SYSCLK : RCC_ADCCLKSOURCE_NONE)
-
-#endif /* RCC_CCIPR_ADCSEL */
-
-#if defined(SWPMI1)
-
-/** @brief Macro to configure the SWPMI1 clock.
- * @param __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock
- * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock
- * @retval None
- */
-#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (__SWPMI1_CLKSOURCE__))
-
-/** @brief Macro to get the SWPMI1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock
- * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock
- */
-#define __HAL_RCC_GET_SWPMI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL))
-
-#endif /* SWPMI1 */
-
-#if defined(DFSDM1_Filter0)
-/** @brief Macro to configure the DFSDM1 clock.
- * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock
- * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock
- * @retval None
- */
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, (__DFSDM1_CLKSOURCE__))
-#else
-#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (__DFSDM1_CLKSOURCE__))
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-/** @brief Macro to get the DFSDM1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock
- * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock
- */
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL))
-#else
-#define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL))
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-
-/** @brief Macro to configure the DFSDM1 audio clock.
- * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 audio clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock
- * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock
- * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock
- * @retval None
- */
-#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, (__DFSDM1AUDIO_CLKSOURCE__))
-
-/** @brief Macro to get the DFSDM1 audio clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock
- * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock
- * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock
- */
-#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL))
-
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-#endif /* DFSDM1_Filter0 */
-
-#if defined(LTDC)
-
-/** @brief Macro to configure the LTDC clock.
- * @param __LTDC_CLKSOURCE__ specifies the LTDC clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock
- * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock
- * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock
- * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock
- * @retval None
- */
-#define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, (__LTDC_CLKSOURCE__))
-
-/** @brief Macro to get the LTDC clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock
- * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock
- * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock
- * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock
- */
-#define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR))
-
-#endif /* LTDC */
-
-#if defined(DSI )
-
-/** @brief Macro to configure the DSI clock.
- * @param __DSI_CLKSOURCE__ specifies the DSI clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock
- * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock
- * @retval None
- */
-#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, (__DSI_CLKSOURCE__))
-
-/** @brief Macro to get the DSI clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock
- * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock
- */
-#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSISEL))
-
-#endif /* DSI */
-
-#if defined(OCTOSPI1) || defined(OCTOSPI2)
-
-/** @brief Macro to configure the OctoSPI clock.
- * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock
- * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock
- * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock
- * @retval None
- */
-#define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (__OSPI_CLKSOURCE__))
-
-/** @brief Macro to get the OctoSPI clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock
- * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock
- * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock
- */
-#define __HAL_RCC_GET_OSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL))
-
-#endif /* OCTOSPI1 || OCTOSPI2 */
-
-/** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
- * @brief macros to manage the specified RCC Flags and interrupts.
- * @{
- */
-#if defined(RCC_PLLSAI1_SUPPORT)
-
-/** @brief Enable PLLSAI1RDY interrupt.
- * @retval None
- */
-#define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
-
-/** @brief Disable PLLSAI1RDY interrupt.
- * @retval None
- */
-#define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
-
-/** @brief Clear the PLLSAI1RDY interrupt pending bit.
- * @retval None
- */
-#define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)
-
-/** @brief Check whether PLLSAI1RDY interrupt has occurred or not.
- * @retval TRUE or FALSE.
- */
-#define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)
-
-/** @brief Check whether the PLLSAI1RDY flag is set or not.
- * @retval TRUE or FALSE.
- */
-#define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))
-
-#endif /* RCC_PLLSAI1_SUPPORT */
-
-#if defined(RCC_PLLSAI2_SUPPORT)
-
-/** @brief Enable PLLSAI2RDY interrupt.
- * @retval None
- */
-#define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
-
-/** @brief Disable PLLSAI2RDY interrupt.
- * @retval None
- */
-#define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
-
-/** @brief Clear the PLLSAI2RDY interrupt pending bit.
- * @retval None
- */
-#define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)
-
-/** @brief Check whether the PLLSAI2RDY interrupt has occurred or not.
- * @retval TRUE or FALSE.
- */
-#define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)
-
-/** @brief Check whether the PLLSAI2RDY flag is set or not.
- * @retval TRUE or FALSE.
- */
-#define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))
-
-#endif /* RCC_PLLSAI2_SUPPORT */
-
-
-/**
- * @brief Enable the RCC LSE CSS Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
-
-/**
- * @brief Disable the RCC LSE CSS Extended Interrupt Line.
- * @retval None
- */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
-
-/**
- * @brief Enable the RCC LSE CSS Event Line.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
-
-/**
- * @brief Disable the RCC LSE CSS Event Line.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
-
-
-/**
- * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
-
-
-/**
- * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
-
-
-/**
- * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
-
-/**
- * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
-
-/**
- * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0)
-
-/**
- * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
- do { \
- __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0)
-
-/**
- * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
- * @retval EXTI RCC LSE CSS Line Status.
- */
-#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
-
-/**
- * @brief Clear the RCC LSE CSS EXTI flag.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
-
-/**
- * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
- * @retval None.
- */
-#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
-
-
-#if defined(CRS)
-
-/**
- * @brief Enable the specified CRS interrupts.
- * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
- * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
- * @retval None
- */
-#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
-
-/**
- * @brief Disable the specified CRS interrupts.
- * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
- * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
- * @retval None
- */
-#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
-
-/** @brief Check whether the CRS interrupt has occurred or not.
- * @param __INTERRUPT__ specifies the CRS interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
- * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
- * @retval The new state of __INTERRUPT__ (SET or RESET).
- */
-#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
-
-/** @brief Clear the CRS interrupt pending bits
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
- * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
- * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
- * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
- * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
- */
-/* CRS IT Error Mask */
-#define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)
-
-#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
- if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
- { \
- WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
- } \
- else \
- { \
- WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
- } \
- } while(0)
-
-/**
- * @brief Check whether the specified CRS flag is set or not.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
- * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
- * @arg @ref RCC_CRS_FLAG_ERR Error
- * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
- * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
- * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
- * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
- * @retval The new state of _FLAG_ (TRUE or FALSE).
- */
-#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clear the CRS specified FLAG.
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
- * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
- * @arg @ref RCC_CRS_FLAG_ERR Error
- * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
- * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
- * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
- * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
- * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
- * @retval None
- */
-
-/* CRS Flag Error Mask */
-#define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)
-
-#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
- if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
- { \
- WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
- } \
- else \
- { \
- WRITE_REG(CRS->ICR, (__FLAG__)); \
- } \
- } while(0)
-
-#endif /* CRS */
-
-/**
- * @}
- */
-
-#if defined(CRS)
-
-/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
- * @{
- */
-/**
- * @brief Enable the oscillator clock for frequency error counter.
- * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
- * @retval None
- */
-#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
-
-/**
- * @brief Disable the oscillator clock for frequency error counter.
- * @retval None
- */
-#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
-
-/**
- * @brief Enable the automatic hardware adjustment of TRIM bits.
- * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
- * @retval None
- */
-#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
-
-/**
- * @brief Enable or disable the automatic hardware adjustment of TRIM bits.
- * @retval None
- */
-#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
-
-/**
- * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
- * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
- * of the synchronization source after prescaling. It is then decreased by one in order to
- * reach the expected synchronization on the zero value. The formula is the following:
- * RELOAD = (fTARGET / fSYNC) -1
- * @param __FTARGET__ Target frequency (value in Hz)
- * @param __FSYNC__ Synchronization signal frequency (value in Hz)
- * @retval None
- */
-#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
-
-/**
- * @}
- */
-
-#endif /* CRS */
-
-#if defined(PSSI)
-
-/** @defgroup RCCEx_PSSI_Macros_Aliases RCCEx PSSI Macros Aliases
- * @{
- */
-
-#define __HAL_RCC_PSSI_CLK_ENABLE() __HAL_RCC_DCMI_CLK_ENABLE()
-
-#define __HAL_RCC_PSSI_CLK_DISABLE() __HAL_RCC_DCMI_CLK_DISABLE()
-
-#define __HAL_RCC_PSSI_IS_CLK_ENABLED() __HAL_RCC_DCMI_IS_CLK_ENABLED()
-
-#define __HAL_RCC_PSSI_IS_CLK_DISABLED() __HAL_RCC_DCMI_IS_CLK_DISABLED()
-
-#define __HAL_RCC_PSSI_FORCE_RESET() __HAL_RCC_DCMI_FORCE_RESET()
-
-#define __HAL_RCC_PSSI_RELEASE_RESET() __HAL_RCC_DCMI_RELEASE_RESET()
-
-#define __HAL_RCC_PSSI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()
-
-#define __HAL_RCC_PSSI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()
-
-#define __HAL_RCC_PSSI_IS_CLK_SLEEP_ENABLED() __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()
-
-#define __HAL_RCC_PSSI_IS_CLK_SLEEP_DISABLED() __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()
-
-/**
- * @}
- */
-
-#endif /* PSSI */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCCEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup RCCEx_Exported_Functions_Group1
- * @{
- */
-
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
-
-/**
- * @}
- */
-
-/** @addtogroup RCCEx_Exported_Functions_Group2
- * @{
- */
-#if defined(RCC_PLLSAI1_SUPPORT)
-
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init);
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void);
-
-#endif /* RCC_PLLSAI1_SUPPORT */
-
-#if defined(RCC_PLLSAI2_SUPPORT)
-
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init);
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void);
-
-#endif /* RCC_PLLSAI2_SUPPORT */
-
-void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
-void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange);
-void HAL_RCCEx_EnableLSECSS(void);
-void HAL_RCCEx_DisableLSECSS(void);
-void HAL_RCCEx_EnableLSECSS_IT(void);
-void HAL_RCCEx_LSECSS_IRQHandler(void);
-void HAL_RCCEx_LSECSS_Callback(void);
-void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
-void HAL_RCCEx_DisableLSCO(void);
-void HAL_RCCEx_EnableMSIPLLMode(void);
-void HAL_RCCEx_DisableMSIPLLMode(void);
-#if defined (OCTOSPI1) && defined (OCTOSPI2)
-void HAL_RCCEx_OCTOSPIDelayConfig(uint32_t Delay1, uint32_t Delay2);
-#endif /* OCTOSPI1 && OCTOSPI2 */
-
-/**
- * @}
- */
-
-#if defined(CRS)
-
-/** @addtogroup RCCEx_Exported_Functions_Group3
- * @{
- */
-
-void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
-void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
-void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
-uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
-void HAL_RCCEx_CRS_IRQHandler(void);
-void HAL_RCCEx_CRS_SyncOkCallback(void);
-void HAL_RCCEx_CRS_SyncWarnCallback(void);
-void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
-void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
-
-/**
- * @}
- */
-
-#endif /* CRS */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup RCCEx_Private_Constants
- * @{
- */
-/* Define used for IS_RCC_* macros below */
-#if defined(STM32L412xx) || defined(STM32L422xx)
-#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
- RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | \
- RCC_PERIPHCLK_RNG)
-#elif defined(STM32L431xx)
-#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
- RCC_PERIPHCLK_SAI1 | \
- RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1)
-#elif defined(STM32L432xx) || defined(STM32L442xx)
-#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
- RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
- RCC_PERIPHCLK_SAI1 | \
- RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC | \
- RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG)
-#elif defined(STM32L433xx) || defined(STM32L443xx)
-#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\
- RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
- RCC_PERIPHCLK_SAI1 | \
- RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1)
-#elif defined(STM32L451xx)
-#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\
- RCC_PERIPHCLK_UART4 | \
- RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_I2C4 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
- RCC_PERIPHCLK_SAI1 | \
- RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1)
-#elif defined(STM32L452xx) || defined(STM32L462xx)
-#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\
- RCC_PERIPHCLK_UART4 | \
- RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_I2C4 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
- RCC_PERIPHCLK_SAI1 | \
- RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1)
-#elif defined(STM32L471xx)
-#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
- RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
- RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
- RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1)
-#elif defined(STM32L496xx) || defined(STM32L4A6xx)
-#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
- RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_I2C4 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
- RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
- RCC_PERIPHCLK_USB | \
- RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1)
-#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx)
-#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
- RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_I2C4 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
- RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
- RCC_PERIPHCLK_USB | \
- RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1AUDIO | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1 | \
- RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC)
-#elif defined(STM32L4R5xx) || defined(STM32L4S5xx)
-#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
- RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_I2C4 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
- RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
- RCC_PERIPHCLK_USB | \
- RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1AUDIO | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1 | \
- RCC_PERIPHCLK_OSPI)
-#elif defined(STM32L4R7xx) || defined(STM32L4S7xx)
-#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
- RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_I2C4 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
- RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
- RCC_PERIPHCLK_USB | \
- RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1AUDIO | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1 | \
- RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC)
-#elif defined(STM32L4R9xx) || defined(STM32L4S9xx)
-#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
- RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_I2C4 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
- RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
- RCC_PERIPHCLK_USB | \
- RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1AUDIO | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1 | \
- RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_DSI)
-#else
-#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
- RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
- RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
- RCC_PERIPHCLK_USB | \
- RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SDMMC1)
-#endif /* STM32L412xx || STM32L422xx */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCCEx_Private_Macros
- * @{
- */
-
-#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
- ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \
- (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == 0x00u))
-
-#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
- ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
-
-#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
-
-#if defined(USART3)
-
-#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
-
-#endif /* USART3 */
-
-#if defined(UART4)
-
-#define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
-
-#endif /* UART4 */
-
-#if defined(UART5)
-
-#define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
-
-#endif /* UART5 */
-
-#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
-
-#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
- ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
-
-#if defined(I2C2)
-
-#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
- ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
-
-#endif /* I2C2 */
-
-#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
- ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
-
-#if defined(I2C4)
-
-#define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
- ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI))
-
-#endif /* I2C4 */
-
-#if defined(RCC_PLLSAI2_SUPPORT)
-
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define IS_RCC_SAI1CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))
-#else
-#define IS_RCC_SAI1CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-#elif defined(RCC_PLLSAI1_SUPPORT)
-
-#define IS_RCC_SAI1CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
-
-#endif /* RCC_PLLSAI2_SUPPORT */
-
-#if defined(RCC_PLLSAI2_SUPPORT)
-
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define IS_RCC_SAI2CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \
- ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \
- ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI))
-#else
-#define IS_RCC_SAI2CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \
- ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-#endif /* RCC_PLLSAI2_SUPPORT */
-
-#define IS_RCC_LPTIM1CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
- ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
-
-#define IS_RCC_LPTIM2CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \
- ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
-
-#if defined(SDMMC1)
-#if defined(RCC_HSI48_SUPPORT) && defined(RCC_CCIPR2_SDMMCSEL)
-
-#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) || \
- ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \
- ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
-
-#elif defined(RCC_HSI48_SUPPORT)
-
-#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \
- ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
-#else
-
-#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE) || \
- ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
-
-#endif /* RCC_HSI48_SUPPORT */
-#endif /* SDMMC1 */
-
-#if defined(RCC_HSI48_SUPPORT)
-
-#if defined(RCC_PLLSAI1_SUPPORT)
-#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
- ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
-#else
-#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
- ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
-#endif /* RCC_PLLSAI1_SUPPORT */
-
-#else
-
-#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \
- ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
-
-#endif /* RCC_HSI48_SUPPORT */
-
-#if defined(USB_OTG_FS) || defined(USB)
-#if defined(RCC_HSI48_SUPPORT)
-
-#if defined(RCC_PLLSAI1_SUPPORT)
-#define IS_RCC_USBCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
- ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
-#else
-#define IS_RCC_USBCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
- ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
-#endif /* RCC_PLLSAI1_SUPPORT */
-
-#else
-
-#define IS_RCC_USBCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_USBCLKSOURCE_NONE) || \
- ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
-
-#endif /* RCC_HSI48_SUPPORT */
-#endif /* USB_OTG_FS || USB */
-
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
-
-#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
- ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \
- ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
-
-#else
-
-#if defined(RCC_PLLSAI1_SUPPORT)
-#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
- ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
-#else
-#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
- ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
-#endif /* RCC_PLLSAI1_SUPPORT */
-
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
-
-#if defined(SWPMI1)
-
-#define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI))
-
-#endif /* SWPMI1 */
-
-#if defined(DFSDM1_Filter0)
-
-#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \
- ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
-
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-
-#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \
- ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI))
-
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-#endif /* DFSDM1_Filter0 */
-
-#if defined(LTDC)
-
-#define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV2) || \
- ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV4) || \
- ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV8) || \
- ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV16))
-
-#endif /* LTDC */
-
-#if defined(DSI)
-
-#define IS_RCC_DSICLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY) || \
- ((__SOURCE__) == RCC_DSICLKSOURCE_PLLSAI2))
-
-#endif /* DSI */
-
-#if defined(OCTOSPI1) || defined(OCTOSPI2)
-
-#define IS_RCC_OSPICLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) || \
- ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL))
-
-#endif /* OCTOSPI1 || OCTOSPI2 */
-
-#if defined(RCC_PLLSAI1_SUPPORT)
-
-#define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
-
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
-#define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
-#else
-#define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
-#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
-
-#if defined(RCC_PLLSAI1N_MUL_8_127_SUPPORT)
-#define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U))
-#else
-#define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
-#endif /* RCC_PLLSAI1N_MUL_8_127_SUPPORT */
-
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
-#define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
-#else
-#define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
-#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
-
-#define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
- ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
-
-#define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
- ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
-
-#endif /* RCC_PLLSAI1_SUPPORT */
-
-#if defined(RCC_PLLSAI2_SUPPORT)
-
-#define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
-
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
-#define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
-#else
-#define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
-#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
-
-#if defined(RCC_PLLSAI2N_MUL_8_127_SUPPORT)
-#define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U))
-#else
-#define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
-#endif /* RCC_PLLSAI2N_MUL_8_127_SUPPORT */
-
-#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
-#define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
-#else
-#define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
-#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
-
-#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
-#define IS_RCC_PLLSAI2Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
- ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
-#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
-
-#define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
- ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
-
-#endif /* RCC_PLLSAI2_SUPPORT */
-
-#if defined (OCTOSPI1) && defined (OCTOSPI2)
-#define IS_RCC_OCTOSPIDELAY(__DELAY__) (((__DELAY__) <= 0xFU))
-#endif /* OCTOSPI1 && OCTOSPI2 */
-
-#if defined(CRS)
-
-#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
- ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
- ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
-
-#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
- ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
- ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
- ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
-
-#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
- ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
-
-#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
-
-#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
-
-#if defined(STM32L412xx) || defined(STM32L422xx)
-#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU))
-#else
-#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
-#endif /* STM32L412xx || STM32L422xx */
-
-#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
- ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
-
-#endif /* CRS */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L4xx_HAL_RCC_EX_H */
-
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h
deleted file mode 100644
index a1768ed..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h
+++ /dev/null
@@ -1,2361 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_tim.h
- * @author MCD Application Team
- * @brief Header file of TIM HAL module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L4xx_HAL_TIM_H
-#define STM32L4xx_HAL_TIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup TIM
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIM_Exported_Types TIM Exported Types
- * @{
- */
-
-/**
- * @brief TIM Time base Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
- uint32_t CounterMode; /*!< Specifies the counter mode.
- This parameter can be a value of @ref TIM_Counter_Mode */
-
- uint32_t Period; /*!< Specifies the period value to be loaded into the active
- Auto-Reload Register at the next update event.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t ClockDivision; /*!< Specifies the clock division.
- This parameter can be a value of @ref TIM_ClockDivision */
-
- uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
- reaches zero, an update event is generated and counting restarts
- from the RCR value (N).
- This means in PWM mode that (N+1) corresponds to:
- - the number of PWM periods in edge-aligned mode
- - the number of half PWM period in center-aligned mode
- GP timers: this parameter must be a number between Min_Data = 0x00 and
- Max_Data = 0xFF.
- Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
- Max_Data = 0xFFFF. */
-
- uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
- This parameter can be a value of @ref TIM_AutoReloadPreload */
-} TIM_Base_InitTypeDef;
-
-/**
- * @brief TIM Output Compare Configuration Structure definition
- */
-typedef struct
-{
- uint32_t OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
- uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
- uint32_t OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for timer instances supporting break feature. */
-
- uint32_t OCFastMode; /*!< Specifies the Fast mode state.
- This parameter can be a value of @ref TIM_Output_Fast_State
- @note This parameter is valid only in PWM1 and PWM2 mode. */
-
-
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for timer instances supporting break feature. */
-
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for timer instances supporting break feature. */
-} TIM_OC_InitTypeDef;
-
-/**
- * @brief TIM One Pulse Mode Configuration Structure definition
- */
-typedef struct
-{
- uint32_t OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
- uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
- uint32_t OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for timer instances supporting break feature. */
-
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for timer instances supporting break feature. */
-
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for timer instances supporting break feature. */
-
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_OnePulse_InitTypeDef;
-
-/**
- * @brief TIM Input Capture Configuration Structure definition
- */
-typedef struct
-{
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_IC_InitTypeDef;
-
-/**
- * @brief TIM Encoder Configuration Structure definition
- */
-typedef struct
-{
- uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Encoder_Mode */
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
-
- uint32_t IC1Selection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t IC1Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
- uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
-
- uint32_t IC2Selection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t IC2Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_Encoder_InitTypeDef;
-
-/**
- * @brief Clock Configuration Handle Structure definition
- */
-typedef struct
-{
- uint32_t ClockSource; /*!< TIM clock sources
- This parameter can be a value of @ref TIM_Clock_Source */
- uint32_t ClockPolarity; /*!< TIM clock polarity
- This parameter can be a value of @ref TIM_Clock_Polarity */
- uint32_t ClockPrescaler; /*!< TIM clock prescaler
- This parameter can be a value of @ref TIM_Clock_Prescaler */
- uint32_t ClockFilter; /*!< TIM clock filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_ClockConfigTypeDef;
-
-/**
- * @brief TIM Clear Input Configuration Handle Structure definition
- */
-typedef struct
-{
- uint32_t ClearInputState; /*!< TIM clear Input state
- This parameter can be ENABLE or DISABLE */
- uint32_t ClearInputSource; /*!< TIM clear Input sources
- This parameter can be a value of @ref TIM_ClearInput_Source */
- uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
- This parameter can be a value of @ref TIM_ClearInput_Polarity */
- uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
- This parameter must be 0: When OCRef clear feature is used with ETR source,
- ETR prescaler must be off */
- uint32_t ClearInputFilter; /*!< TIM Clear Input filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_ClearInputConfigTypeDef;
-
-/**
- * @brief TIM Master configuration Structure definition
- * @note Advanced timers provide TRGO2 internal line which is redirected
- * to the ADC
- */
-typedef struct
-{
- uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
- This parameter can be a value of @ref TIM_Master_Mode_Selection */
- uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
- This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
- uint32_t MasterSlaveMode; /*!< Master/slave mode selection
- This parameter can be a value of @ref TIM_Master_Slave_Mode
- @note When the Master/slave mode is enabled, the effect of
- an event on the trigger input (TRGI) is delayed to allow a
- perfect synchronization between the current timer and its
- slaves (through TRGO). It is not mandatory in case of timer
- synchronization mode. */
-} TIM_MasterConfigTypeDef;
-
-/**
- * @brief TIM Slave configuration Structure definition
- */
-typedef struct
-{
- uint32_t SlaveMode; /*!< Slave mode selection
- This parameter can be a value of @ref TIM_Slave_Mode */
- uint32_t InputTrigger; /*!< Input Trigger source
- This parameter can be a value of @ref TIM_Trigger_Selection */
- uint32_t TriggerPolarity; /*!< Input Trigger polarity
- This parameter can be a value of @ref TIM_Trigger_Polarity */
- uint32_t TriggerPrescaler; /*!< Input trigger prescaler
- This parameter can be a value of @ref TIM_Trigger_Prescaler */
- uint32_t TriggerFilter; /*!< Input trigger filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
-} TIM_SlaveConfigTypeDef;
-
-/**
- * @brief TIM Break input(s) and Dead time configuration Structure definition
- * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
- * filter and polarity.
- */
-typedef struct
-{
- uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
-
- uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
-
- uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
-
- uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
-
- uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
-
- uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
-
- uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
- uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
-
- uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */
-
- uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
- uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-
-} TIM_BreakDeadTimeConfigTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
- HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
- HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
- HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
-} HAL_TIM_StateTypeDef;
-
-/**
- * @brief TIM Channel States definition
- */
-typedef enum
-{
- HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
- HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
- HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
-} HAL_TIM_ChannelStateTypeDef;
-
-/**
- * @brief DMA Burst States definition
- */
-typedef enum
-{
- HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
- HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
- HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
-} HAL_TIM_DMABurstStateTypeDef;
-
-/**
- * @brief HAL Active channel structures definition
- */
-typedef enum
-{
- HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
- HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
- HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
- HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
- HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */
- HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */
- HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
-} HAL_TIM_ActiveChannel;
-
-/**
- * @brief TIM Time Base Handle Structure definition
- */
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-typedef struct __TIM_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-{
- TIM_TypeDef *Instance; /*!< Register base address */
- TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
- HAL_TIM_ActiveChannel Channel; /*!< Active channel */
- DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
- This array is accessed by a @ref DMA_Handle_index */
- HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
- __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */
- __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
- __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
- void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
- void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
- void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
- void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
- void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
- void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
- void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
- void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
- void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
- void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
- void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
- void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */
- void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
- void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
- void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */
- void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
- void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */
- void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
- void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */
- void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
- void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
- void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */
- void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
- void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
- void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */
- void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
- void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-} TIM_HandleTypeDef;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL TIM Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
- , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
- , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
- , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
- , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
- , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
- , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
- , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
- , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
- , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
- , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
- , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
- , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
- , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
- , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
- , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
- , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
- , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
-
- , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
- , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
- , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
- , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
- , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
- , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
- , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
- , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
- , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
- , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
-} HAL_TIM_CallbackIDTypeDef;
-
-/**
- * @brief HAL TIM Callback pointer definition
- */
-typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
-
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-/* End of exported types -----------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Constants TIM Exported Constants
- * @{
- */
-
-/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
- * @{
- */
-#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */
-#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
-#define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
- * @{
- */
-#define TIM_DMABASE_CR1 0x00000000U
-#define TIM_DMABASE_CR2 0x00000001U
-#define TIM_DMABASE_SMCR 0x00000002U
-#define TIM_DMABASE_DIER 0x00000003U
-#define TIM_DMABASE_SR 0x00000004U
-#define TIM_DMABASE_EGR 0x00000005U
-#define TIM_DMABASE_CCMR1 0x00000006U
-#define TIM_DMABASE_CCMR2 0x00000007U
-#define TIM_DMABASE_CCER 0x00000008U
-#define TIM_DMABASE_CNT 0x00000009U
-#define TIM_DMABASE_PSC 0x0000000AU
-#define TIM_DMABASE_ARR 0x0000000BU
-#define TIM_DMABASE_RCR 0x0000000CU
-#define TIM_DMABASE_CCR1 0x0000000DU
-#define TIM_DMABASE_CCR2 0x0000000EU
-#define TIM_DMABASE_CCR3 0x0000000FU
-#define TIM_DMABASE_CCR4 0x00000010U
-#define TIM_DMABASE_BDTR 0x00000011U
-#define TIM_DMABASE_DCR 0x00000012U
-#define TIM_DMABASE_DMAR 0x00000013U
-#define TIM_DMABASE_OR1 0x00000014U
-#define TIM_DMABASE_CCMR3 0x00000015U
-#define TIM_DMABASE_CCR5 0x00000016U
-#define TIM_DMABASE_CCR6 0x00000017U
-#define TIM_DMABASE_OR2 0x00000018U
-#define TIM_DMABASE_OR3 0x00000019U
-/**
- * @}
- */
-
-/** @defgroup TIM_Event_Source TIM Event Source
- * @{
- */
-#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
-#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
-#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
-#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
-#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
-#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
-#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
-#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
-#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
- * @{
- */
-#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
-#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */
-#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
-/**
- * @}
- */
-
-/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
- * @{
- */
-#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
-/**
- * @}
- */
-
-/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
- * @{
- */
-#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
-#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
-#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
-#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Counter_Mode TIM Counter Mode
- * @{
- */
-#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
-#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
-#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
-#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
-#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
- * @{
- */
-#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */
-#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_ClockDivision TIM Clock Division
- * @{
- */
-#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
-#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
-#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_State TIM Output Compare State
- * @{
- */
-#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */
-#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
- * @{
- */
-#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */
-#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Fast_State TIM Output Fast State
- * @{
- */
-#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
-#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
- * @{
- */
-#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
-#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
- * @{
- */
-#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
-#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
- * @{
- */
-#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */
-#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
- * @{
- */
-#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
-#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
- * @{
- */
-#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
-#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
- * @{
- */
-#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
-#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
-#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
-/**
- * @}
- */
-
-/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
- * @{
- */
-#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
-#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
- * @{
- */
-#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
-#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
- * @{
- */
-#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
-#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
-#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
-#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
-/**
- * @}
- */
-
-/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
- * @{
- */
-#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
-#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
-/**
- * @}
- */
-
-/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
- * @{
- */
-#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
-#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
-#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
-/**
- * @}
- */
-
-/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
- * @{
- */
-#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
-#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
-#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
-#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
-#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
-#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */
-#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
-#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */
-/**
- * @}
- */
-
-/** @defgroup TIM_Commutation_Source TIM Commutation Source
- * @{
- */
-#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
-#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_sources TIM DMA Sources
- * @{
- */
-#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */
-#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
-#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
-#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
-#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
-#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
-#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
-/**
- * @}
- */
-
-/** @defgroup TIM_Flag_definition TIM Flag Definition
- * @{
- */
-#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
-#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
-#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
-#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
-#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
-#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */
-#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */
-#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */
-#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
-#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */
-#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */
-#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */
-#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
-#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
-#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
-#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
-/**
- * @}
- */
-
-/** @defgroup TIM_Channel TIM Channel
- * @{
- */
-#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
-#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
-#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */
-#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */
-#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */
-#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */
-#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Source TIM Clock Source
- * @{
- */
-#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
-#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
-#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
-#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
-#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
-#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
-#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
-#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
-#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
-#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
- * @{
- */
-#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
- * @{
- */
-#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
-/**
- * @}
- */
-
-/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
- * @{
- */
-#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
-/**
- * @}
- */
-
-/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
- * @{
- */
-#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
- * @{
- */
-#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
-#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
- * @{
- */
-#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
-#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
-/**
- * @}
- */
-/** @defgroup TIM_Lock_level TIM Lock level
- * @{
- */
-#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */
-#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
-#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
-#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
- * @{
- */
-#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */
-#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
- * @{
- */
-#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
-#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
-/**
- * @}
- */
-
-/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
- * @{
- */
-#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */
-#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
- * @{
- */
-#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
-#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
-/**
- * @}
- */
-
-/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
- * @{
- */
-#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
-#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
-/**
- * @}
- */
-
-/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3
- * @{
- */
-#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
-#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
-#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
-#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
- * @{
- */
-#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
-#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
-#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
-#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
-#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
-#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
-#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
-#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
- * @{
- */
-#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */
-#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */
-#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */
-#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
-#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */
-#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */
-#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */
-#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */
-#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */
-#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */
-#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */
-#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */
-#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */
-#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
-#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
-#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
- * @{
- */
-#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
-#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */
-/**
- * @}
- */
-
-/** @defgroup TIM_Slave_Mode TIM Slave mode
- * @{
- */
-#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
-#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
-#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
-#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
-#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
-#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
- * @{
- */
-#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */
-#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
-#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
-#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
-#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */
-#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
-#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
-#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */
-#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */
-#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
-#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
-#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
-#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
-#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
- * @{
- */
-#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
-#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
-#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
-#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
-#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
-#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
-#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
-#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
-#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
- * @{
- */
-#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
- * @{
- */
-#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
-#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
-#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
-/**
- * @}
- */
-
-/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
- * @{
- */
-#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
-#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
- * @{
- */
-#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-/**
- * @}
- */
-
-/** @defgroup DMA_Handle_index TIM DMA Handle Index
- * @{
- */
-#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
-#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
-/**
- * @}
- */
-
-/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
- * @{
- */
-#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
-#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */
-#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */
-#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_System TIM Break System
- * @{
- */
-#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
-#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
-#define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */
-#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported constants -------------------------------------------------*/
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup TIM_Exported_Macros TIM Exported Macros
- * @{
- */
-
-/** @brief Reset TIM handle state.
- * @param __HANDLE__ TIM handle.
- * @retval None
- */
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
- (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
- (__HANDLE__)->Base_MspInitCallback = NULL; \
- (__HANDLE__)->Base_MspDeInitCallback = NULL; \
- (__HANDLE__)->IC_MspInitCallback = NULL; \
- (__HANDLE__)->IC_MspDeInitCallback = NULL; \
- (__HANDLE__)->OC_MspInitCallback = NULL; \
- (__HANDLE__)->OC_MspDeInitCallback = NULL; \
- (__HANDLE__)->PWM_MspInitCallback = NULL; \
- (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
- (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
- (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
- (__HANDLE__)->Encoder_MspInitCallback = NULL; \
- (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
- (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
- (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
- (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
- } while(0)
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @brief Enable the TIM peripheral.
- * @param __HANDLE__ TIM handle
- * @retval None
- */
-#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
-
-/**
- * @brief Enable the TIM main Output.
- * @param __HANDLE__ TIM handle
- * @retval None
- */
-#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
-
-/**
- * @brief Disable the TIM peripheral.
- * @param __HANDLE__ TIM handle
- * @retval None
- */
-#define __HAL_TIM_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
- { \
- (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
- } \
- } \
- } while(0)
-
-/**
- * @brief Disable the TIM main Output.
- * @param __HANDLE__ TIM handle
- * @retval None
- * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
- * disabled
- */
-#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
- { \
- (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
- } \
- } \
- } while(0)
-
-/**
- * @brief Disable the TIM main Output.
- * @param __HANDLE__ TIM handle
- * @retval None
- * @note The Main Output Enable of a timer instance is disabled unconditionally
- */
-#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
-
-/** @brief Enable the specified TIM interrupt.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @retval None
- */
-#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
-
-/** @brief Disable the specified TIM interrupt.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @retval None
- */
-#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
-
-/** @brief Enable the specified DMA request.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __DMA__ specifies the TIM DMA request to enable.
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: Update DMA request
- * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
- * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
- * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
- * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
- * @arg TIM_DMA_COM: Commutation DMA request
- * @arg TIM_DMA_TRIGGER: Trigger DMA request
- * @retval None
- */
-#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
-
-/** @brief Disable the specified DMA request.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __DMA__ specifies the TIM DMA request to disable.
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: Update DMA request
- * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
- * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
- * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
- * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
- * @arg TIM_DMA_COM: Commutation DMA request
- * @arg TIM_DMA_TRIGGER: Trigger DMA request
- * @retval None
- */
-#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
-
-/** @brief Check whether the specified TIM interrupt flag is set or not.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __FLAG__ specifies the TIM interrupt flag to check.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_UPDATE: Update interrupt flag
- * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
- * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
- * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
- * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
- * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
- * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
- * @arg TIM_FLAG_COM: Commutation interrupt flag
- * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
- * @arg TIM_FLAG_BREAK: Break interrupt flag
- * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
- * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
- * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
- * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
- * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
- * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the specified TIM interrupt flag.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __FLAG__ specifies the TIM interrupt flag to clear.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_UPDATE: Update interrupt flag
- * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
- * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
- * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
- * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
- * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
- * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
- * @arg TIM_FLAG_COM: Commutation interrupt flag
- * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
- * @arg TIM_FLAG_BREAK: Break interrupt flag
- * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
- * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
- * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
- * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
- * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
- * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/**
- * @brief Check whether the specified TIM interrupt source is enabled or not.
- * @param __HANDLE__ TIM handle
- * @param __INTERRUPT__ specifies the TIM interrupt source to check.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @retval The state of TIM_IT (SET or RESET).
- */
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
- == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Clear the TIM interrupt pending bits.
- * @param __HANDLE__ TIM handle
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @retval None
- */
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
-
-/**
- * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
- * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
- * in an atomic way.
- * @param __HANDLE__ TIM handle.
- * @retval None
-mode.
- */
-#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
-
-/**
- * @brief Disable update interrupt flag (UIF) remapping.
- * @param __HANDLE__ TIM handle.
- * @retval None
-mode.
- */
-#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
-
-/**
- * @brief Get update interrupt flag (UIF) copy status.
- * @param __COUNTER__ Counter value.
- * @retval The state of UIFCPY (TRUE or FALSE).
-mode.
- */
-#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
-
-/**
- * @brief Indicates whether or not the TIM Counter is used as downcounter.
- * @param __HANDLE__ TIM handle.
- * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
- * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
- * or Encoder mode.
- */
-#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
-
-/**
- * @brief Set the TIM Prescaler on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __PRESC__ specifies the Prescaler new value.
- * @retval None
- */
-#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
-
-/**
- * @brief Set the TIM Counter Register value on runtime.
- * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in
- * case of 32 bits counter TIM instance.
- * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
- * @param __HANDLE__ TIM handle.
- * @param __COUNTER__ specifies the Counter register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
-
-/**
- * @brief Get the TIM Counter Register value on runtime.
- * @param __HANDLE__ TIM handle.
- * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
- */
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
-
-/**
- * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
- * @param __HANDLE__ TIM handle.
- * @param __AUTORELOAD__ specifies the Counter register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
- do{ \
- (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
- (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
- } while(0)
-
-/**
- * @brief Get the TIM Autoreload Register value on runtime.
- * @param __HANDLE__ TIM handle.
- * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
- */
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
-
-/**
- * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
- * @param __HANDLE__ TIM handle.
- * @param __CKD__ specifies the clock division value.
- * This parameter can be one of the following value:
- * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
- * @retval None
- */
-#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
- do{ \
- (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
- (__HANDLE__)->Instance->CR1 |= (__CKD__); \
- (__HANDLE__)->Init.ClockDivision = (__CKD__); \
- } while(0)
-
-/**
- * @brief Get the TIM Clock Division value on runtime.
- * @param __HANDLE__ TIM handle.
- * @retval The clock division can be one of the following values:
- * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
- */
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
-
-/**
- * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
- * function.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
- do{ \
- TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
- } while(0)
-
-/**
- * @brief Get the TIM Input Capture prescaler on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
- * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
- * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
- * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
- * @retval The input capture prescaler can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- */
-#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
- (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
-
-/**
- * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @param __COMPARE__ specifies the Capture Compare register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
- ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
-
-/**
- * @brief Get the TIM Capture Compare Register value on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channel associated with the capture compare register
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: get capture/compare 1 register value
- * @arg TIM_CHANNEL_2: get capture/compare 2 register value
- * @arg TIM_CHANNEL_3: get capture/compare 3 register value
- * @arg TIM_CHANNEL_4: get capture/compare 4 register value
- * @arg TIM_CHANNEL_5: get capture/compare 5 register value
- * @arg TIM_CHANNEL_6: get capture/compare 6 register value
- * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
- */
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
- ((__HANDLE__)->Instance->CCR6))
-
-/**
- * @brief Set the TIM Output compare preload.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval None
- */
-#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
- ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
-
-/**
- * @brief Reset the TIM Output compare preload.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval None
- */
-#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
- ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
-
-/**
- * @brief Enable fast mode for a given channel.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @note When fast mode is enabled an active edge on the trigger input acts
- * like a compare match on CCx output. Delay to sample the trigger
- * input and to activate CCx output is reduced to 3 clock cycles.
- * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
- * @retval None
- */
-#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
- ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
-
-/**
- * @brief Disable fast mode for a given channel.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @note When fast mode is disabled CCx output behaves normally depending
- * on counter and CCRx values even when the trigger is ON. The minimum
- * delay to activate CCx output when an active edge occurs on the
- * trigger input is 5 clock cycles.
- * @retval None
- */
-#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
- ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
-
-/**
- * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
- * @param __HANDLE__ TIM handle.
- * @note When the URS bit of the TIMx_CR1 register is set, only counter
- * overflow/underflow generates an update interrupt or DMA request (if
- * enabled)
- * @retval None
- */
-#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
-
-/**
- * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
- * @param __HANDLE__ TIM handle.
- * @note When the URS bit of the TIMx_CR1 register is reset, any of the
- * following events generate an update interrupt or DMA request (if
- * enabled):
- * _ Counter overflow underflow
- * _ Setting the UG bit
- * _ Update generation through the slave mode controller
- * @retval None
- */
-#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
-
-/**
- * @brief Set the TIM Capture x input polarity on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __POLARITY__ Polarity for TIx source
- * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
- * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
- * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
- * @retval None
- */
-#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
- do{ \
- TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
- }while(0)
-
-/**
- * @}
- */
-/* End of exported macros ----------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIM_Private_Constants TIM Private Constants
- * @{
- */
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
-#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
-/**
- * @}
- */
-/* End of private constants --------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
- * @{
- */
-#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
- ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
- ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
-
-#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
- ((__BASE__) == TIM_DMABASE_CR2) || \
- ((__BASE__) == TIM_DMABASE_SMCR) || \
- ((__BASE__) == TIM_DMABASE_DIER) || \
- ((__BASE__) == TIM_DMABASE_SR) || \
- ((__BASE__) == TIM_DMABASE_EGR) || \
- ((__BASE__) == TIM_DMABASE_CCMR1) || \
- ((__BASE__) == TIM_DMABASE_CCMR2) || \
- ((__BASE__) == TIM_DMABASE_CCER) || \
- ((__BASE__) == TIM_DMABASE_CNT) || \
- ((__BASE__) == TIM_DMABASE_PSC) || \
- ((__BASE__) == TIM_DMABASE_ARR) || \
- ((__BASE__) == TIM_DMABASE_RCR) || \
- ((__BASE__) == TIM_DMABASE_CCR1) || \
- ((__BASE__) == TIM_DMABASE_CCR2) || \
- ((__BASE__) == TIM_DMABASE_CCR3) || \
- ((__BASE__) == TIM_DMABASE_CCR4) || \
- ((__BASE__) == TIM_DMABASE_BDTR) || \
- ((__BASE__) == TIM_DMABASE_OR1) || \
- ((__BASE__) == TIM_DMABASE_CCMR3) || \
- ((__BASE__) == TIM_DMABASE_CCR5) || \
- ((__BASE__) == TIM_DMABASE_CCR6) || \
- ((__BASE__) == TIM_DMABASE_OR2) || \
- ((__BASE__) == TIM_DMABASE_OR3))
-
-#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
-
-#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
- ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
- ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
- ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
- ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
-
-#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
- ((__MODE__) == TIM_UIFREMAP_ENALE))
-
-#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
- ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
- ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
-
-#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
- ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
-
-#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
- ((__STATE__) == TIM_OCFAST_ENABLE))
-
-#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
- ((__POLARITY__) == TIM_OCPOLARITY_LOW))
-
-#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
- ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
-
-#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
- ((__STATE__) == TIM_OCIDLESTATE_RESET))
-
-#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
- ((__STATE__) == TIM_OCNIDLESTATE_RESET))
-
-#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
- ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
-
-#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
- ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
- ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
-
-#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
- ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
- ((__SELECTION__) == TIM_ICSELECTION_TRC))
-
-#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
- ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
- ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
- ((__PRESCALER__) == TIM_ICPSC_DIV8))
-
-#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
- ((__MODE__) == TIM_OPMODE_REPETITIVE))
-
-#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
- ((__MODE__) == TIM_ENCODERMODE_TI2) || \
- ((__MODE__) == TIM_ENCODERMODE_TI12))
-
-#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
-
-#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
- ((__CHANNEL__) == TIM_CHANNEL_2) || \
- ((__CHANNEL__) == TIM_CHANNEL_3) || \
- ((__CHANNEL__) == TIM_CHANNEL_4) || \
- ((__CHANNEL__) == TIM_CHANNEL_5) || \
- ((__CHANNEL__) == TIM_CHANNEL_6) || \
- ((__CHANNEL__) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
- ((__CHANNEL__) == TIM_CHANNEL_2))
-
-#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
- ((__CHANNEL__) == TIM_CHANNEL_2) || \
- ((__CHANNEL__) == TIM_CHANNEL_3))
-
-#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
-
-#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
-
-#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
- ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
- ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
- ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
-
-#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
- ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
-
-#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
- ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
- ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
- ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
-
-#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
- ((__STATE__) == TIM_OSSR_DISABLE))
-
-#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
- ((__STATE__) == TIM_OSSI_DISABLE))
-
-#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
- ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
- ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
- ((__LEVEL__) == TIM_LOCKLEVEL_3))
-
-#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
-
-
-#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
- ((__STATE__) == TIM_BREAK_DISABLE))
-
-#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
- ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
-
-#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \
- ((__STATE__) == TIM_BREAK2_DISABLE))
-
-#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
- ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
- ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
-
-#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
-
-#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
- ((__SOURCE__) == TIM_TRGO_ENABLE) || \
- ((__SOURCE__) == TIM_TRGO_UPDATE) || \
- ((__SOURCE__) == TIM_TRGO_OC1) || \
- ((__SOURCE__) == TIM_TRGO_OC1REF) || \
- ((__SOURCE__) == TIM_TRGO_OC2REF) || \
- ((__SOURCE__) == TIM_TRGO_OC3REF) || \
- ((__SOURCE__) == TIM_TRGO_OC4REF))
-
-#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \
- ((__SOURCE__) == TIM_TRGO2_ENABLE) || \
- ((__SOURCE__) == TIM_TRGO2_UPDATE) || \
- ((__SOURCE__) == TIM_TRGO2_OC1) || \
- ((__SOURCE__) == TIM_TRGO2_OC1REF) || \
- ((__SOURCE__) == TIM_TRGO2_OC2REF) || \
- ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
- ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
- ((__SOURCE__) == TIM_TRGO2_OC4REF) || \
- ((__SOURCE__) == TIM_TRGO2_OC5REF) || \
- ((__SOURCE__) == TIM_TRGO2_OC6REF) || \
- ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
- ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
- ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
- ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
- ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
- ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
-
-#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
- ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
-
-#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
- ((__MODE__) == TIM_SLAVEMODE_RESET) || \
- ((__MODE__) == TIM_SLAVEMODE_GATED) || \
- ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
- ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
- ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
-
-#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
- ((__MODE__) == TIM_OCMODE_PWM2) || \
- ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
- ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
- ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
- ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
-
-#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
- ((__MODE__) == TIM_OCMODE_ACTIVE) || \
- ((__MODE__) == TIM_OCMODE_INACTIVE) || \
- ((__MODE__) == TIM_OCMODE_TOGGLE) || \
- ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
- ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
- ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
- ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
-
-#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
- ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || \
- ((__SELECTION__) == TIM_TS_ETRF))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
- ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_NONE))
-
-#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
-
-#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
- ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
- ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
- ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
-
-#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
- ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
-
-#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
-
-#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
-
-#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
-
-#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \
- ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
- ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) || \
- ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
-
-#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
- ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
-
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
-
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
-
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
-
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
- ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
-
-#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
- (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
- (__HANDLE__)->ChannelState[5])
-
-#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
- ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
-
-#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
- (__HANDLE__)->ChannelState[0] = \
- (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[1] = \
- (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[2] = \
- (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[3] = \
- (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[4] = \
- (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[5] = \
- (__CHANNEL_STATE__); \
- } while(0)
-
-#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
- (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
- (__HANDLE__)->ChannelNState[3])
-
-#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
- ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
-
-#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
- (__HANDLE__)->ChannelNState[0] = \
- (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelNState[1] = \
- (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelNState[2] = \
- (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelNState[3] = \
- (__CHANNEL_STATE__); \
- } while(0)
-
-/**
- * @}
- */
-/* End of private macros -----------------------------------------------------*/
-
-/* Include TIM HAL Extended module */
-#include "stm32l4xx_hal_tim_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_Exported_Functions TIM Exported Functions
- * @{
- */
-
-/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
- * @brief Time Base functions
- * @{
- */
-/* Time Base functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
- * @brief TIM Output Compare functions
- * @{
- */
-/* Timer Output Compare functions *********************************************/
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
- * @brief TIM PWM functions
- * @{
- */
-/* Timer PWM functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
- * @brief TIM Input Capture functions
- * @{
- */
-/* Timer Input Capture functions **********************************************/
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
- * @brief TIM One Pulse functions
- * @{
- */
-/* Timer One Pulse functions **************************************************/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
- * @brief TIM Encoder functions
- * @{
- */
-/* Timer Encoder functions ****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
- uint32_t *pData2, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- * @brief IRQ handler management
- * @{
- */
-/* Interrupt Handler functions ***********************************************/
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
- * @brief Peripheral Control functions
- * @{
- */
-/* Control functions *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
- uint32_t OutputChannel, uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
- uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
- uint32_t BurstLength, uint32_t DataLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
- uint32_t BurstLength, uint32_t DataLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- * @brief TIM Callbacks functions
- * @{
- */
-/* Callback in non blocking modes (Interrupt and DMA) *************************/
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
-
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
- pTIM_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
- * @brief Peripheral State functions
- * @{
- */
-/* Peripheral State functions ************************************************/
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
-
-/* Peripheral Channel state functions ************************************************/
-HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
-HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private functions----------------------------------------------------------*/
-/** @defgroup TIM_Private_Functions TIM Private Functions
- * @{
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-
-void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
-void TIM_DMAError(DMA_HandleTypeDef *hdma);
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
-void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-void TIM_ResetCallback(TIM_HandleTypeDef *htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-/* End of private functions --------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L4xx_HAL_TIM_H */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h
deleted file mode 100644
index a5ba3a5..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h
+++ /dev/null
@@ -1,437 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_tim_ex.h
- * @author MCD Application Team
- * @brief Header file of TIM HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L4xx_HAL_TIM_EX_H
-#define STM32L4xx_HAL_TIM_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal_def.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup TIMEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
- * @{
- */
-
-/**
- * @brief TIM Hall sensor Configuration Structure definition
- */
-
-typedef struct
-{
- uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t IC1Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
- uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-} TIM_HallSensor_InitTypeDef;
-
-/**
- * @brief TIM Break/Break2 input configuration
- */
-typedef struct
-{
- uint32_t Source; /*!< Specifies the source of the timer break input.
- This parameter can be a value of @ref TIMEx_Break_Input_Source */
- uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
- This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
- uint32_t Polarity; /*!< Specifies the break input source polarity.
- This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
- Not relevant when analog watchdog output of the DFSDM1 used as break input source */
-} TIMEx_BreakInputConfigTypeDef;
-
-/**
- * @}
- */
-/* End of exported types -----------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
- * @{
- */
-
-/** @defgroup TIMEx_Remap TIM Extended Remapping
- * @{
- */
-#define TIM_TIM1_ETR_ADC1_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR1_ETR_ADC1_RMP_0 /* !< TIM1_ETR is connected to ADC1 AWD1 */
-#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR1_ETR_ADC1_RMP_1 /* !< TIM1_ETR is connected to ADC1 AWD2 */
-#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
-#if defined (ADC3)
-#define TIM_TIM1_ETR_ADC3_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM1_ETR_ADC3_AWD1 TIM1_OR1_ETR_ADC3_RMP_0 /* !< TIM1_ETR is connected to ADC3 AWD1 */
-#define TIM_TIM1_ETR_ADC3_AWD2 TIM1_OR1_ETR_ADC3_RMP_1 /* !< TIM1_ETR is connected to ADC3 AWD2 */
-#define TIM_TIM1_ETR_ADC3_AWD3 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD3 */
-#endif /* ADC3 */
-#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1 TI1 is connected to GPIO */
-#define TIM_TIM1_TI1_COMP1 TIM1_OR1_TI1_RMP /* !< TIM1 TI1 is connected to COMP1 */
-#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
-#define TIM_TIM1_ETR_COMP1 TIM1_OR2_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */
-#if defined(COMP2)
-#define TIM_TIM1_ETR_COMP2 TIM1_OR2_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */
-#endif /* COMP2 */
-
-#if defined (USB_OTG_FS)
-#define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */
-#define TIM_TIM2_ITR1_OTG_FS_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to OTG_FS SOF */
-#else
-#if defined(STM32L471xx)
-#define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */
-#define TIM_TIM2_ITR1_NONE TIM2_OR1_ITR1_RMP /* !< No internal trigger on TIM2_ITR1 */
-#else
-#define TIM_TIM2_ITR1_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */
-#define TIM_TIM2_ITR1_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */
-#endif /* STM32L471xx */
-#endif /* USB_OTG_FS */
-#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */
-#define TIM_TIM2_ETR_LSE TIM2_OR1_ETR1_RMP /* !< TIM2_ETR is connected to LSE */
-#define TIM_TIM2_ETR_COMP1 TIM2_OR2_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */
-#if defined(COMP2)
-#define TIM_TIM2_ETR_COMP2 TIM2_OR2_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */
-#endif /* COMP2 */
-#define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2 TI4 is connected to GPIO */
-#define TIM_TIM2_TI4_COMP1 TIM2_OR1_TI4_RMP_0 /* !< TIM2 TI4 is connected to COMP1 output */
-#if defined(COMP2)
-#define TIM_TIM2_TI4_COMP2 TIM2_OR1_TI4_RMP_1 /* !< TIM2 TI4 is connected to COMP2 output */
-#define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */
-#endif /* COMP2 */
-
-#if defined (TIM3)
-#define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3 TI1 is connected to GPIO */
-#define TIM_TIM3_TI1_COMP1 TIM3_OR1_TI1_RMP_0 /* !< TIM3 TI1 is connected to COMP1 output */
-#define TIM_TIM3_TI1_COMP2 TIM3_OR1_TI1_RMP_1 /* !< TIM3 TI1 is connected to COMP2 output */
-#define TIM_TIM3_TI1_COMP1_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */
-#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */
-#define TIM_TIM3_ETR_COMP1 TIM3_OR2_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 output */
-#endif /* TIM3 */
-
-#if defined (TIM8)
-#if defined(ADC2) && defined(ADC3)
-#define TIM_TIM8_ETR_ADC2_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM8_ETR_ADC2_AWD1 TIM8_OR1_ETR_ADC2_RMP_0 /* !< TIM8_ETR is connected to ADC2 AWD1 */
-#define TIM_TIM8_ETR_ADC2_AWD2 TIM8_OR1_ETR_ADC2_RMP_1 /* !< TIM8_ETR is connected to ADC2 AWD2 */
-#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
-#define TIM_TIM8_ETR_ADC3_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM8_ETR_ADC3_AWD1 TIM8_OR1_ETR_ADC3_RMP_0 /* !< TIM8_ETR is connected to ADC3 AWD1 */
-#define TIM_TIM8_ETR_ADC3_AWD2 TIM8_OR1_ETR_ADC3_RMP_1 /* !< TIM8_ETR is connected to ADC3 AWD2 */
-#define TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */
-#endif /* ADC2 && ADC3 */
-
-#define TIM_TIM8_TI1_GPIO 0x00000000U /* !< TIM8 TI1 is connected to GPIO */
-#define TIM_TIM8_TI1_COMP2 TIM8_OR1_TI1_RMP /* !< TIM8 TI1 is connected to COMP1 */
-#define TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */
-#define TIM_TIM8_ETR_COMP1 TIM8_OR2_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 output */
-#define TIM_TIM8_ETR_COMP2 TIM8_OR2_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 output */
-#endif /* TIM8 */
-
-#define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15 TI1 is connected to GPIO */
-#define TIM_TIM15_TI1_LSE TIM15_OR1_TI1_RMP /* !< TIM15 TI1 is connected to LSE */
-#define TIM_TIM15_ENCODERMODE_NONE 0x00000000U /* !< No redirection */
-#define TIM_TIM15_ENCODERMODE_TIM2 TIM15_OR1_ENCODER_MODE_0 /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
-#if defined (TIM3)
-#define TIM_TIM15_ENCODERMODE_TIM3 TIM15_OR1_ENCODER_MODE_1 /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
-#endif /* TIM3 */
-#if defined (TIM4)
-#define TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
-#endif /* TIM4 */
-
-#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16 TI1 is connected to GPIO */
-#define TIM_TIM16_TI1_LSI TIM16_OR1_TI1_RMP_0 /* !< TIM16 TI1 is connected to LSI */
-#define TIM_TIM16_TI1_LSE TIM16_OR1_TI1_RMP_1 /* !< TIM16 TI1 is connected to LSE */
-#define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to RTC wakeup interrupt */
-#if defined (TIM16_OR1_TI1_RMP_2)
-#define TIM_TIM16_TI1_MSI TIM16_OR1_TI1_RMP_2 /* !< TIM16 TI1 is connected to MSI */
-#define TIM_TIM16_TI1_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to HSE div 32 */
-#define TIM_TIM16_TI1_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to MCO */
-#endif /* TIM16_OR1_TI1_RMP_2 */
-
-#if defined (TIM17)
-#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */
-#define TIM_TIM17_TI1_MSI TIM17_OR1_TI1_RMP_0 /* !< TIM17 TI1 is connected to MSI */
-#define TIM_TIM17_TI1_HSE_32 TIM17_OR1_TI1_RMP_1 /* !< TIM17 TI1 is connected to HSE div 32 */
-#define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */
-#endif /* TIM17 */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Break_Input TIM Extended Break input
- * @{
- */
-#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */
-#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
- * @{
- */
-#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
-#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */
-#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */
-#if defined (DFSDM1_Channel0)
-#define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
-#endif /* DFSDM1_Channel0 */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
- * @{
- */
-#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */
-#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
- * @{
- */
-#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */
-#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported constants -------------------------------------------------*/
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
- * @{
- */
-
-/**
- * @}
- */
-/* End of exported macro -----------------------------------------------------*/
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
- * @{
- */
-#define IS_TIM_REMAP(__REMAP__) (((__REMAP__) <= (uint32_t)0x0001C01F))
-
-#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
- ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
-
-#if defined (DFSDM1_Channel0)
-#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
-#else
-#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))
-#endif /* DFSDM1_Channel0 */
-
-#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
- ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
-
-#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
- ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
-
-/**
- * @}
- */
-/* End of private macro ------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
- * @{
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
- * @brief Timer Hall Sensor functions
- * @{
- */
-/* Timer Hall Sensor functions **********************************************/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
-
-void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
- * @brief Timer Complementary Output Compare functions
- * @{
- */
-/* Timer Complementary Output Compare functions *****************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
- * @brief Timer Complementary PWM functions
- * @{
- */
-/* Timer Complementary PWM functions ****************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
- * @brief Timer Complementary One Pulse functions
- * @{
- */
-/* Timer Complementary One Pulse functions **********************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
- * @brief Peripheral Control functions
- * @{
- */
-/* Extended Control functions ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
- uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
- uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
- uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
- TIM_MasterConfigTypeDef *sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
- TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
- TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
-HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
- * @brief Extended Callbacks functions
- * @{
- */
-/* Extended Callback **********************************************************/
-void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
- * @brief Extended Peripheral State functions
- * @{
- */
-/* Extended Peripheral State functions ***************************************/
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private functions----------------------------------------------------------*/
-/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
- * @{
- */
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
-void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-/* End of private functions --------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32L4xx_HAL_TIM_EX_H */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h
new file mode 100644
index 0000000..55927f3
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h
@@ -0,0 +1,1954 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_bus.h
+ * @author MCD Application Team
+ * @brief Header file of BUS LL module.
+
+ @verbatim
+ ##### RCC Limitations #####
+ ==============================================================================
+ [..]
+ A delay between an RCC peripheral clock enable and the effective peripheral
+ enabling should be taken into account in order to manage the peripheral read/write
+ from/to registers.
+ (+) This delay depends on the peripheral mapping.
+ (++) AHB & APB peripherals, 1 dummy read is necessary
+
+ [..]
+ Workarounds:
+ (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+ inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L4xx_LL_BUS_H
+#define STM32L4xx_LL_BUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @defgroup BUS_LL BUS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+ * @{
+ */
+
+/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
+ * @{
+ */
+#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
+#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
+#if defined(DMAMUX1)
+#define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN
+#endif /* DMAMUX1 */
+#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
+#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
+#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
+#if defined(DMA2D)
+#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
+#endif /* DMA2D */
+#if defined(GFXMMU)
+#define LL_AHB1_GRP1_PERIPH_GFXMMU RCC_AHB1ENR_GFXMMUEN
+#endif /* GFXMMU */
+#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
+ * @{
+ */
+#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
+#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
+#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
+#if defined(GPIOD)
+#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
+#endif /*GPIOD*/
+#if defined(GPIOE)
+#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
+#endif /*GPIOE*/
+#if defined(GPIOF)
+#define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
+#endif /* GPIOF */
+#if defined(GPIOG)
+#define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
+#endif /* GPIOG */
+#define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
+#if defined(GPIOI)
+#define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR_GPIOIEN
+#endif /* GPIOI */
+#if defined(USB_OTG_FS)
+#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
+#endif /* USB_OTG_FS */
+#define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
+#if defined(DCMI)
+#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
+#endif /* DCMI */
+#if defined(AES)
+#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
+#endif /* AES */
+#if defined(HASH)
+#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
+#endif /* HASH */
+#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
+#if defined(OCTOSPIM)
+#define LL_AHB2_GRP1_PERIPH_OSPIM RCC_AHB2ENR_OSPIMEN
+#endif /* OCTOSPIM */
+#if defined(PKA)
+#define LL_AHB2_GRP1_PERIPH_PKA RCC_AHB2ENR_PKAEN
+#endif /* PKA */
+#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)
+#define LL_AHB2_GRP1_PERIPH_SDMMC1 RCC_AHB2ENR_SDMMC1EN
+#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */
+#define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
+#if defined(SRAM3_BASE)
+#define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2SMENR_SRAM3SMEN
+#endif /* SRAM3_BASE */
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
+ * @{
+ */
+#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#if defined(FMC_Bank1_R)
+#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
+#endif /* FMC_Bank1_R */
+#if defined(QUADSPI)
+#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
+#endif /* QUADSPI */
+#if defined(OCTOSPI1)
+#define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN
+#endif /* OCTOSPI1 */
+#if defined(OCTOSPI2)
+#define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN
+#endif /* OCTOSPI2 */
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
+ * @{
+ */
+#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
+#if defined(TIM3)
+#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
+#endif /* TIM3 */
+#if defined(TIM4)
+#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
+#endif /* TIM4 */
+#if defined(TIM5)
+#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
+#endif /* TIM5 */
+#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
+#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
+#if defined(LCD)
+#define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN
+#endif /* LCD */
+#if defined(RCC_APB1ENR1_RTCAPBEN)
+#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
+#endif /* RCC_APB1ENR1_RTCAPBEN */
+#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
+#if defined(SPI2)
+#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
+#endif /* SPI2 */
+#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
+#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
+#if defined(USART3)
+#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
+#endif /* USART3 */
+#if defined(UART4)
+#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
+#endif /* UART4 */
+#if defined(UART5)
+#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
+#endif /* UART5 */
+#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
+#if defined(I2C2)
+#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
+#endif /* I2C2 */
+#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
+#if defined(CRS)
+#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
+#endif /* CRS */
+#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR1_CAN1EN
+#if defined(CAN2)
+#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR1_CAN2EN
+#endif /* CAN2 */
+#if defined(USB)
+#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBFSEN
+#endif /* USB */
+#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
+#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN
+#define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN
+#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
+/**
+ * @}
+ */
+
+
+/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
+ * @{
+ */
+#define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
+#define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
+#if defined(I2C4)
+#define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN
+#endif /* I2C4 */
+#if defined(SWPMI1)
+#define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1ENR2_SWPMI1EN
+#endif /* SWPMI1 */
+#define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
+ * @{
+ */
+#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
+#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
+#define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN
+#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
+#define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN
+#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
+#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
+#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
+#if defined(TIM8)
+#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
+#endif /* TIM8 */
+#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
+#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
+#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
+#if defined(TIM17)
+#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
+#endif /* TIM17 */
+#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
+#if defined(SAI2)
+#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
+#endif /* SAI2 */
+#if defined(DFSDM1_Channel0)
+#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
+#endif /* DFSDM1_Channel0 */
+#if defined(LTDC)
+#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
+#endif /* LTDC */
+#if defined(DSI)
+#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN
+#endif /* DSI */
+/**
+ * @}
+ */
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+*/
+#if defined(DFSDM1_Channel0)
+#define LL_APB2_GRP1_PERIPH_DFSDM LL_APB2_GRP1_PERIPH_DFSDM1
+#endif /* DFSDM1_Channel0 */
+/**
+@endcond
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+ * @{
+ */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+ * @{
+ */
+
+/**
+ * @brief Enable AHB1 peripherals clock.
+ * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB1ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB1 peripheral clock is enabled or not
+ * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable AHB1 peripherals clock.
+ * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
+ * AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB1ENR, Periphs);
+}
+
+/**
+ * @brief Force AHB1 peripherals reset.
+ * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n
+ * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+ * @brief Release AHB1 peripherals reset.
+ * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+ * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
+ * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_EnableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB1SMENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
+ * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_DisableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB1SMENR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_AHB2 AHB2
+ * @{
+ */
+
+/**
+ * @brief Enable AHB2 peripherals clock.
+ * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR GPIOIEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR OSPIMEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR SDMMC1EN LL_AHB2_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB2ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB2 peripheral clock is enabled or not
+ * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR OSPIMEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR SDMMC1EN LL_AHB2_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable AHB2 peripherals clock.
+ * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR GPIOIEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR OSPIMEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR SDMMC1EN LL_AHB2_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB2ENR, Periphs);
+}
+
+/**
+ * @brief Force AHB2 peripherals reset.
+ * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR GPIOIRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR OSPIMRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+ * @brief Release AHB2 peripherals reset.
+ * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR GPIOIRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR OSPIMRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+ * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR DCMISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
+ * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB2SMENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR DCMISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
+ * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
+ * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+ * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB2SMENR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_AHB3 AHB3
+ * @{
+ */
+
+/**
+ * @brief Enable AHB3 peripherals clock.
+ * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
+ * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n
+ * AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock\n
+ * AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB3ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB3 peripheral clock is enabled or not
+ * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
+ * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n
+ * AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock\n
+ * AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable AHB3 peripherals clock.
+ * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
+ * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n
+ * AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock\n
+ * AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB3ENR, Periphs);
+}
+
+/**
+ * @brief Force AHB3 peripherals reset.
+ * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
+ * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n
+ * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n
+ * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+ * @brief Release AHB3 peripherals reset.
+ * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
+ * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n
+ * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset\n
+ * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+ * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n
+ * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep\n
+ * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
+ * AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_EnableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHB3SMENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes
+ * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n
+ * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep\n
+ * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
+ * AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHB3SMENR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+ * @{
+ */
+
+/**
+ * @brief Enable APB1 peripherals clock.
+ * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 CAN1EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 USBFSEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 CAN2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+ * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1ENR1, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Enable APB1 peripherals clock.
+ * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
+ * APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n
+ * APB1ENR2 SWPMI1EN LL_APB1_GRP2_EnableClock\n
+ * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1ENR2, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if APB1 peripheral clock is enabled or not
+ * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 USBFSEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 CAN2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+ * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if APB1 peripheral clock is enabled or not
+ * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
+ * APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n
+ * APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock\n
+ * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable APB1 peripherals clock.
+ * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 CAN1EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 USBFSEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 CAN2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+ * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1ENR1, Periphs);
+}
+
+/**
+ * @brief Disable APB1 peripherals clock.
+ * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
+ * APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n
+ * APB1ENR2 SWPMI1EN LL_APB1_GRP2_DisableClock\n
+ * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1ENR2, Periphs);
+}
+
+/**
+ * @brief Force APB1 peripherals reset.
+ * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 CAN1RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 USBFSRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 CAN2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+ * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->APB1RSTR1, Periphs);
+}
+
+/**
+ * @brief Force APB1 peripherals reset.
+ * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n
+ * APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset\n
+ * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ForceReset\n
+ * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->APB1RSTR2, Periphs);
+}
+
+/**
+ * @brief Release APB1 peripherals reset.
+ * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 CAN1RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 USBFSRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 CAN2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+ * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1RSTR1, Periphs);
+}
+
+/**
+ * @brief Release APB1 peripherals reset.
+ * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n
+ * APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n
+ * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ReleaseReset\n
+ * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1RSTR2, Periphs);
+}
+
+/**
+ * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 USBFSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 CAN2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep\n
+ * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+ * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1SMENR1, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
+ * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n
+ * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
+ * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1SMENR2, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 USBFSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 CAN2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep\n
+ * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+ * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+ * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
+ * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1SMENR1, Periphs);
+}
+
+/**
+ * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
+ * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n
+ * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
+ * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
+ * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1SMENR2, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+ * @{
+ */
+
+/**
+ * @brief Enable APB2 peripherals clock.
+ * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR DSIEN LL_APB2_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_FW
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB2ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if APB2 peripheral clock is enabled or not
+ * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_FW
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable APB2 peripherals clock.
+ * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR DSIEN LL_APB2_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB2ENR, Periphs);
+}
+
+/**
+ * @brief Force APB2 peripherals reset.
+ * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+ * @brief Release APB2 peripherals reset.
+ * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+ * @brief Enable APB2 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR LTDCSMEN LL_APB2_GRP1_EnableClockStopSleep\n
+ * APB2SMENR DSISMEN LL_APB2_GRP1_EnableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB2SMENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Disable APB2 peripheral clocks in Sleep and Stop modes
+ * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR LTDCSMEN LL_APB2_GRP1_DisableClockStopSleep\n
+ * APB2SMENR DSISMEN LL_APB2_GRP1_DisableClockStopSleep
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB2SMENR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RCC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L4xx_LL_BUS_H */
+
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h
new file mode 100644
index 0000000..4ad94d6
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h
@@ -0,0 +1,637 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_cortex.h
+ * @author MCD Application Team
+ * @brief Header file of CORTEX LL module.
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL CORTEX driver contains a set of generic APIs that can be
+ used by user:
+ (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
+ functions
+ (+) Low power mode configuration (SCB register of Cortex-MCU)
+ (+) MPU API to configure and enable regions
+ (+) API to access to MCU info (CPUID register)
+ (+) API to enable fault handler (SHCSR accesses)
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L4xx_LL_CORTEX_H
+#define STM32L4xx_LL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX_LL CORTEX
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
+ * @{
+ */
+
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
+ * @{
+ */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
+#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
+ * @{
+ */
+#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
+#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
+#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
+/**
+ * @}
+ */
+
+#if __MPU_PRESENT
+
+/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
+ * @{
+ */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
+#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
+ * @{
+ */
+#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
+#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
+#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
+#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
+#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
+#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
+#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
+#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
+ * @{
+ */
+#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
+ * @{
+ */
+#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
+#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
+#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
+#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
+#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
+#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
+ * @{
+ */
+#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
+#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
+#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
+#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
+ * @{
+ */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
+#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
+#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
+#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
+ * @{
+ */
+
+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
+ * @{
+ */
+
+/**
+ * @brief This function checks if the Systick counter flag is active or not.
+ * @note It can be used in timeout function on application side.
+ * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
+{
+ return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
+}
+
+/**
+ * @brief Configures the SysTick clock source
+ * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
+{
+ if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
+ {
+ SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+ }
+ else
+ {
+ CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+ }
+}
+
+/**
+ * @brief Get the SysTick clock source
+ * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
+{
+ return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+}
+
+/**
+ * @brief Enable SysTick exception request
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
+{
+ SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Disable SysTick exception request
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
+{
+ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Checks if the SYSTICK interrupt is enabled or disabled.
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
+{
+ return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
+ * @{
+ */
+
+/**
+ * @brief Processor uses sleep as its low power mode
+ * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
+{
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Processor uses deep sleep as its low power mode
+ * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
+{
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
+ * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
+ * empty main application.
+ * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
+{
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Do not sleep when returning to Thread mode.
+ * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
+{
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
+ * processor.
+ * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
+{
+ /* Set SEVEONPEND bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
+ * excluded
+ * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
+{
+ /* Clear SEVEONPEND bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
+ * @{
+ */
+
+/**
+ * @brief Enable a fault in System handler control register (SHCSR)
+ * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
+ * @param Fault This parameter can be a combination of the following values:
+ * @arg @ref LL_HANDLER_FAULT_USG
+ * @arg @ref LL_HANDLER_FAULT_BUS
+ * @arg @ref LL_HANDLER_FAULT_MEM
+ * @retval None
+ */
+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
+{
+ /* Enable the system handler fault */
+ SET_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+ * @brief Disable a fault in System handler control register (SHCSR)
+ * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
+ * @param Fault This parameter can be a combination of the following values:
+ * @arg @ref LL_HANDLER_FAULT_USG
+ * @arg @ref LL_HANDLER_FAULT_BUS
+ * @arg @ref LL_HANDLER_FAULT_MEM
+ * @retval None
+ */
+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
+{
+ /* Disable the system handler fault */
+ CLEAR_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
+ * @{
+ */
+
+/**
+ * @brief Get Implementer code
+ * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
+ * @retval Value should be equal to 0x41 for ARM
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
+}
+
+/**
+ * @brief Get Variant number (The r value in the rnpn product revision identifier)
+ * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
+ * @retval Value between 0 and 255 (0x0: revision 0)
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
+}
+
+/**
+ * @brief Get Constant number
+ * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
+ * @retval Value should be equal to 0xF for Cortex-M4 devices
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
+}
+
+/**
+ * @brief Get Part number
+ * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
+ * @retval Value should be equal to 0xC24 for Cortex-M4
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
+}
+
+/**
+ * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
+ * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
+ * @retval Value between 0 and 255 (0x1: patch 1)
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
+}
+
+/**
+ * @}
+ */
+
+#if __MPU_PRESENT
+/** @defgroup CORTEX_LL_EF_MPU MPU
+ * @{
+ */
+
+/**
+ * @brief Enable MPU with input options
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
+ * @param Options This parameter can be one of the following values:
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+ * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+ * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
+{
+ /* Enable the MPU*/
+ WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
+ /* Ensure MPU settings take effects */
+ __DSB();
+ /* Sequence instruction fetches using update settings */
+ __ISB();
+}
+
+/**
+ * @brief Disable MPU
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Disable(void)
+{
+ /* Make sure outstanding transfers are done */
+ __DMB();
+ /* Disable MPU*/
+ WRITE_REG(MPU->CTRL, 0U);
+}
+
+/**
+ * @brief Check if MPU is enabled or not
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
+{
+ return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
+}
+
+/**
+ * @brief Enable a MPU region
+ * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Enable the MPU region */
+ SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @brief Configure and enable a region
+ * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
+ * MPU_RBAR REGION LL_MPU_ConfigRegion\n
+ * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
+ * MPU_RASR XN LL_MPU_ConfigRegion\n
+ * MPU_RASR AP LL_MPU_ConfigRegion\n
+ * MPU_RASR S LL_MPU_ConfigRegion\n
+ * MPU_RASR C LL_MPU_ConfigRegion\n
+ * MPU_RASR B LL_MPU_ConfigRegion\n
+ * MPU_RASR SIZE LL_MPU_ConfigRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param Address Value of region base address
+ * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
+ * @param Attributes This parameter can be a combination of the following values:
+ * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
+ * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
+ * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
+ * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
+ * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
+ * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
+ * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
+ * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
+ * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+ * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+ * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
+ * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
+ * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Set base address */
+ WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
+ /* Configure MPU */
+ WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
+}
+
+/**
+ * @brief Disable a region
+ * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
+ * MPU_RASR ENABLE LL_MPU_DisableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Disable the MPU region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @}
+ */
+
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L4xx_LL_CORTEX_H */
+
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h
new file mode 100644
index 0000000..1d2b333
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h
@@ -0,0 +1,785 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_crs.h
+ * @author MCD Application Team
+ * @brief Header file of CRS LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L4xx_LL_CRS_H
+#define STM32L4xx_LL_CRS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined(CRS)
+
+/** @defgroup CRS_LL CRS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
+ * @{
+ */
+
+/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_CRS_ReadReg function
+ * @{
+ */
+#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
+#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
+#define LL_CRS_ISR_ERRF CRS_ISR_ERRF
+#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
+#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
+#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
+#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
+ * @{
+ */
+#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
+#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
+#define LL_CRS_CR_ERRIE CRS_CR_ERRIE
+#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
+ * @{
+ */
+#define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
+#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
+#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
+#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
+#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
+#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
+#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
+#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
+ * @{
+ */
+#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal source GPIO */
+#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
+#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
+ * @{
+ */
+#define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
+#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
+ * @{
+ */
+#define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */
+#define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
+ * @{
+ */
+/**
+ * @brief Reset value of the RELOAD field
+ * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
+ * and a synchronization signal frequency of 1 kHz (SOF signal from USB)
+ */
+#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
+
+/**
+ * @brief Reset value of Frequency error limit.
+ */
+#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
+
+/**
+ * @brief Reset value of the HSI48 Calibration field
+ * @note The default value is 64 for STM32L412xx/L422xx, 32 otherwise, which corresponds
+ * to the middle of the trimming interval.
+ * The trimming step is around 67 kHz between two consecutive TRIM steps.
+ * A higher TRIM value corresponds to a higher output frequency
+ */
+#if defined (STM32L412xx) || defined (STM32L422xx)
+#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)64U)
+#else
+#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)32U)
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
+ * @{
+ */
+
+/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in CRS register
+ * @param __INSTANCE__ CRS Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in CRS register
+ * @param __INSTANCE__ CRS Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
+ * @{
+ */
+
+/**
+ * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
+ * @note The RELOAD value should be selected according to the ratio between
+ * the target frequency and the frequency of the synchronization source after
+ * prescaling. It is then decreased by one in order to reach the expected
+ * synchronization on the zero value. The formula is the following:
+ * RELOAD = (fTARGET / fSYNC) -1
+ * @param __FTARGET__ Target frequency (value in Hz)
+ * @param __FSYNC__ Synchronization signal frequency (value in Hz)
+ * @retval Reload value (in Hz)
+ */
+#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
+ * @{
+ */
+
+/** @defgroup CRS_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable Frequency error counter
+ * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
+ * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
+{
+ SET_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+ * @brief Disable Frequency error counter
+ * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
+{
+ CLEAR_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+ * @brief Check if Frequency error counter is enabled or not
+ * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
+{
+ return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
+}
+
+/**
+ * @brief Enable Automatic trimming counter
+ * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
+{
+ SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+ * @brief Disable Automatic trimming counter
+ * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
+{
+ CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+ * @brief Check if Automatic trimming is enabled or not
+ * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
+{
+ return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
+}
+
+/**
+ * @brief Set HSI48 oscillator smooth trimming
+ * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
+ * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
+ * @param Value a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise
+ * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
+{
+ MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
+}
+
+/**
+ * @brief Get HSI48 oscillator smooth trimming
+ * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
+ * @retval a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
+{
+ return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
+}
+
+/**
+ * @brief Set counter reload value
+ * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
+ * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
+ * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
+ * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
+{
+ MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
+}
+
+/**
+ * @brief Get counter reload value
+ * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
+ * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
+{
+ return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
+}
+
+/**
+ * @brief Set frequency error limit
+ * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
+ * @param Value a number between Min_Data = 0 and Max_Data = 255
+ * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
+{
+ MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
+}
+
+/**
+ * @brief Get frequency error limit
+ * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
+ * @retval A number between Min_Data = 0 and Max_Data = 255
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
+{
+ return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
+}
+
+/**
+ * @brief Set division factor for SYNC signal
+ * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
+ * @param Divider This parameter can be one of the following values:
+ * @arg @ref LL_CRS_SYNC_DIV_1
+ * @arg @ref LL_CRS_SYNC_DIV_2
+ * @arg @ref LL_CRS_SYNC_DIV_4
+ * @arg @ref LL_CRS_SYNC_DIV_8
+ * @arg @ref LL_CRS_SYNC_DIV_16
+ * @arg @ref LL_CRS_SYNC_DIV_32
+ * @arg @ref LL_CRS_SYNC_DIV_64
+ * @arg @ref LL_CRS_SYNC_DIV_128
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
+{
+ MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
+}
+
+/**
+ * @brief Get division factor for SYNC signal
+ * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRS_SYNC_DIV_1
+ * @arg @ref LL_CRS_SYNC_DIV_2
+ * @arg @ref LL_CRS_SYNC_DIV_4
+ * @arg @ref LL_CRS_SYNC_DIV_8
+ * @arg @ref LL_CRS_SYNC_DIV_16
+ * @arg @ref LL_CRS_SYNC_DIV_32
+ * @arg @ref LL_CRS_SYNC_DIV_64
+ * @arg @ref LL_CRS_SYNC_DIV_128
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
+{
+ return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
+}
+
+/**
+ * @brief Set SYNC signal source
+ * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+ * @arg @ref LL_CRS_SYNC_SOURCE_LSE
+ * @arg @ref LL_CRS_SYNC_SOURCE_USB
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
+{
+ MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
+}
+
+/**
+ * @brief Get SYNC signal source
+ * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+ * @arg @ref LL_CRS_SYNC_SOURCE_LSE
+ * @arg @ref LL_CRS_SYNC_SOURCE_USB
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
+{
+ return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
+}
+
+/**
+ * @brief Set input polarity for the SYNC signal source
+ * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_CRS_SYNC_POLARITY_RISING
+ * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
+{
+ MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
+}
+
+/**
+ * @brief Get input polarity for the SYNC signal source
+ * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRS_SYNC_POLARITY_RISING
+ * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
+{
+ return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
+}
+
+/**
+ * @brief Configure CRS for the synchronization
+ * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
+ * CFGR RELOAD LL_CRS_ConfigSynchronization\n
+ * CFGR FELIM LL_CRS_ConfigSynchronization\n
+ * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
+ * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
+ * CFGR SYNCPOL LL_CRS_ConfigSynchronization
+ * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise
+ * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
+ * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
+ * @param Settings This parameter can be a combination of the following values:
+ * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
+ * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
+ * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
+ * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
+{
+ MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
+ MODIFY_REG(CRS->CFGR,
+ CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
+ ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
+ * @{
+ */
+
+/**
+ * @brief Generate software SYNC event
+ * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
+{
+ SET_BIT(CRS->CR, CRS_CR_SWSYNC);
+}
+
+/**
+ * @brief Get the frequency error direction latched in the time of the last
+ * SYNC event
+ * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
+ * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
+{
+ return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
+}
+
+/**
+ * @brief Get the frequency error counter value latched in the time of the last SYNC event
+ * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
+ * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
+{
+ return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check if SYNC event OK signal occurred or not
+ * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
+{
+ return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
+}
+
+/**
+ * @brief Check if SYNC warning signal occurred or not
+ * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
+{
+ return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
+}
+
+/**
+ * @brief Check if Synchronization or trimming error signal occurred or not
+ * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
+{
+ return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
+}
+
+/**
+ * @brief Check if Expected SYNC signal occurred or not
+ * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
+{
+ return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
+}
+
+/**
+ * @brief Check if SYNC error signal occurred or not
+ * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
+{
+ return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
+}
+
+/**
+ * @brief Check if SYNC missed error signal occurred or not
+ * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
+{
+ return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
+}
+
+/**
+ * @brief Check if Trimming overflow or underflow occurred or not
+ * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
+{
+ return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
+}
+
+/**
+ * @brief Clear the SYNC event OK flag
+ * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
+{
+ WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
+}
+
+/**
+ * @brief Clear the SYNC warning flag
+ * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
+{
+ WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
+}
+
+/**
+ * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
+ * the ERR flag
+ * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
+{
+ WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
+}
+
+/**
+ * @brief Clear Expected SYNC flag
+ * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
+{
+ WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRS_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable SYNC event OK interrupt
+ * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
+{
+ SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+ * @brief Disable SYNC event OK interrupt
+ * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
+{
+ CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+ * @brief Check if SYNC event OK interrupt is enabled or not
+ * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
+{
+ return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
+}
+
+/**
+ * @brief Enable SYNC warning interrupt
+ * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
+{
+ SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+ * @brief Disable SYNC warning interrupt
+ * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
+{
+ CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+ * @brief Check if SYNC warning interrupt is enabled or not
+ * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
+{
+ return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
+}
+
+/**
+ * @brief Enable Synchronization or trimming error interrupt
+ * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
+{
+ SET_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+ * @brief Disable Synchronization or trimming error interrupt
+ * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
+{
+ CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+ * @brief Check if Synchronization or trimming error interrupt is enabled or not
+ * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
+{
+ return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
+}
+
+/**
+ * @brief Enable Expected SYNC interrupt
+ * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
+{
+ SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+ * @brief Disable Expected SYNC interrupt
+ * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
+{
+ CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+ * @brief Check if Expected SYNC interrupt is enabled or not
+ * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
+{
+ return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_CRS_DeInit(void);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(CRS) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L4xx_LL_CRS_H */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h
new file mode 100644
index 0000000..add3c4a
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h
@@ -0,0 +1,2430 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_dma.h
+ * @author MCD Application Team
+ * @brief Header file of DMA LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L4xx_LL_DMA_H
+#define STM32L4xx_LL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+#if defined(DMAMUX1)
+#include "stm32l4xx_ll_dmamux.h"
+#endif /* DMAMUX1 */
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Variables DMA Private Variables
+ * @{
+ */
+/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
+static const uint8_t CHANNEL_OFFSET_TAB[] =
+{
+ (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
+};
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+#if defined(DMAMUX1)
+#else
+/** @defgroup DMA_LL_Private_Constants DMA Private Constants
+ * @{
+ */
+/* Define used to get CSELR register offset */
+#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
+
+/* Defines used for the bit position in the register and perform offsets */
+#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << (Channel*4U))
+/**
+ * @}
+ */
+#endif /* DMAMUX1 */
+/* Private macros ------------------------------------------------------------*/
+#if defined(DMAMUX1)
+
+/** @defgroup DMA_LL_Private_Macros DMA Private Macros
+ * @{
+ */
+/**
+ * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel
+ * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
+ * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
+ * @param __DMA_INSTANCE__ DMAx
+ * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0).
+ */
+#define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \
+(((__DMA_INSTANCE__) == DMA1) ? 0x00000000U : LL_DMA_CHANNEL_7)
+
+/**
+ * @}
+ */
+#else
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_Private_Macros DMA Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+#endif /* DMAMUX1 */
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+ * @{
+ */
+typedef struct
+{
+ uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
+ or as Source base address in case of memory to memory transfer direction.
+
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+ uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
+ or as Destination base address in case of memory to memory transfer direction.
+
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+ from memory to memory or from peripheral to memory.
+ This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
+
+ uint32_t Mode; /*!< Specifies the normal or circular operation mode.
+ This parameter can be a value of @ref DMA_LL_EC_MODE
+ @note: The circular buffer mode cannot be used if the memory to memory
+ data transfer direction is configured on the selected Channel
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
+
+ uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
+ is incremented or not.
+ This parameter can be a value of @ref DMA_LL_EC_PERIPH
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
+
+ uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
+ is incremented or not.
+ This parameter can be a value of @ref DMA_LL_EC_MEMORY
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
+
+ uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
+ in case of memory to memory transfer direction.
+ This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
+
+ uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
+ in case of memory to memory transfer direction.
+ This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
+
+ uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
+ The data unit is equal to the source buffer configuration set in PeripheralSize
+ or MemorySize parameters depending in the transfer direction.
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
+
+#if defined(DMAMUX1)
+ uint32_t PeriphRequest; /*!< Specifies the peripheral request.
+ This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
+#else
+ uint32_t PeriphRequest; /*!< Specifies the peripheral request.
+ This parameter can be a value of @ref DMA_LL_EC_REQUEST
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
+#endif /* DMAMUX1 */
+
+ uint32_t Priority; /*!< Specifies the channel priority level.
+ This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
+
+} LL_DMA_InitTypeDef;
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+ * @{
+ */
+/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_DMA_WriteReg function
+ * @{
+ */
+#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
+#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
+#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
+#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
+#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
+#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
+#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
+#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
+#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
+#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
+#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
+#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
+#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
+#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
+#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
+#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
+#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
+#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
+#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
+#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
+#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_DMA_ReadReg function
+ * @{
+ */
+#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
+#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
+#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
+#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
+#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
+#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
+#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
+#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
+#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
+#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
+#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
+#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
+#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
+#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
+#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
+#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
+#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
+#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
+#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
+#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
+#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
+#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
+#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
+#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
+#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
+#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
+#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
+#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
+ * @{
+ */
+#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
+#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
+#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
+ * @{
+ */
+#define LL_DMA_CHANNEL_1 0x00000000U /*!< DMA Channel 1 */
+#define LL_DMA_CHANNEL_2 0x00000001U /*!< DMA Channel 2 */
+#define LL_DMA_CHANNEL_3 0x00000002U /*!< DMA Channel 3 */
+#define LL_DMA_CHANNEL_4 0x00000003U /*!< DMA Channel 4 */
+#define LL_DMA_CHANNEL_5 0x00000004U /*!< DMA Channel 5 */
+#define LL_DMA_CHANNEL_6 0x00000005U /*!< DMA Channel 6 */
+#define LL_DMA_CHANNEL_7 0x00000006U /*!< DMA Channel 7 */
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
+#endif /*USE_FULL_LL_DRIVER*/
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
+ * @{
+ */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MODE Transfer mode
+ * @{
+ */
+#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
+#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
+ * @{
+ */
+#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
+#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
+ * @{
+ */
+#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
+#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
+ * @{
+ */
+#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
+#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
+#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
+ * @{
+ */
+#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
+#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
+#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
+ * @{
+ */
+#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
+#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
+#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
+#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
+/**
+ * @}
+ */
+
+#if !defined (DMAMUX1)
+/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
+ * @{
+ */
+#define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */
+#define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */
+#define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */
+#define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */
+#define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */
+#define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */
+#define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */
+#define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */
+/**
+ * @}
+ */
+#endif /* !defined DMAMUX1 */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+ * @{
+ */
+
+/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
+ * @{
+ */
+/**
+ * @brief Write a value in DMA register
+ * @param __INSTANCE__ DMA Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in DMA register
+ * @param __INSTANCE__ DMA Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
+ * @{
+ */
+/**
+ * @brief Convert DMAx_Channely into DMAx
+ * @param __CHANNEL_INSTANCE__ DMAx_Channely
+ * @retval DMAx
+ */
+#if defined(DMA2)
+#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
+(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
+#else
+#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
+#endif
+
+/**
+ * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
+ * @param __CHANNEL_INSTANCE__ DMAx_Channely
+ * @retval LL_DMA_CHANNEL_y
+ */
+#if defined (DMA2)
+#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ LL_DMA_CHANNEL_7)
+#else
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ LL_DMA_CHANNEL_7)
+#endif
+#else
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ LL_DMA_CHANNEL_7)
+#endif
+
+/**
+ * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
+ * @param __DMA_INSTANCE__ DMAx
+ * @param __CHANNEL__ LL_DMA_CHANNEL_y
+ * @retval DMAx_Channely
+ */
+#if defined (DMA2)
+#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
+ DMA2_Channel7)
+#else
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
+ DMA1_Channel7)
+#endif
+#else
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
+ DMA1_Channel7)
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_LL_EF_Configuration Configuration
+ * @{
+ */
+/**
+ * @brief Enable DMA channel.
+ * @rmtoll CCR EN LL_DMA_EnableChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
+}
+
+/**
+ * @brief Disable DMA channel.
+ * @rmtoll CCR EN LL_DMA_DisableChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
+}
+
+/**
+ * @brief Check if DMA channel is enabled or disabled.
+ * @rmtoll CCR EN LL_DMA_IsEnabledChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
+ DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure all parameters link to DMA transfer.
+ * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
+ * CCR MEM2MEM LL_DMA_ConfigTransfer\n
+ * CCR CIRC LL_DMA_ConfigTransfer\n
+ * CCR PINC LL_DMA_ConfigTransfer\n
+ * CCR MINC LL_DMA_ConfigTransfer\n
+ * CCR PSIZE LL_DMA_ConfigTransfer\n
+ * CCR MSIZE LL_DMA_ConfigTransfer\n
+ * CCR PL LL_DMA_ConfigTransfer
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
+ * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
+ * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
+ * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
+ Configuration);
+}
+
+/**
+ * @brief Set Data transfer direction (read from peripheral or from memory).
+ * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
+ * CCR MEM2MEM LL_DMA_SetDataTransferDirection
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
+}
+
+/**
+ * @brief Get Data transfer direction (read from peripheral or from memory).
+ * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
+ * CCR MEM2MEM LL_DMA_GetDataTransferDirection
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM));
+}
+
+/**
+ * @brief Set DMA mode circular or normal.
+ * @note The circular buffer mode cannot be used if the memory-to-memory
+ * data transfer is configured on the selected Channel.
+ * @rmtoll CCR CIRC LL_DMA_SetMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MODE_NORMAL
+ * @arg @ref LL_DMA_MODE_CIRCULAR
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CIRC,
+ Mode);
+}
+
+/**
+ * @brief Get DMA mode circular or normal.
+ * @rmtoll CCR CIRC LL_DMA_GetMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MODE_NORMAL
+ * @arg @ref LL_DMA_MODE_CIRCULAR
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
+ DMA_CCR_CIRC));
+}
+
+/**
+ * @brief Set Peripheral increment mode.
+ * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PERIPH_INCREMENT
+ * @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC,
+ PeriphOrM2MSrcIncMode);
+}
+
+/**
+ * @brief Get Peripheral increment mode.
+ * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PERIPH_INCREMENT
+ * @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
+ DMA_CCR_PINC));
+}
+
+/**
+ * @brief Set Memory increment mode.
+ * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MEMORY_INCREMENT
+ * @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MINC,
+ MemoryOrM2MDstIncMode);
+}
+
+/**
+ * @brief Get Memory increment mode.
+ * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MEMORY_INCREMENT
+ * @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
+ DMA_CCR_MINC));
+}
+
+/**
+ * @brief Set Peripheral size.
+ * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE
+ * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_PDATAALIGN_WORD
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE,
+ PeriphOrM2MSrcDataSize);
+}
+
+/**
+ * @brief Get Peripheral size.
+ * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE
+ * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_PDATAALIGN_WORD
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
+ DMA_CCR_PSIZE));
+}
+
+/**
+ * @brief Set Memory size.
+ * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE
+ * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_MDATAALIGN_WORD
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MSIZE,
+ MemoryOrM2MDstDataSize);
+}
+
+/**
+ * @brief Get Memory size.
+ * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE
+ * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_MDATAALIGN_WORD
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
+ DMA_CCR_MSIZE));
+}
+
+/**
+ * @brief Set Channel priority level.
+ * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Priority This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PRIORITY_LOW
+ * @arg @ref LL_DMA_PRIORITY_MEDIUM
+ * @arg @ref LL_DMA_PRIORITY_HIGH
+ * @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PL,
+ Priority);
+}
+
+/**
+ * @brief Get Channel priority level.
+ * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PRIORITY_LOW
+ * @arg @ref LL_DMA_PRIORITY_MEDIUM
+ * @arg @ref LL_DMA_PRIORITY_HIGH
+ * @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
+ DMA_CCR_PL));
+}
+
+/**
+ * @brief Set Number of data to transfer.
+ * @note This action has no effect if
+ * channel is enabled.
+ * @rmtoll CNDTR NDT LL_DMA_SetDataLength
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
+ DMA_CNDTR_NDT, NbData);
+}
+
+/**
+ * @brief Get Number of data to transfer.
+ * @note Once the channel is enabled, the return value indicate the
+ * remaining bytes to be transmitted.
+ * @rmtoll CNDTR NDT LL_DMA_GetDataLength
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
+ DMA_CNDTR_NDT));
+}
+
+/**
+ * @brief Configure the Source and Destination addresses.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @note Each peripheral using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
+ * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
+ * CMAR MA LL_DMA_ConfigAddresses
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
+ uint32_t DstAddress, uint32_t Direction)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ /* Direction Memory to Periph */
+ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
+ {
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, SrcAddress);
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, DstAddress);
+ }
+ /* Direction Periph to Memory and Memory to Memory */
+ else
+ {
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, SrcAddress);
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, DstAddress);
+ }
+}
+
+/**
+ * @brief Set the Memory address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress);
+}
+
+/**
+ * @brief Set the Peripheral address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, PeriphAddress);
+}
+
+/**
+ * @brief Get Memory address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR));
+}
+
+/**
+ * @brief Get Peripheral address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
+}
+
+/**
+ * @brief Set the Memory to Memory Source address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, MemoryAddress);
+}
+
+/**
+ * @brief Set the Memory to Memory Destination address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress);
+}
+
+/**
+ * @brief Get the Memory to Memory Source address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
+}
+
+/**
+ * @brief Get the Memory to Memory Destination address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR));
+}
+
+#if defined(DMAMUX1)
+/**
+ * @brief Set DMA request for DMA Channels on DMAMUX Channel x.
+ * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
+ * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
+ * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Request This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_MEM2MEM
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR0
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR1
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR2
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR3
+ * @arg @ref LL_DMAMUX_REQ_ADC1
+ * @arg @ref LL_DMAMUX_REQ_ADC2
+ * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
+ * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM6_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM7_UP
+ * @arg @ref LL_DMAMUX_REQ_SPI1_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI1_TX
+ * @arg @ref LL_DMAMUX_REQ_SPI2_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI2_TX
+ * @arg @ref LL_DMAMUX_REQ_SPI3_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI3_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C1_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C1_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C2_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C2_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C3_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C3_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C4_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C4_TX
+ * @arg @ref LL_DMAMUX_REQ_USART1_RX
+ * @arg @ref LL_DMAMUX_REQ_USART1_TX
+ * @arg @ref LL_DMAMUX_REQ_USART2_RX
+ * @arg @ref LL_DMAMUX_REQ_USART2_TX
+ * @arg @ref LL_DMAMUX_REQ_USART3_RX
+ * @arg @ref LL_DMAMUX_REQ_USART3_TX
+ * @arg @ref LL_DMAMUX_REQ_UART4_RX
+ * @arg @ref LL_DMAMUX_REQ_UART4_TX
+ * @arg @ref LL_DMAMUX_REQ_UART5_RX
+ * @arg @ref LL_DMAMUX_REQ_UART5_TX
+ * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
+ * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
+ * @arg @ref LL_DMAMUX_REQ_SAI1_A
+ * @arg @ref LL_DMAMUX_REQ_SAI1_B
+ * @arg @ref LL_DMAMUX_REQ_SAI2_A
+ * @arg @ref LL_DMAMUX_REQ_SAI2_B
+ * @arg @ref LL_DMAMUX_REQ_OSPI1
+ * @arg @ref LL_DMAMUX_REQ_OSPI2
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM1_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM1_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM8_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM8_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM2_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM3_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM4_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM5_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM15_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM15_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM16_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM17_UP
+ * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0
+ * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1
+ * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2
+ * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3
+ * @arg @ref LL_DMAMUX_REQ_DCMI
+ * @arg @ref LL_DMAMUX_REQ_DCMI_PSSI
+ * @arg @ref LL_DMAMUX_REQ_AES_IN
+ * @arg @ref LL_DMAMUX_REQ_AES_OUT
+ * @arg @ref LL_DMAMUX_REQ_HASH_IN
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
+{
+ uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U);
+ MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
+}
+
+/**
+ * @brief Get DMA request for DMA Channels on DMAMUX Channel x.
+ * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
+ * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
+ * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_MEM2MEM
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR0
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR1
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR2
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR3
+ * @arg @ref LL_DMAMUX_REQ_ADC1
+ * @arg @ref LL_DMAMUX_REQ_ADC2
+ * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
+ * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM6_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM7_UP
+ * @arg @ref LL_DMAMUX_REQ_SPI1_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI1_TX
+ * @arg @ref LL_DMAMUX_REQ_SPI2_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI2_TX
+ * @arg @ref LL_DMAMUX_REQ_SPI3_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI3_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C1_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C1_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C2_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C2_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C3_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C3_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C4_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C4_TX
+ * @arg @ref LL_DMAMUX_REQ_USART1_RX
+ * @arg @ref LL_DMAMUX_REQ_USART1_TX
+ * @arg @ref LL_DMAMUX_REQ_USART2_RX
+ * @arg @ref LL_DMAMUX_REQ_USART2_TX
+ * @arg @ref LL_DMAMUX_REQ_USART3_RX
+ * @arg @ref LL_DMAMUX_REQ_USART3_TX
+ * @arg @ref LL_DMAMUX_REQ_UART4_RX
+ * @arg @ref LL_DMAMUX_REQ_UART4_TX
+ * @arg @ref LL_DMAMUX_REQ_UART5_RX
+ * @arg @ref LL_DMAMUX_REQ_UART5_TX
+ * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
+ * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
+ * @arg @ref LL_DMAMUX_REQ_SAI1_A
+ * @arg @ref LL_DMAMUX_REQ_SAI1_B
+ * @arg @ref LL_DMAMUX_REQ_SAI2_A
+ * @arg @ref LL_DMAMUX_REQ_SAI2_B
+ * @arg @ref LL_DMAMUX_REQ_OSPI1
+ * @arg @ref LL_DMAMUX_REQ_OSPI2
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM1_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM1_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM8_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM8_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM2_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM3_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM4_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM5_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM15_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM15_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM16_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM17_UP
+ * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0
+ * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1
+ * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2
+ * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3
+ * @arg @ref LL_DMAMUX_REQ_DCMI
+ * @arg @ref LL_DMAMUX_REQ_DCMI_PSSI
+ * @arg @ref LL_DMAMUX_REQ_AES_IN
+ * @arg @ref LL_DMAMUX_REQ_AES_OUT
+ * @arg @ref LL_DMAMUX_REQ_HASH_IN
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U);
+ return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID));
+}
+
+#else
+/**
+ * @brief Set DMA request for DMA instance on Channel x.
+ * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
+ * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
+ * CSELR C2S LL_DMA_SetPeriphRequest\n
+ * CSELR C3S LL_DMA_SetPeriphRequest\n
+ * CSELR C4S LL_DMA_SetPeriphRequest\n
+ * CSELR C5S LL_DMA_SetPeriphRequest\n
+ * CSELR C6S LL_DMA_SetPeriphRequest\n
+ * CSELR C7S LL_DMA_SetPeriphRequest
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param PeriphRequest This parameter can be one of the following values:
+ * @arg @ref LL_DMA_REQUEST_0
+ * @arg @ref LL_DMA_REQUEST_1
+ * @arg @ref LL_DMA_REQUEST_2
+ * @arg @ref LL_DMA_REQUEST_3
+ * @arg @ref LL_DMA_REQUEST_4
+ * @arg @ref LL_DMA_REQUEST_5
+ * @arg @ref LL_DMA_REQUEST_6
+ * @arg @ref LL_DMA_REQUEST_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
+{
+ MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
+ DMA_CSELR_C1S << ((Channel) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
+}
+
+/**
+ * @brief Get DMA request for DMA instance on Channel x.
+ * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
+ * CSELR C2S LL_DMA_GetPeriphRequest\n
+ * CSELR C3S LL_DMA_GetPeriphRequest\n
+ * CSELR C4S LL_DMA_GetPeriphRequest\n
+ * CSELR C5S LL_DMA_GetPeriphRequest\n
+ * CSELR C6S LL_DMA_GetPeriphRequest\n
+ * CSELR C7S LL_DMA_GetPeriphRequest
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_REQUEST_0
+ * @arg @ref LL_DMA_REQUEST_1
+ * @arg @ref LL_DMA_REQUEST_2
+ * @arg @ref LL_DMA_REQUEST_3
+ * @arg @ref LL_DMA_REQUEST_4
+ * @arg @ref LL_DMA_REQUEST_5
+ * @arg @ref LL_DMA_REQUEST_6
+ * @arg @ref LL_DMA_REQUEST_7
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
+ DMA_CSELR_C1S << ((Channel) * 4U)) >> DMA_POSITION_CSELR_CXS);
+}
+
+#endif /* DMAMUX1 */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Channel 1 global interrupt flag.
+ * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 2 global interrupt flag.
+ * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 3 global interrupt flag.
+ * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 4 global interrupt flag.
+ * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 5 global interrupt flag.
+ * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 6 global interrupt flag.
+ * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 7 global interrupt flag.
+ * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 1 transfer complete flag.
+ * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 2 transfer complete flag.
+ * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 3 transfer complete flag.
+ * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 4 transfer complete flag.
+ * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 5 transfer complete flag.
+ * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 6 transfer complete flag.
+ * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 7 transfer complete flag.
+ * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 1 half transfer flag.
+ * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 2 half transfer flag.
+ * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 3 half transfer flag.
+ * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 4 half transfer flag.
+ * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 5 half transfer flag.
+ * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 6 half transfer flag.
+ * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 7 half transfer flag.
+ * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 1 transfer error flag.
+ * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 2 transfer error flag.
+ * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 3 transfer error flag.
+ * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 4 transfer error flag.
+ * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 5 transfer error flag.
+ * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 6 transfer error flag.
+ * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Channel 7 transfer error flag.
+ * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
+{
+ return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear Channel 1 global interrupt flag.
+ * @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
+ LL_DMA_ClearFlag_TE1. bug 2.4.1/2.5.1 in Product Errata Sheet.
+ * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
+}
+
+/**
+ * @brief Clear Channel 2 global interrupt flag.
+ * @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
+ LL_DMA_ClearFlag_TE2. bug id 2.4.1/2.5.1 in Product Errata Sheet.
+ * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
+}
+
+/**
+ * @brief Clear Channel 3 global interrupt flag.
+ * @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
+ LL_DMA_ClearFlag_TE3. bug id 2.4.1/2.5.1 in Product Errata Sheet.
+ * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
+}
+
+/**
+ * @brief Clear Channel 4 global interrupt flag.
+ * @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
+ LL_DMA_ClearFlag_TE4. bug id 2.4.1/2.5.1 in Product Errata Sheet.
+ * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
+}
+
+/**
+ * @brief Clear Channel 5 global interrupt flag.
+ * @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
+ LL_DMA_ClearFlag_TE5. bug id 2.4.1/2.5.1 in Product Errata Sheet.
+ * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
+}
+
+/**
+ * @brief Clear Channel 6 global interrupt flag.
+ * @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
+ LL_DMA_ClearFlag_TE6. bug id 2.4.1/2.5.1 in Product Errata Sheet.
+ * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
+}
+
+/**
+ * @brief Clear Channel 7 global interrupt flag.
+ * @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
+ LL_DMA_ClearFlag_TE7. bug id 2.4.1/2.5.1 in Product Errata Sheet.
+ * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
+}
+
+/**
+ * @brief Clear Channel 1 transfer complete flag.
+ * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
+}
+
+/**
+ * @brief Clear Channel 2 transfer complete flag.
+ * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
+}
+
+/**
+ * @brief Clear Channel 3 transfer complete flag.
+ * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
+}
+
+/**
+ * @brief Clear Channel 4 transfer complete flag.
+ * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
+}
+
+/**
+ * @brief Clear Channel 5 transfer complete flag.
+ * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
+}
+
+/**
+ * @brief Clear Channel 6 transfer complete flag.
+ * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
+}
+
+/**
+ * @brief Clear Channel 7 transfer complete flag.
+ * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
+}
+
+/**
+ * @brief Clear Channel 1 half transfer flag.
+ * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
+}
+
+/**
+ * @brief Clear Channel 2 half transfer flag.
+ * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
+}
+
+/**
+ * @brief Clear Channel 3 half transfer flag.
+ * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
+}
+
+/**
+ * @brief Clear Channel 4 half transfer flag.
+ * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
+}
+
+/**
+ * @brief Clear Channel 5 half transfer flag.
+ * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
+}
+
+/**
+ * @brief Clear Channel 6 half transfer flag.
+ * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
+}
+
+/**
+ * @brief Clear Channel 7 half transfer flag.
+ * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
+}
+
+/**
+ * @brief Clear Channel 1 transfer error flag.
+ * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
+}
+
+/**
+ * @brief Clear Channel 2 transfer error flag.
+ * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
+}
+
+/**
+ * @brief Clear Channel 3 transfer error flag.
+ * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
+}
+
+/**
+ * @brief Clear Channel 4 transfer error flag.
+ * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
+}
+
+/**
+ * @brief Clear Channel 5 transfer error flag.
+ * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
+}
+
+/**
+ * @brief Clear Channel 6 transfer error flag.
+ * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
+}
+
+/**
+ * @brief Clear Channel 7 transfer error flag.
+ * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EF_IT_Management IT_Management
+ * @{
+ */
+/**
+ * @brief Enable Transfer complete interrupt.
+ * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+ * @brief Enable Half transfer interrupt.
+ * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+ * @brief Enable Transfer error interrupt.
+ * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
+}
+
+/**
+ * @brief Disable Transfer complete interrupt.
+ * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+ * @brief Disable Half transfer interrupt.
+ * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+ * @brief Disable Transfer error interrupt.
+ * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
+}
+
+/**
+ * @brief Check if Transfer complete Interrupt is enabled.
+ * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
+ DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Half transfer Interrupt is enabled.
+ * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
+ DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Transfer error Interrupt is enabled.
+ * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
+ DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
+ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L4xx_LL_DMA_H */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h
new file mode 100644
index 0000000..6de6976
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h
@@ -0,0 +1,1981 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_dmamux.h
+ * @author MCD Application Team
+ * @brief Header file of DMAMUX LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L4xx_LL_DMAMUX_H
+#define STM32L4xx_LL_DMAMUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined (DMAMUX1)
+
+/** @defgroup DMAMUX_LL DMAMUX
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
+ * @{
+ */
+/* Define used to get DMAMUX CCR register size */
+#define DMAMUX_CCR_SIZE 0x00000004UL
+
+/* Define used to get DMAMUX RGCR register size */
+#define DMAMUX_RGCR_SIZE 0x00000004UL
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
+ * @{
+ */
+/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function
+ * @{
+ */
+#define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
+#define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
+#define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
+#define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
+#define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
+#define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
+#define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
+#define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
+#define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
+#define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
+#define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
+#define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
+#define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
+#define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
+#define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function
+ * @{
+ */
+#define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
+#define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
+#define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
+#define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
+#define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
+#define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
+#define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
+#define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
+#define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
+#define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
+#define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
+#define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
+#define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
+#define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
+#define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions
+ * @{
+ */
+#define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */
+#define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request
+ * @{
+ */
+#define LL_DMAMUX_REQ_MEM2MEM 0U /*!< Memory to memory transfer */
+
+#define LL_DMAMUX_REQ_GENERATOR0 1U /*!< DMAMUX request generator 0 */
+#define LL_DMAMUX_REQ_GENERATOR1 2U /*!< DMAMUX request generator 1 */
+#define LL_DMAMUX_REQ_GENERATOR2 3U /*!< DMAMUX request generator 2 */
+#define LL_DMAMUX_REQ_GENERATOR3 4U /*!< DMAMUX request generator 3 */
+
+#define LL_DMAMUX_REQ_ADC1 5U /*!< DMAMUX ADC1 request */
+
+#if defined (ADC2)
+
+#define LL_DMAMUX_REQ_ADC2 6U /*!< DMAMUX ADC1 request */
+
+#define LL_DMAMUX_REQ_DAC1_CH1 7U /*!< DMAMUX DAC1 CH1 request */
+#define LL_DMAMUX_REQ_DAC1_CH2 8U /*!< DMAMUX DAC1 CH2 request */
+
+#define LL_DMAMUX_REQ_TIM6_UP 9U /*!< DMAMUX TIM6 UP request */
+#define LL_DMAMUX_REQ_TIM7_UP 10U /*!< DMAMUX TIM7 UP request */
+
+#define LL_DMAMUX_REQ_SPI1_RX 11U /*!< DMAMUX SPI1 RX request */
+#define LL_DMAMUX_REQ_SPI1_TX 12U /*!< DMAMUX SPI1 TX request */
+#define LL_DMAMUX_REQ_SPI2_RX 13U /*!< DMAMUX SPI2 RX request */
+#define LL_DMAMUX_REQ_SPI2_TX 14U /*!< DMAMUX SPI2 TX request */
+#define LL_DMAMUX_REQ_SPI3_RX 15U /*!< DMAMUX SPI3 RX request */
+#define LL_DMAMUX_REQ_SPI3_TX 16U /*!< DMAMUX SPI3 TX request */
+
+#define LL_DMAMUX_REQ_I2C1_RX 17U /*!< DMAMUX I2C1 RX request */
+#define LL_DMAMUX_REQ_I2C1_TX 18U /*!< DMAMUX I2C1 TX request */
+#define LL_DMAMUX_REQ_I2C2_RX 19U /*!< DMAMUX I2C2 RX request */
+#define LL_DMAMUX_REQ_I2C2_TX 20U /*!< DMAMUX I2C2 TX request */
+#define LL_DMAMUX_REQ_I2C3_RX 21U /*!< DMAMUX I2C3 RX request */
+#define LL_DMAMUX_REQ_I2C3_TX 22U /*!< DMAMUX I2C3 TX request */
+#define LL_DMAMUX_REQ_I2C4_RX 23U /*!< DMAMUX I2C4 RX request */
+#define LL_DMAMUX_REQ_I2C4_TX 24U /*!< DMAMUX I2C4 TX request */
+
+#define LL_DMAMUX_REQ_USART1_RX 25U /*!< DMAMUX USART1 RX request */
+#define LL_DMAMUX_REQ_USART1_TX 26U /*!< DMAMUX USART1 TX request */
+#define LL_DMAMUX_REQ_USART2_RX 27U /*!< DMAMUX USART2 RX request */
+#define LL_DMAMUX_REQ_USART2_TX 28U /*!< DMAMUX USART2 TX request */
+#define LL_DMAMUX_REQ_USART3_RX 29U /*!< DMAMUX USART3 RX request */
+#define LL_DMAMUX_REQ_USART3_TX 30U /*!< DMAMUX USART3 TX request */
+
+#define LL_DMAMUX_REQ_UART4_RX 31U /*!< DMAMUX UART4 RX request */
+#define LL_DMAMUX_REQ_UART4_TX 32U /*!< DMAMUX UART4 TX request */
+#define LL_DMAMUX_REQ_UART5_RX 33U /*!< DMAMUX UART5 RX request */
+#define LL_DMAMUX_REQ_UART5_TX 34U /*!< DMAMUX UART5 TX request */
+
+#define LL_DMAMUX_REQ_LPUART1_RX 35U /*!< DMAMUX LPUART1 RX request */
+#define LL_DMAMUX_REQ_LPUART1_TX 36U /*!< DMAMUX LPUART1 TX request */
+
+#define LL_DMAMUX_REQ_SAI1_A 37U /*!< DMAMUX SAI1 A request */
+#define LL_DMAMUX_REQ_SAI1_B 38U /*!< DMAMUX SAI1 B request */
+#define LL_DMAMUX_REQ_SAI2_A 39U /*!< DMAMUX SAI2 A request */
+#define LL_DMAMUX_REQ_SAI2_B 40U /*!< DMAMUX SAI2 B request */
+
+#define LL_DMAMUX_REQ_OSPI1 41U /*!< DMAMUX OCTOSPI1 request */
+#define LL_DMAMUX_REQ_OSPI2 42U /*!< DMAMUX OCTOSPI2 request */
+
+#define LL_DMAMUX_REQ_TIM1_CH1 43U /*!< DMAMUX TIM1 CH1 request */
+#define LL_DMAMUX_REQ_TIM1_CH2 44U /*!< DMAMUX TIM1 CH2 request */
+#define LL_DMAMUX_REQ_TIM1_CH3 45U /*!< DMAMUX TIM1 CH3 request */
+#define LL_DMAMUX_REQ_TIM1_CH4 46U /*!< DMAMUX TIM1 CH4 request */
+#define LL_DMAMUX_REQ_TIM1_UP 47U /*!< DMAMUX TIM1 UP request */
+#define LL_DMAMUX_REQ_TIM1_TRIG 48U /*!< DMAMUX TIM1 TRIG request */
+#define LL_DMAMUX_REQ_TIM1_COM 49U /*!< DMAMUX TIM1 COM request */
+
+#define LL_DMAMUX_REQ_TIM8_CH1 50U /*!< DMAMUX TIM8 CH1 request */
+#define LL_DMAMUX_REQ_TIM8_CH2 51U /*!< DMAMUX TIM8 CH2 request */
+#define LL_DMAMUX_REQ_TIM8_CH3 52U /*!< DMAMUX TIM8 CH3 request */
+#define LL_DMAMUX_REQ_TIM8_CH4 53U /*!< DMAMUX TIM8 CH4 request */
+#define LL_DMAMUX_REQ_TIM8_UP 54U /*!< DMAMUX TIM8 UP request */
+#define LL_DMAMUX_REQ_TIM8_TRIG 55U /*!< DMAMUX TIM8 TRIG request */
+#define LL_DMAMUX_REQ_TIM8_COM 56U /*!< DMAMUX TIM8 COM request */
+
+#define LL_DMAMUX_REQ_TIM2_CH1 57U /*!< DMAMUX TIM2 CH1 request */
+#define LL_DMAMUX_REQ_TIM2_CH2 58U /*!< DMAMUX TIM2 CH2 request */
+#define LL_DMAMUX_REQ_TIM2_CH3 59U /*!< DMAMUX TIM2 CH3 request */
+#define LL_DMAMUX_REQ_TIM2_CH4 60U /*!< DMAMUX TIM2 CH4 request */
+#define LL_DMAMUX_REQ_TIM2_UP 61U /*!< DMAMUX TIM2 UP request */
+
+#define LL_DMAMUX_REQ_TIM3_CH1 62U /*!< DMAMUX TIM3 CH1 request */
+#define LL_DMAMUX_REQ_TIM3_CH2 63U /*!< DMAMUX TIM3 CH2 request */
+#define LL_DMAMUX_REQ_TIM3_CH3 64U /*!< DMAMUX TIM3 CH3 request */
+#define LL_DMAMUX_REQ_TIM3_CH4 65U /*!< DMAMUX TIM3 CH4 request */
+#define LL_DMAMUX_REQ_TIM3_UP 66U /*!< DMAMUX TIM3 UP request */
+#define LL_DMAMUX_REQ_TIM3_TRIG 67U /*!< DMAMUX TIM3 TRIG request */
+
+#define LL_DMAMUX_REQ_TIM4_CH1 68U /*!< DMAMUX TIM4 CH1 request */
+#define LL_DMAMUX_REQ_TIM4_CH2 69U /*!< DMAMUX TIM4 CH2 request */
+#define LL_DMAMUX_REQ_TIM4_CH3 70U /*!< DMAMUX TIM4 CH3 request */
+#define LL_DMAMUX_REQ_TIM4_CH4 71U /*!< DMAMUX TIM4 CH4 request */
+#define LL_DMAMUX_REQ_TIM4_UP 72U /*!< DMAMUX TIM4 UP request */
+
+#define LL_DMAMUX_REQ_TIM5_CH1 73U /*!< DMAMUX TIM5 CH1 request */
+#define LL_DMAMUX_REQ_TIM5_CH2 74U /*!< DMAMUX TIM5 CH2 request */
+#define LL_DMAMUX_REQ_TIM5_CH3 75U /*!< DMAMUX TIM5 CH3 request */
+#define LL_DMAMUX_REQ_TIM5_CH4 76U /*!< DMAMUX TIM5 CH4 request */
+#define LL_DMAMUX_REQ_TIM5_UP 77U /*!< DMAMUX TIM5 UP request */
+#define LL_DMAMUX_REQ_TIM5_TRIG 78U /*!< DMAMUX TIM5 TRIG request */
+#define LL_DMAMUX_REQ_TIM15_CH1 79U /*!< DMAMUX TIM15 CH1 request */
+#define LL_DMAMUX_REQ_TIM15_UP 80U /*!< DMAMUX TIM15 UP request */
+#define LL_DMAMUX_REQ_TIM15_TRIG 81U /*!< DMAMUX TIM15 TRIG request */
+#define LL_DMAMUX_REQ_TIM15_COM 82U /*!< DMAMUX TIM15 COM request */
+
+#define LL_DMAMUX_REQ_TIM16_CH1 83U /*!< DMAMUX TIM16 CH1 request */
+#define LL_DMAMUX_REQ_TIM16_UP 84U /*!< DMAMUX TIM16 UP request */
+#define LL_DMAMUX_REQ_TIM17_CH1 85U /*!< DMAMUX TIM17 CH1 request */
+#define LL_DMAMUX_REQ_TIM17_UP 86U /*!< DMAMUX TIM17 UP request */
+
+#define LL_DMAMUX_REQ_DFSDM1_FLT0 87U /*!< DMAMUX DFSDM1_FLT0 request */
+#define LL_DMAMUX_REQ_DFSDM1_FLT1 88U /*!< DMAMUX DFSDM1_FLT1 request */
+#define LL_DMAMUX_REQ_DFSDM1_FLT2 89U /*!< DMAMUX DFSDM1_FLT2 request */
+#define LL_DMAMUX_REQ_DFSDM1_FLT3 90U /*!< DMAMUX DFSDM1_FLT3 request */
+
+#define LL_DMAMUX_REQ_DCMI 91U /*!< DMAMUX DCMI request */
+#define LL_DMAMUX_REQ_DCMI_PSSI 91U /*!< DMAMUX PSSI request */
+
+#define LL_DMAMUX_REQ_AES_IN 92U /*!< DMAMUX AES_IN request */
+#define LL_DMAMUX_REQ_AES_OUT 93U /*!< DMAMUX AES_OUT request */
+
+#define LL_DMAMUX_REQ_HASH_IN 94U /*!< DMAMUX HASH_IN request */
+
+#else
+
+#define LL_DMAMUX_REQ_DAC1_CH1 6U /*!< DMAMUX DAC1 CH1 request */
+#define LL_DMAMUX_REQ_DAC1_CH2 7U /*!< DMAMUX DAC1 CH2 request */
+
+#define LL_DMAMUX_REQ_TIM6_UP 8U /*!< DMAMUX TIM6 UP request */
+#define LL_DMAMUX_REQ_TIM7_UP 9U /*!< DMAMUX TIM7 UP request */
+
+#define LL_DMAMUX_REQ_SPI1_RX 10U /*!< DMAMUX SPI1 RX request */
+#define LL_DMAMUX_REQ_SPI1_TX 11U /*!< DMAMUX SPI1 TX request */
+#define LL_DMAMUX_REQ_SPI2_RX 12U /*!< DMAMUX SPI2 RX request */
+#define LL_DMAMUX_REQ_SPI2_TX 13U /*!< DMAMUX SPI2 TX request */
+#define LL_DMAMUX_REQ_SPI3_RX 14U /*!< DMAMUX SPI3 RX request */
+#define LL_DMAMUX_REQ_SPI3_TX 15U /*!< DMAMUX SPI3 TX request */
+
+#define LL_DMAMUX_REQ_I2C1_RX 16U /*!< DMAMUX I2C1 RX request */
+#define LL_DMAMUX_REQ_I2C1_TX 17U /*!< DMAMUX I2C1 TX request */
+#define LL_DMAMUX_REQ_I2C2_RX 18U /*!< DMAMUX I2C2 RX request */
+#define LL_DMAMUX_REQ_I2C2_TX 19U /*!< DMAMUX I2C2 TX request */
+#define LL_DMAMUX_REQ_I2C3_RX 20U /*!< DMAMUX I2C3 RX request */
+#define LL_DMAMUX_REQ_I2C3_TX 21U /*!< DMAMUX I2C3 TX request */
+#define LL_DMAMUX_REQ_I2C4_RX 22U /*!< DMAMUX I2C4 RX request */
+#define LL_DMAMUX_REQ_I2C4_TX 23U /*!< DMAMUX I2C4 TX request */
+
+#define LL_DMAMUX_REQ_USART1_RX 24U /*!< DMAMUX USART1 RX request */
+#define LL_DMAMUX_REQ_USART1_TX 25U /*!< DMAMUX USART1 TX request */
+#define LL_DMAMUX_REQ_USART2_RX 26U /*!< DMAMUX USART2 RX request */
+#define LL_DMAMUX_REQ_USART2_TX 27U /*!< DMAMUX USART2 TX request */
+#define LL_DMAMUX_REQ_USART3_RX 28U /*!< DMAMUX USART3 RX request */
+#define LL_DMAMUX_REQ_USART3_TX 29U /*!< DMAMUX USART3 TX request */
+
+#define LL_DMAMUX_REQ_UART4_RX 30U /*!< DMAMUX UART4 RX request */
+#define LL_DMAMUX_REQ_UART4_TX 31U /*!< DMAMUX UART4 TX request */
+#define LL_DMAMUX_REQ_UART5_RX 32U /*!< DMAMUX UART5 RX request */
+#define LL_DMAMUX_REQ_UART5_TX 33U /*!< DMAMUX UART5 TX request */
+
+#define LL_DMAMUX_REQ_LPUART1_RX 34U /*!< DMAMUX LPUART1 RX request */
+#define LL_DMAMUX_REQ_LPUART1_TX 35U /*!< DMAMUX LPUART1 TX request */
+
+#define LL_DMAMUX_REQ_SAI1_A 36U /*!< DMAMUX SAI1 A request */
+#define LL_DMAMUX_REQ_SAI1_B 37U /*!< DMAMUX SAI1 B request */
+#define LL_DMAMUX_REQ_SAI2_A 38U /*!< DMAMUX SAI2 A request */
+#define LL_DMAMUX_REQ_SAI2_B 39U /*!< DMAMUX SAI2 B request */
+
+#define LL_DMAMUX_REQ_OSPI1 40U /*!< DMAMUX OCTOSPI1 request */
+#define LL_DMAMUX_REQ_OSPI2 41U /*!< DMAMUX OCTOSPI2 request */
+
+#define LL_DMAMUX_REQ_TIM1_CH1 42U /*!< DMAMUX TIM1 CH1 request */
+#define LL_DMAMUX_REQ_TIM1_CH2 43U /*!< DMAMUX TIM1 CH2 request */
+#define LL_DMAMUX_REQ_TIM1_CH3 44U /*!< DMAMUX TIM1 CH3 request */
+#define LL_DMAMUX_REQ_TIM1_CH4 45U /*!< DMAMUX TIM1 CH4 request */
+#define LL_DMAMUX_REQ_TIM1_UP 46U /*!< DMAMUX TIM1 UP request */
+#define LL_DMAMUX_REQ_TIM1_TRIG 47U /*!< DMAMUX TIM1 TRIG request */
+#define LL_DMAMUX_REQ_TIM1_COM 48U /*!< DMAMUX TIM1 COM request */
+
+#define LL_DMAMUX_REQ_TIM8_CH1 49U /*!< DMAMUX TIM8 CH1 request */
+#define LL_DMAMUX_REQ_TIM8_CH2 50U /*!< DMAMUX TIM8 CH2 request */
+#define LL_DMAMUX_REQ_TIM8_CH3 51U /*!< DMAMUX TIM8 CH3 request */
+#define LL_DMAMUX_REQ_TIM8_CH4 52U /*!< DMAMUX TIM8 CH4 request */
+#define LL_DMAMUX_REQ_TIM8_UP 53U /*!< DMAMUX TIM8 UP request */
+#define LL_DMAMUX_REQ_TIM8_TRIG 54U /*!< DMAMUX TIM8 TRIG request */
+#define LL_DMAMUX_REQ_TIM8_COM 55U /*!< DMAMUX TIM8 COM request */
+
+#define LL_DMAMUX_REQ_TIM2_CH1 56U /*!< DMAMUX TIM2 CH1 request */
+#define LL_DMAMUX_REQ_TIM2_CH2 57U /*!< DMAMUX TIM2 CH2 request */
+#define LL_DMAMUX_REQ_TIM2_CH3 58U /*!< DMAMUX TIM2 CH3 request */
+#define LL_DMAMUX_REQ_TIM2_CH4 59U /*!< DMAMUX TIM2 CH4 request */
+#define LL_DMAMUX_REQ_TIM2_UP 60U /*!< DMAMUX TIM2 UP request */
+
+#define LL_DMAMUX_REQ_TIM3_CH1 61U /*!< DMAMUX TIM3 CH1 request */
+#define LL_DMAMUX_REQ_TIM3_CH2 62U /*!< DMAMUX TIM3 CH2 request */
+#define LL_DMAMUX_REQ_TIM3_CH3 63U /*!< DMAMUX TIM3 CH3 request */
+#define LL_DMAMUX_REQ_TIM3_CH4 64U /*!< DMAMUX TIM3 CH4 request */
+#define LL_DMAMUX_REQ_TIM3_UP 65U /*!< DMAMUX TIM3 UP request */
+#define LL_DMAMUX_REQ_TIM3_TRIG 66U /*!< DMAMUX TIM3 TRIG request */
+
+#define LL_DMAMUX_REQ_TIM4_CH1 67U /*!< DMAMUX TIM4 CH1 request */
+#define LL_DMAMUX_REQ_TIM4_CH2 68U /*!< DMAMUX TIM4 CH2 request */
+#define LL_DMAMUX_REQ_TIM4_CH3 69U /*!< DMAMUX TIM4 CH3 request */
+#define LL_DMAMUX_REQ_TIM4_CH4 70U /*!< DMAMUX TIM4 CH4 request */
+#define LL_DMAMUX_REQ_TIM4_UP 71U /*!< DMAMUX TIM4 UP request */
+
+#define LL_DMAMUX_REQ_TIM5_CH1 72U /*!< DMAMUX TIM5 CH1 request */
+#define LL_DMAMUX_REQ_TIM5_CH2 73U /*!< DMAMUX TIM5 CH2 request */
+#define LL_DMAMUX_REQ_TIM5_CH3 74U /*!< DMAMUX TIM5 CH3 request */
+#define LL_DMAMUX_REQ_TIM5_CH4 75U /*!< DMAMUX TIM5 CH4 request */
+#define LL_DMAMUX_REQ_TIM5_UP 76U /*!< DMAMUX TIM5 UP request */
+#define LL_DMAMUX_REQ_TIM5_TRIG 77U /*!< DMAMUX TIM5 TRIG request */
+#define LL_DMAMUX_REQ_TIM15_CH1 78U /*!< DMAMUX TIM15 CH1 request */
+#define LL_DMAMUX_REQ_TIM15_UP 79U /*!< DMAMUX TIM15 UP request */
+#define LL_DMAMUX_REQ_TIM15_TRIG 80U /*!< DMAMUX TIM15 TRIG request */
+#define LL_DMAMUX_REQ_TIM15_COM 81U /*!< DMAMUX TIM15 COM request */
+
+#define LL_DMAMUX_REQ_TIM16_CH1 82U /*!< DMAMUX TIM16 CH1 request */
+#define LL_DMAMUX_REQ_TIM16_UP 83U /*!< DMAMUX TIM16 UP request */
+#define LL_DMAMUX_REQ_TIM17_CH1 84U /*!< DMAMUX TIM17 CH1 request */
+#define LL_DMAMUX_REQ_TIM17_UP 85U /*!< DMAMUX TIM17 UP request */
+
+#define LL_DMAMUX_REQ_DFSDM1_FLT0 86U /*!< DMAMUX DFSDM1_FLT0 request */
+#define LL_DMAMUX_REQ_DFSDM1_FLT1 87U /*!< DMAMUX DFSDM1_FLT1 request */
+#define LL_DMAMUX_REQ_DFSDM1_FLT2 88U /*!< DMAMUX DFSDM1_FLT2 request */
+#define LL_DMAMUX_REQ_DFSDM1_FLT3 89U /*!< DMAMUX DFSDM1_FLT3 request */
+
+#define LL_DMAMUX_REQ_DCMI 90U /*!< DMAMUX DCMI request */
+
+#define LL_DMAMUX_REQ_AES_IN 91U /*!< DMAMUX AES_IN request */
+#define LL_DMAMUX_REQ_AES_OUT 92U /*!< DMAMUX AES_OUT request */
+
+#define LL_DMAMUX_REQ_HASH_IN 93U /*!< DMAMUX HASH_IN request */
+
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
+ * @{
+ */
+#define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX Channel 0 connected to DMA1 Channel 1 */
+#define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX Channel 1 connected to DMA1 Channel 2 */
+#define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX Channel 2 connected to DMA1 Channel 3 */
+#define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX Channel 3 connected to DMA1 Channel 4 */
+#define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */
+#define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */
+#define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */
+#define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX Channel 7 connected to DMA2 Channel 1 */
+#define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX Channel 8 connected to DMA2 Channel 2 */
+#define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX Channel 9 connected to DMA2 Channel 3 */
+#define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX Channel 10 connected to DMA2 Channel 4 */
+#define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 5 */
+#define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX Channel 12 connected to DMA2 Channel 6 */
+#define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX Channel 13 connected to DMA2 Channel 7 */
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
+ * @{
+ */
+#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */
+#define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */
+#define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */
+#define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
+ * @{
+ */
+#define LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U /*!< Synchronization signal from EXTI Line0 */
+#define LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0 /*!< Synchronization signal from EXTI Line1 */
+#define LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1 /*!< Synchronization signal from EXTI Line2 */
+#define LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line3 */
+#define LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2 /*!< Synchronization signal from EXTI Line4 */
+#define LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line5 */
+#define LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line6 */
+#define LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line7 */
+#define LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3 /*!< Synchronization signal from EXTI Line8 */
+#define LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line9 */
+#define LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line10 */
+#define LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line11 */
+#define LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from EXTI Line12 */
+#define LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line13 */
+#define LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line14 */
+#define LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line15 */
+#define LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4 /*!< Synchronization signal from DMAMUX channel0 Event */
+#define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel1 Event */
+#define LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DMAMUX channel2 Event */
+#define LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel3 Event */
+#define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Output */
+#define LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from LPTIM2 Output */
+#define LL_DMAMUX_SYNC_DSI_TE (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DSI Tearing Effect */
+#define LL_DMAMUX_SYNC_DSI_REFRESH_END (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DSI End of Refresh */
+#define LL_DMAMUX_SYNC_DMA2D_TX_END (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_3) /*!< Synchronization signal from DMA2D End of Transfer */
+#define LL_DMAMUX_SYNC_LTDC_LINE_IT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from LTDC Line Interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
+ * @{
+ */
+#define LL_DMAMUX_REQ_GEN_0 0x00000000U
+#define LL_DMAMUX_REQ_GEN_1 0x00000001U
+#define LL_DMAMUX_REQ_GEN_2 0x00000002U
+#define LL_DMAMUX_REQ_GEN_3 0x00000003U
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
+ * @{
+ */
+#define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */
+#define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */
+#define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */
+#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
+ * @{
+ */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U /*!< Request signal generation from EXTI Line0 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0 /*!< Request signal generation from EXTI Line1 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1 /*!< Request signal generation from EXTI Line2 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line3 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2 /*!< Request signal generation from EXTI Line4 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line5 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line6 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line7 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3 /*!< Request signal generation from EXTI Line8 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line9 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line10 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line11 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from EXTI Line12 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line13 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line14 */
+#define LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line15 */
+#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4 /*!< Request signal generation from DMAMUX channel0 Event */
+#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel1 Event */
+#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DMAMUX channel2 Event */
+#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel3 Event */
+#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Output */
+#define LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from LPTIM2 Output */
+#define LL_DMAMUX_REQ_GEN_DSI_TE (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DSI Tearing Effect */
+#define LL_DMAMUX_REQ_GEN_DSI_REFRESH_END (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DSI End of Refresh */
+#define LL_DMAMUX_REQ_GEN_DMA2D_TX_END (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_3) /*!< Request signal generation from DMA2D End of Transfer */
+#define LL_DMAMUX_REQ_GEN_LTDC_LINE_IT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from LTDC Line Interrupt */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
+ * @{
+ */
+
+/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
+ * @{
+ */
+/**
+ * @brief Write a value in DMAMUX register
+ * @param __INSTANCE__ DMAMUX Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in DMAMUX register
+ * @param __INSTANCE__ DMAMUX Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
+ * @{
+ */
+
+/** @defgroup DMAMUX_LL_EF_Configuration Configuration
+ * @{
+ */
+/**
+ * @brief Set DMAMUX request ID for DMAMUX Channel x.
+ * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
+ * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
+ * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @param Request This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_MEM2MEM
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR0
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR1
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR2
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR3
+ * @arg @ref LL_DMAMUX_REQ_ADC1
+ * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
+ * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM6_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM7_UP
+ * @arg @ref LL_DMAMUX_REQ_SPI1_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI1_TX
+ * @arg @ref LL_DMAMUX_REQ_SPI2_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI2_TX
+ * @arg @ref LL_DMAMUX_REQ_SPI3_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI3_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C1_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C1_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C2_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C2_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C3_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C3_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C4_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C4_TX
+ * @arg @ref LL_DMAMUX_REQ_USART1_RX
+ * @arg @ref LL_DMAMUX_REQ_USART1_TX
+ * @arg @ref LL_DMAMUX_REQ_USART2_RX
+ * @arg @ref LL_DMAMUX_REQ_USART2_TX
+ * @arg @ref LL_DMAMUX_REQ_USART3_RX
+ * @arg @ref LL_DMAMUX_REQ_USART3_TX
+ * @arg @ref LL_DMAMUX_REQ_UART4_RX
+ * @arg @ref LL_DMAMUX_REQ_UART4_TX
+ * @arg @ref LL_DMAMUX_REQ_UART5_RX
+ * @arg @ref LL_DMAMUX_REQ_UART5_TX
+ * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
+ * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
+ * @arg @ref LL_DMAMUX_REQ_SAI1_A
+ * @arg @ref LL_DMAMUX_REQ_SAI1_B
+ * @arg @ref LL_DMAMUX_REQ_SAI2_A
+ * @arg @ref LL_DMAMUX_REQ_SAI2_B
+ * @arg @ref LL_DMAMUX_REQ_OSPI1
+ * @arg @ref LL_DMAMUX_REQ_OSPI2
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM1_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM1_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM8_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM8_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM2_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM3_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM4_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM5_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM15_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM15_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM16_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM17_UP
+ * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0
+ * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1
+ * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2
+ * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3
+ * @arg @ref LL_DMAMUX_REQ_DCMI
+ * @arg @ref LL_DMAMUX_REQ_AES_IN
+ * @arg @ref LL_DMAMUX_REQ_AES_OUT
+ * @arg @ref LL_DMAMUX_REQ_HASH_IN
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
+{
+ (void)(DMAMUXx);
+ MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
+}
+
+/**
+ * @brief Get DMAMUX request ID for DMAMUX Channel x.
+ * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
+ * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
+ * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_MEM2MEM
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR0
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR1
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR2
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR3
+ * @arg @ref LL_DMAMUX_REQ_ADC1
+ * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
+ * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM6_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM7_UP
+ * @arg @ref LL_DMAMUX_REQ_SPI1_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI1_TX
+ * @arg @ref LL_DMAMUX_REQ_SPI2_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI2_TX
+ * @arg @ref LL_DMAMUX_REQ_SPI3_RX
+ * @arg @ref LL_DMAMUX_REQ_SPI3_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C1_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C1_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C2_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C2_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C3_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C3_TX
+ * @arg @ref LL_DMAMUX_REQ_I2C4_RX
+ * @arg @ref LL_DMAMUX_REQ_I2C4_TX
+ * @arg @ref LL_DMAMUX_REQ_USART1_RX
+ * @arg @ref LL_DMAMUX_REQ_USART1_TX
+ * @arg @ref LL_DMAMUX_REQ_USART2_RX
+ * @arg @ref LL_DMAMUX_REQ_USART2_TX
+ * @arg @ref LL_DMAMUX_REQ_USART3_RX
+ * @arg @ref LL_DMAMUX_REQ_USART3_TX
+ * @arg @ref LL_DMAMUX_REQ_UART4_RX
+ * @arg @ref LL_DMAMUX_REQ_UART4_TX
+ * @arg @ref LL_DMAMUX_REQ_UART5_RX
+ * @arg @ref LL_DMAMUX_REQ_UART5_TX
+ * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
+ * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
+ * @arg @ref LL_DMAMUX_REQ_SAI1_A
+ * @arg @ref LL_DMAMUX_REQ_SAI1_B
+ * @arg @ref LL_DMAMUX_REQ_SAI2_A
+ * @arg @ref LL_DMAMUX_REQ_SAI2_B
+ * @arg @ref LL_DMAMUX_REQ_OSPI1
+ * @arg @ref LL_DMAMUX_REQ_OSPI2
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM1_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM1_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM8_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM8_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM2_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM3_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM4_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH2
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH3
+ * @arg @ref LL_DMAMUX_REQ_TIM5_CH4
+ * @arg @ref LL_DMAMUX_REQ_TIM5_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM15_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
+ * @arg @ref LL_DMAMUX_REQ_TIM15_COM
+ * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM16_UP
+ * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
+ * @arg @ref LL_DMAMUX_REQ_TIM17_UP
+ * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0
+ * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1
+ * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2
+ * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3
+ * @arg @ref LL_DMAMUX_REQ_DCMI
+ * @arg @ref LL_DMAMUX_REQ_AES_IN
+ * @arg @ref LL_DMAMUX_REQ_AES_OUT
+ * @arg @ref LL_DMAMUX_REQ_HASH_IN
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+ (void)(DMAMUXx);
+ return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID));
+}
+
+/**
+ * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
+ * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
+{
+ (void)(DMAMUXx);
+ MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos));
+}
+
+/**
+ * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
+ * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @retval Between Min_Data = 1 and Max_Data = 32
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+ (void)(DMAMUXx);
+ return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
+}
+
+/**
+ * @brief Set the polarity of the signal on which the DMA request is synchronized.
+ * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
+ * @arg @ref LL_DMAMUX_SYNC_POL_RISING
+ * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
+ * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
+{
+ (void)(DMAMUXx);
+ MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity);
+}
+
+/**
+ * @brief Get the polarity of the signal on which the DMA request is synchronized.
+ * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
+ * @arg @ref LL_DMAMUX_SYNC_POL_RISING
+ * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
+ * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+ (void)(DMAMUXx);
+ return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL));
+}
+
+/**
+ * @brief Enable the Event Generation on DMAMUX channel x.
+ * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+ (void)(DMAMUXx);
+ SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
+}
+
+/**
+ * @brief Disable the Event Generation on DMAMUX channel x.
+ * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+ (void)(DMAMUXx);
+ CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
+}
+
+/**
+ * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled.
+ * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE))? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the synchronization mode.
+ * @rmtoll CxCR SE LL_DMAMUX_EnableSync
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+ (void)(DMAMUXx);
+ SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
+}
+
+/**
+ * @brief Disable the synchronization mode.
+ * @rmtoll CxCR SE LL_DMAMUX_DisableSync
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+ (void)(DMAMUXx);
+ CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
+}
+
+/**
+ * @brief Check if the synchronization mode is enabled or disabled.
+ * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE))? 1UL : 0UL);
+}
+
+/**
+ * @brief Set DMAMUX synchronization ID on DMAMUX Channel x.
+ * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @param SyncID This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
+ * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
+ * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
+ * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
+ * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
+ * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
+ * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT
+ * @arg @ref LL_DMAMUX_SYNC_DSI_TE
+ * @arg @ref LL_DMAMUX_SYNC_DSI_REFRESH_END
+ * @arg @ref LL_DMAMUX_SYNC_DMA2D_TX_END
+ * @arg @ref LL_DMAMUX_SYNC_LTDC_LINE_IT
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
+{
+ (void)(DMAMUXx);
+ MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
+}
+
+/**
+ * @brief Get DMAMUX synchronization ID on DMAMUX Channel x.
+ * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
+ * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
+ * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
+ * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
+ * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
+ * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
+ * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
+ * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT
+ * @arg @ref LL_DMAMUX_SYNC_DSI_TE
+ * @arg @ref LL_DMAMUX_SYNC_DSI_REFRESH_END
+ * @arg @ref LL_DMAMUX_SYNC_DMA2D_TX_END
+ * @arg @ref LL_DMAMUX_SYNC_LTDC_LINE_IT
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+ (void)(DMAMUXx);
+ return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID));
+}
+
+/**
+ * @brief Enable the Request Generator.
+ * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+ (void)(DMAMUXx);
+ SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
+}
+
+/**
+ * @brief Disable the Request Generator.
+ * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+ (void)(DMAMUXx);
+ CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
+}
+
+/**
+ * @brief Check if the Request Generator is enabled or disabled.
+ * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE))? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the polarity of the signal on which the DMA request is generated.
+ * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
+ * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
+ * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
+ * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
+{
+ (void)(DMAMUXx);
+ MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
+}
+
+/**
+ * @brief Get the polarity of the signal on which the DMA request is generated.
+ * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
+ * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
+ * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
+ * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+ (void)(DMAMUXx);
+ return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL));
+}
+
+/**
+ * @brief Set the number of DMA request that will be autorized after a generation event.
+ * @note This field can only be written when Generator is disabled.
+ * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
+{
+ (void)(DMAMUXx);
+ MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
+}
+
+/**
+ * @brief Get the number of DMA request that will be autorized after a generation event.
+ * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @retval Between Min_Data = 1 and Max_Data = 32
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+ (void)(DMAMUXx);
+ return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
+}
+
+/**
+ * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
+ * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @param RequestSignalID This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
+ * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
+ * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
+ * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
+ * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
+ * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
+ * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT
+ * @arg @ref LL_DMAMUX_REQ_GEN_DSI_TE
+ * @arg @ref LL_DMAMUX_REQ_GEN_DSI_REFRESH_END
+ * @arg @ref LL_DMAMUX_REQ_GEN_DMA2D_TX_END
+ * @arg @ref LL_DMAMUX_REQ_GEN_LTDC_LINE_IT
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
+{
+ (void)(DMAMUXx);
+ MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
+}
+
+/**
+ * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
+ * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
+ * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
+ * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
+ * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
+ * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
+ * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
+ * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
+ * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT
+ * @arg @ref LL_DMAMUX_REQ_GEN_DSI_TE
+ * @arg @ref LL_DMAMUX_REQ_GEN_DSI_REFRESH_END
+ * @arg @ref LL_DMAMUX_REQ_GEN_DMA2D_TX_END
+ * @arg @ref LL_DMAMUX_REQ_GEN_LTDC_LINE_IT
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+ (void)(DMAMUXx);
+ return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 0.
+ * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 1.
+ * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 2.
+ * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 3.
+ * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 4.
+ * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 5.
+ * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 6.
+ * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 7.
+ * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 8.
+ * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 9.
+ * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 10.
+ * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 11.
+ * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 12.
+ * @rmtoll CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Synchronization Event Overrun Flag Channel 13.
+ * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Request Generator 0 Trigger Event Overrun Flag.
+ * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Request Generator 1 Trigger Event Overrun Flag.
+ * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Request Generator 2 Trigger Event Overrun Flag.
+ * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Request Generator 3 Trigger Event Overrun Flag.
+ * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 0.
+ * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef * DMAMUXx)
+{
+ (void)(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 1.
+ * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 2.
+ * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 3.
+ * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 4.
+ * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 5.
+ * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 6.
+ * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 7.
+ * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 8.
+ * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 9.
+ * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 10.
+ * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 11.
+ * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 12.
+ * @rmtoll CFR CSOF12 LL_DMAMUX_ClearFlag_SO12
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF12);
+}
+
+/**
+ * @brief Clear Synchronization Event Overrun Flag Channel 13.
+ * @rmtoll CFR CSOF13 LL_DMAMUX_ClearFlag_SO13
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF13);
+}
+
+/**
+ * @brief Clear Request Generator 0 Trigger Event Overrun Flag.
+ * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0);
+}
+
+/**
+ * @brief Clear Request Generator 1 Trigger Event Overrun Flag.
+ * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1);
+}
+
+/**
+ * @brief Clear Request Generator 2 Trigger Event Overrun Flag.
+ * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2);
+}
+
+/**
+ * @brief Clear Request Generator 3 Trigger Event Overrun Flag.
+ * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3
+ * @param DMAMUXx DMAMUXx DMAMUXx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+ (void)(DMAMUXx);
+ SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
+ * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+ (void)(DMAMUXx);
+ SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
+}
+
+/**
+ * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
+ * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+ (void)(DMAMUXx);
+ CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
+}
+
+/**
+ * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
+ * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO
+ * @param DMAMUXx DMAMUXx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_CHANNEL_0
+ * @arg @ref LL_DMAMUX_CHANNEL_1
+ * @arg @ref LL_DMAMUX_CHANNEL_2
+ * @arg @ref LL_DMAMUX_CHANNEL_3
+ * @arg @ref LL_DMAMUX_CHANNEL_4
+ * @arg @ref LL_DMAMUX_CHANNEL_5
+ * @arg @ref LL_DMAMUX_CHANNEL_6
+ * @arg @ref LL_DMAMUX_CHANNEL_7
+ * @arg @ref LL_DMAMUX_CHANNEL_8
+ * @arg @ref LL_DMAMUX_CHANNEL_9
+ * @arg @ref LL_DMAMUX_CHANNEL_10
+ * @arg @ref LL_DMAMUX_CHANNEL_11
+ * @arg @ref LL_DMAMUX_CHANNEL_12
+ * @arg @ref LL_DMAMUX_CHANNEL_13
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+ (void)(DMAMUXx);
+ return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE))? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
+ * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+ (void)(DMAMUXx);
+ SET_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE);
+}
+
+/**
+ * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
+ * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+ (void)(DMAMUXx);
+ CLEAR_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE);
+}
+
+/**
+ * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
+ * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO
+ * @param DMAMUXx DMAMUXx Instance
+ * @param RequestGenChannel This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_GEN_0
+ * @arg @ref LL_DMAMUX_REQ_GEN_1
+ * @arg @ref LL_DMAMUX_REQ_GEN_2
+ * @arg @ref LL_DMAMUX_REQ_GEN_3
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+ (void)(DMAMUXx);
+ return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE))? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DMAMUX1 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L4xx_LL_DMAMUX_H */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h
new file mode 100644
index 0000000..a1ee112
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h
@@ -0,0 +1,1359 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_exti.h
+ * @author MCD Application Team
+ * @brief Header file of EXTI LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L4xx_LL_EXTI_H
+#define STM32L4xx_LL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
+ * @{
+ */
+typedef struct
+{
+
+ uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
+ This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+ uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
+ This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+ FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
+
+ uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTI_LL_EC_MODE. */
+
+ uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
+} LL_EXTI_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
+ * @{
+ */
+
+/** @defgroup EXTI_LL_EC_LINE LINE
+ * @{
+ */
+#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */
+#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */
+#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */
+#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */
+#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */
+#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */
+#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */
+#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */
+#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */
+#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */
+#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */
+#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */
+#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */
+#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */
+#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */
+#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */
+#if defined(EXTI_IMR1_IM16)
+#define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */
+#endif
+#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */
+#if defined(EXTI_IMR1_IM18)
+#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */
+#endif
+#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */
+#if defined(EXTI_IMR1_IM20)
+#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */
+#endif
+#if defined(EXTI_IMR1_IM21)
+#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */
+#endif
+#if defined(EXTI_IMR1_IM22)
+#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */
+#endif
+#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */
+#if defined(EXTI_IMR1_IM24)
+#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */
+#endif
+#if defined(EXTI_IMR1_IM25)
+#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */
+#endif
+#if defined(EXTI_IMR1_IM26)
+#define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */
+#endif
+#if defined(EXTI_IMR1_IM27)
+#define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */
+#endif
+#if defined(EXTI_IMR1_IM28)
+#define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */
+#endif
+#if defined(EXTI_IMR1_IM29)
+#define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */
+#endif
+#if defined(EXTI_IMR1_IM30)
+#define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */
+#endif
+#if defined(EXTI_IMR1_IM31)
+#define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */
+#endif
+#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM /*!< All Extended line not reserved*/
+
+#define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */
+#if defined(EXTI_IMR2_IM33)
+#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */
+#endif
+#if defined(EXTI_IMR2_IM34)
+#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */
+#endif
+#if defined(EXTI_IMR2_IM35)
+#define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */
+#endif
+#if defined(EXTI_IMR2_IM36)
+#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */
+#endif
+#if defined(EXTI_IMR2_IM37)
+#define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */
+#endif
+#if defined(EXTI_IMR2_IM38)
+#define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */
+#endif
+#if defined(EXTI_IMR2_IM39)
+#define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */
+#endif
+#if defined(EXTI_IMR2_IM40)
+#define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */
+#endif
+#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/
+
+
+#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */
+
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/**
+ * @}
+ */
+
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup EXTI_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */
+#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */
+#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
+ * @{
+ */
+#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */
+#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */
+#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */
+#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
+
+/**
+ * @}
+ */
+
+
+#endif /*USE_FULL_LL_DRIVER*/
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
+ * @{
+ */
+
+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in EXTI register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in EXTI register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
+ * @{
+ */
+/** @defgroup EXTI_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->IMR1, ExtiLine);
+}
+/**
+ * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63
+ * @note The reset value for the direct lines (lines from 32 to 34, line
+ * 39) is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_32
+ * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_34(*)
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39(*)
+ * @arg @ref LL_EXTI_LINE_40(*)
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @note (*): Available in some devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->IMR2, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->IMR1, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63
+ * @note The reset value for the direct lines (lines from 32 to 34, line
+ * 39) is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_32
+ * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_34(*)
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39(*)
+ * @arg @ref LL_EXTI_LINE_40(*)
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @note (*): Available in some devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->IMR2, ExtiLine);
+}
+
+/**
+ * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+ return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
+ * @note The reset value for the direct lines (lines from 32 to 34, line
+ * 39) is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_32
+ * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_34(*)
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39(*)
+ * @arg @ref LL_EXTI_LINE_40(*)
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @note (*): Available in some devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
+{
+ return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Event_Management Event_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Event request for Lines in range 0 to 31
+ * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->EMR1, ExtiLine);
+
+}
+
+/**
+ * @brief Enable ExtiLine Event request for Lines in range 32 to 63
+ * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32
+ * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_34(*)
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39(*)
+ * @arg @ref LL_EXTI_LINE_40(*)
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @note (*): Available in some devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->EMR2, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Event request for Lines in range 0 to 31
+ * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->EMR1, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Event request for Lines in range 32 to 63
+ * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32
+ * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_34(*)
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39(*)
+ * @arg @ref LL_EXTI_LINE_40(*)
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @note (*): Available in some devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->EMR2, ExtiLine);
+}
+
+/**
+ * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
+ * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+ return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+
+}
+
+/**
+ * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
+ * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32
+ * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_34(*)
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39(*)
+ * @arg @ref LL_EXTI_LINE_40(*)
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @note (*): Available in some devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
+{
+ return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->RTSR1, ExtiLine);
+
+}
+
+/**
+ * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->RTSR2, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->RTSR1, ExtiLine);
+
+}
+
+/**
+ * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->RTSR2, ExtiLine);
+}
+
+/**
+ * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
+ * @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
+{
+ return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63
+ * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
+{
+ return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->FTSR1, ExtiLine);
+}
+
+/**
+ * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a Falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->FTSR2, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a Falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for the same interrupt line.
+ * In this case, both generate a trigger condition.
+ * @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->FTSR1, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a Falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for the same interrupt line.
+ * In this case, both generate a trigger condition.
+ * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->FTSR2, ExtiLine);
+}
+
+/**
+ * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
+ * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
+{
+ return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63
+ * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
+{
+ return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
+ * @{
+ */
+
+/**
+ * @brief Generate a software Interrupt Event for Lines in range 0 to 31
+ * @note If the interrupt is enabled on this line in the EXTI_IMR1, writing a 1 to
+ * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1
+ * resulting in an interrupt request generation.
+ * This bit is cleared by clearing the corresponding bit in the EXTI_PR1
+ * register (by writing a 1 into the bit)
+ * @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->SWIER1, ExtiLine);
+}
+
+/**
+ * @brief Generate a software Interrupt Event for Lines in range 32 to 63
+ * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to
+ * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
+ * resulting in an interrupt request generation.
+ * This bit is cleared by clearing the corresponding bit in the EXTI_PR2
+ * register (by writing a 1 into the bit)
+ * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->SWIER2, ExtiLine);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
+ * @{
+ */
+
+/**
+ * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR1 PIFx LL_EXTI_IsActiveFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
+{
+ return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR2 PIFx LL_EXTI_IsActiveFlag_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
+{
+ return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Read ExtLine Combination Flag for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR1 PIFx LL_EXTI_ReadFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval @note This bit is set when the selected edge event arrives on the interrupt
+ */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
+{
+ return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine));
+}
+
+/**
+ * @brief Read ExtLine Combination Flag for Lines in range 32 to 63
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR2 PIFx LL_EXTI_ReadFlag_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval @note This bit is set when the selected edge event arrives on the interrupt
+ */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
+{
+ return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));
+}
+
+/**
+ * @brief Clear ExtLine Flags for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR1 PIFx LL_EXTI_ClearFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
+{
+ WRITE_REG(EXTI->PR1, ExtiLine);
+}
+
+/**
+ * @brief Clear ExtLine Flags for Lines in range 32 to 63
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR2 PIFx LL_EXTI_ClearFlag_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
+{
+ WRITE_REG(EXTI->PR2, ExtiLine);
+}
+
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+uint32_t LL_EXTI_DeInit(void);
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* EXTI */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L4xx_LL_EXTI_H */
+
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h
new file mode 100644
index 0000000..72bb307
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h
@@ -0,0 +1,1056 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_gpio.h
+ * @author MCD Application Team
+ * @brief Header file of GPIO LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L4xx_LL_GPIO_H
+#define STM32L4xx_LL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI)
+
+/** @defgroup GPIO_LL GPIO
+ * @{
+ */
+/** MISRA C:2012 deviation rule has been granted for following rules:
+ * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
+ * which may be out of array bounds [..,UNKNOWN] in following APIs:
+ * LL_GPIO_GetAFPin_0_7
+ * LL_GPIO_SetAFPin_0_7
+ * LL_GPIO_SetAFPin_8_15
+ * LL_GPIO_GetAFPin_8_15
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL GPIO Init Structure definition
+ */
+typedef struct
+{
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_LL_EC_PIN */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_MODE.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
+
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_SPEED.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
+
+ uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
+
+ uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_PULL.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
+
+ uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_AF.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
+} LL_GPIO_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EC_PIN PIN
+ * @{
+ */
+#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */
+#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */
+#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */
+#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */
+#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */
+#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */
+#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */
+#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */
+#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */
+#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */
+#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */
+#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */
+#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */
+#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */
+#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */
+#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */
+#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \
+ GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \
+ GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \
+ GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
+ GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
+ GPIO_BSRR_BS15) /*!< Select all pins */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */
+#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */
+#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */
+#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_OUTPUT Output Type
+ * @{
+ */
+#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_SPEED Output Speed
+ * @{
+ */
+#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */
+#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
+#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */
+#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */
+/**
+ * @}
+ */
+#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW
+#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM
+#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH
+#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH
+
+/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
+ * @{
+ */
+#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */
+#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
+#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_AF Alternate Function
+ * @{
+ */
+#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */
+#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */
+#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */
+#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */
+#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */
+#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */
+#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */
+#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */
+#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */
+#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */
+#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */
+#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */
+#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */
+#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */
+#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */
+#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in GPIO register
+ * @param __INSTANCE__ GPIO Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in GPIO register
+ * @param __INSTANCE__ GPIO Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
+ * @{
+ */
+
+/**
+ * @brief Configure gpio mode for a dedicated pin on dedicated port.
+ * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll MODER MODEy LL_GPIO_SetPinMode
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_MODE_INPUT
+ * @arg @ref LL_GPIO_MODE_OUTPUT
+ * @arg @ref LL_GPIO_MODE_ALTERNATE
+ * @arg @ref LL_GPIO_MODE_ANALOG
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+{
+ MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+ * @brief Return gpio mode for a dedicated pin on dedicated port.
+ * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll MODER MODEy LL_GPIO_GetPinMode
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_MODE_INPUT
+ * @arg @ref LL_GPIO_MODE_OUTPUT
+ * @arg @ref LL_GPIO_MODE_ALTERNATE
+ * @arg @ref LL_GPIO_MODE_ANALOG
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->MODER,
+ (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+ * @brief Configure gpio output type for several pins on dedicated port.
+ * @note Output type as to be set when gpio pin is in output or
+ * alternate modes. Possible type are Push-pull or Open-drain.
+ * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @param OutputType This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+ * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
+{
+ MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+}
+
+/**
+ * @brief Return gpio output type for several pins on dedicated port.
+ * @note Output type as to be set when gpio pin is in output or
+ * alternate modes. Possible type are Push-pull or Open-drain.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+ * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
+}
+
+/**
+ * @brief Configure gpio speed for a dedicated pin on dedicated port.
+ * @note I/O speed can be Low, Medium, Fast or High speed.
+ * @note Warning: only one pin can be passed as parameter.
+ * @note Refer to datasheet for frequency specifications and the power
+ * supply and load conditions for each speed.
+ * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Speed This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_SPEED_FREQ_LOW
+ * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+ * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+ * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
+{
+ MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U)),
+ (Speed << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+ * @brief Return gpio speed for a dedicated pin on dedicated port.
+ * @note I/O speed can be Low, Medium, Fast or High speed.
+ * @note Warning: only one pin can be passed as parameter.
+ * @note Refer to datasheet for frequency specifications and the power
+ * supply and load conditions for each speed.
+ * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_SPEED_FREQ_LOW
+ * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+ * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+ * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
+ (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+ * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Pull This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PULL_NO
+ * @arg @ref LL_GPIO_PULL_UP
+ * @arg @ref LL_GPIO_PULL_DOWN
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
+{
+ MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+ * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_PULL_NO
+ * @arg @ref LL_GPIO_PULL_UP
+ * @arg @ref LL_GPIO_PULL_DOWN
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->PUPDR,
+ (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+ * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+ * @note Possible values are from AF0 to AF15 depending on target.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @param Alternate This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+ MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
+ (Alternate << (POSITION_VAL(Pin) * 4U)));
+}
+
+/**
+ * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+ * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->AFR[0],
+ (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
+}
+
+/**
+ * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+ * @note Possible values are from AF0 to AF15 depending on target.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Alternate This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+ MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
+ (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
+}
+
+/**
+ * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+ * @note Possible values are from AF0 to AF15 depending on target.
+ * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->AFR[1],
+ (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
+}
+
+#if defined(GPIO_ASCR_ASC0)
+/**
+ * @brief Connect analog switch to ADC input of several pins for a dedicated port.
+ * @note This bit must be set prior to the ADC conversion.
+ * Only the IO which connected to the ADC input are effective.
+ * Other IO must be kept reset value
+ * @rmtoll ASCR ASCy LL_GPIO_EnablePinAnalogControl
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_EnablePinAnalogControl(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ SET_BIT(GPIOx->ASCR, PinMask);
+}
+
+/**
+ * @brief Disconnect analog switch to ADC input of several pins for a dedicated port.
+ * @rmtoll ASCR ASCy LL_GPIO_DisablePinAnalogControl
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_DisablePinAnalogControl(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ CLEAR_BIT(GPIOx->ASCR, PinMask);
+}
+#endif /* GPIO_ASCR_ASC0 */
+
+/**
+ * @brief Lock configuration of several pins for a dedicated port.
+ * @note When the lock sequence has been applied on a port bit, the
+ * value of this port bit can no longer be modified until the
+ * next reset.
+ * @note Each lock bit freezes a specific configuration register
+ * (control and alternate function registers).
+ * @rmtoll LCKR LCKK LL_GPIO_LockPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ __IO uint32_t temp;
+ WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+ WRITE_REG(GPIOx->LCKR, PinMask);
+ WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+ /* Read LCKK register. This read is mandatory to complete key lock sequence */
+ temp = READ_REG(GPIOx->LCKR);
+ (void) temp;
+}
+
+/**
+ * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
+ * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
+ * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
+ * @param GPIOx GPIO Port
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
+{
+ return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EF_Data_Access Data Access
+ * @{
+ */
+
+/**
+ * @brief Return full input data register value for a dedicated port.
+ * @rmtoll IDR IDy LL_GPIO_ReadInputPort
+ * @param GPIOx GPIO Port
+ * @retval Input data register value of port
+ */
+__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
+{
+ return (uint32_t)(READ_REG(GPIOx->IDR));
+}
+
+/**
+ * @brief Return if input data level for several pins of dedicated port is high or low.
+ * @rmtoll IDR IDy LL_GPIO_IsInputPinSet
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Write output data register for the port.
+ * @rmtoll ODR ODy LL_GPIO_WriteOutputPort
+ * @param GPIOx GPIO Port
+ * @param PortValue Level value for each pin of the port
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
+{
+ WRITE_REG(GPIOx->ODR, PortValue);
+}
+
+/**
+ * @brief Return full output data register value for a dedicated port.
+ * @rmtoll ODR ODy LL_GPIO_ReadOutputPort
+ * @param GPIOx GPIO Port
+ * @retval Output data register value of port
+ */
+__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
+{
+ return (uint32_t)(READ_REG(GPIOx->ODR));
+}
+
+/**
+ * @brief Return if input data level for several pins of dedicated port is high or low.
+ * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set several pins to high level on dedicated gpio port.
+ * @rmtoll BSRR BSy LL_GPIO_SetOutputPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ WRITE_REG(GPIOx->BSRR, PinMask);
+}
+
+/**
+ * @brief Set several pins to low level on dedicated gpio port.
+ * @rmtoll BRR BRy LL_GPIO_ResetOutputPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ WRITE_REG(GPIOx->BRR, PinMask);
+}
+
+/**
+ * @brief Toggle data value for several pin of dedicated port.
+ * @rmtoll ODR ODy LL_GPIO_TogglePin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ uint32_t odr = READ_REG(GPIOx->ODR);
+ WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L4xx_LL_GPIO_H */
+
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h
new file mode 100644
index 0000000..4660f30
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h
@@ -0,0 +1,1675 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_pwr.h
+ * @author MCD Application Team
+ * @brief Header file of PWR LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L4xx_LL_PWR_H
+#define STM32L4xx_LL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
+ * @{
+ */
+
+/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_PWR_WriteReg function
+ * @{
+ */
+#define LL_PWR_SCR_CSBF PWR_SCR_CSBF
+#define LL_PWR_SCR_CWUF PWR_SCR_CWUF
+#define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
+#define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
+#define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
+#define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
+#define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_PWR_ReadReg function
+ * @{
+ */
+#define LL_PWR_SR1_WUFI PWR_SR1_WUFI
+#if defined(PWR_SR1_EXT_SMPS_RDY)
+#define LL_PWR_SR1_EXT_SMPS_RDY PWR_SR1_EXT_SMPS_RDY
+#endif /* PWR_SR1_EXT_SMPS_RDY */
+#define LL_PWR_SR1_SBF PWR_SR1_SBF
+#define LL_PWR_SR1_WUF5 PWR_SR1_WUF5
+#define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
+#define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
+#define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
+#define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
+#if defined(PWR_SR2_PVMO4)
+#define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4
+#endif /* PWR_SR2_PVMO4 */
+#if defined(PWR_SR2_PVMO3)
+#define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
+#endif /* PWR_SR2_PVMO3 */
+#if defined(PWR_SR2_PVMO2)
+#define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2
+#endif /* PWR_SR2_PVMO2 */
+#if defined(PWR_SR2_PVMO1)
+#define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
+#endif /* PWR_SR2_PVMO1 */
+#define LL_PWR_SR2_PVDO PWR_SR2_PVDO
+#define LL_PWR_SR2_VOSF PWR_SR2_VOSF
+#define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
+#define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
+ * @{
+ */
+#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0)
+#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
+ * @{
+ */
+#define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0)
+#define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1)
+#define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_STOP2)
+#define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY)
+#define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring
+ * @{
+ */
+#if defined(PWR_CR2_PVME1)
+#define LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */
+#endif
+#if defined(PWR_CR2_PVME2)
+#define LL_PWR_PVM_VDDIO2_0_9V (PWR_CR2_PVME2) /* Monitoring VDDIO2 vs. 0.9V */
+#endif
+#if defined(PWR_CR2_PVME3)
+#define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */
+#endif
+#if defined(PWR_CR2_PVME4)
+#define LL_PWR_PVM_VDDA_2_2V (PWR_CR2_PVME4) /* Monitoring VDDA vs. 2.2V */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
+ * @{
+ */
+#define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */
+#define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */
+#define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */
+#define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */
+#define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */
+#define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */
+#define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */
+#define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_WAKEUP WAKEUP
+ * @{
+ */
+#define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
+#define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
+#define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
+#define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
+#define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
+ * @{
+ */
+#define LL_PWR_BATT_CHARG_RESISTOR_5K (0x00000000U)
+#define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_SRAM2_CONTENT_RETENTION SRAM2 CONTENT RETENTION
+ * @{
+ */
+#define LL_PWR_NO_SRAM2_RETENTION (0x00000000U)
+#if defined(PWR_CR3_RRS_1)
+#define LL_PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS_0
+#define LL_PWR_4KBYTES_SRAM2_RETENTION PWR_CR3_RRS_1
+#else
+#define LL_PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS
+#endif /* PWR_CR3_RRS_1 */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_GPIO GPIO
+ * @{
+ */
+#define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
+#define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
+#define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
+#define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
+#define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
+#if defined(GPIOF)
+#define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
+#endif
+#if defined(GPIOG)
+#define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))
+#endif
+#if defined(GPIOH)
+#define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH)))
+#endif
+#if defined(GPIOI)
+#define LL_PWR_GPIO_I ((uint32_t)(&(PWR->PUCRI)))
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
+ * @{
+ */
+#define LL_PWR_GPIO_BIT_0 (0x00000001U)
+#define LL_PWR_GPIO_BIT_1 (0x00000002U)
+#define LL_PWR_GPIO_BIT_2 (0x00000004U)
+#define LL_PWR_GPIO_BIT_3 (0x00000008U)
+#define LL_PWR_GPIO_BIT_4 (0x00000010U)
+#define LL_PWR_GPIO_BIT_5 (0x00000020U)
+#define LL_PWR_GPIO_BIT_6 (0x00000040U)
+#define LL_PWR_GPIO_BIT_7 (0x00000080U)
+#define LL_PWR_GPIO_BIT_8 (0x00000100U)
+#define LL_PWR_GPIO_BIT_9 (0x00000200U)
+#define LL_PWR_GPIO_BIT_10 (0x00000400U)
+#define LL_PWR_GPIO_BIT_11 (0x00000800U)
+#define LL_PWR_GPIO_BIT_12 (0x00001000U)
+#define LL_PWR_GPIO_BIT_13 (0x00002000U)
+#define LL_PWR_GPIO_BIT_14 (0x00004000U)
+#define LL_PWR_GPIO_BIT_15 (0x00008000U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
+ * @{
+ */
+
+/** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in PWR register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in PWR register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @defgroup PWR_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Switch the regulator from main mode to low-power mode
+ * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
+{
+ SET_BIT(PWR->CR1, PWR_CR1_LPR);
+}
+
+/**
+ * @brief Switch the regulator from low-power mode to main mode
+ * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
+{
+ CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
+}
+
+/**
+ * @brief Switch from run main mode to run low-power mode.
+ * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
+{
+ LL_PWR_EnableLowPowerRunMode();
+}
+
+/**
+ * @brief Switch from run main mode to low-power mode.
+ * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
+{
+ LL_PWR_DisableLowPowerRunMode();
+}
+
+/**
+ * @brief Check if the regulator is in low-power mode
+ * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
+{
+ return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the main internal regulator output voltage
+ * @note This configuration may be completed with LL_PWR_EnableRange1BoostMode() on STM32L4Rx/STM32L4Sx devices.
+ * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling
+ * @param VoltageScaling This parameter can be one of the following values:
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
+{
+ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
+}
+
+/**
+ * @brief Get the main internal regulator output voltage
+ * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
+}
+
+#if defined(PWR_CR5_R1MODE)
+/**
+ * @brief Enable main regulator voltage range 1 boost mode
+ * @rmtoll CR5 R1MODE LL_PWR_EnableRange1BoostMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void)
+{
+ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
+}
+
+/**
+ * @brief Disable main regulator voltage range 1 boost mode
+ * @rmtoll CR5 R1MODE LL_PWR_DisableRange1BoostMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void)
+{
+ SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
+}
+
+/**
+ * @brief Check if the main regulator voltage range 1 boost mode is enabled
+ * @rmtoll CR5 R1MODE LL_PWR_IsEnabledRange1BoostMode
+ * @retval Inverted state of bit (0 or 1).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void)
+{
+ return ((READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == 0x0U) ? 1UL : 0UL);
+}
+#endif /* PWR_CR5_R1MODE */
+
+/**
+ * @brief Enable access to the backup domain
+ * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
+{
+ SET_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+ * @brief Disable access to the backup domain
+ * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
+{
+ CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+ * @brief Check if the backup domain is enabled
+ * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
+{
+ return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set Low-Power mode
+ * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
+ * @param LowPowerMode This parameter can be one of the following values:
+ * @arg @ref LL_PWR_MODE_STOP0
+ * @arg @ref LL_PWR_MODE_STOP1
+ * @arg @ref LL_PWR_MODE_STOP2
+ * @arg @ref LL_PWR_MODE_STANDBY
+ * @arg @ref LL_PWR_MODE_SHUTDOWN
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
+{
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
+}
+
+/**
+ * @brief Get Low-Power mode
+ * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_MODE_STOP0
+ * @arg @ref LL_PWR_MODE_STOP1
+ * @arg @ref LL_PWR_MODE_STOP2
+ * @arg @ref LL_PWR_MODE_STANDBY
+ * @arg @ref LL_PWR_MODE_SHUTDOWN
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
+}
+
+#if defined(PWR_CR1_RRSTP)
+/**
+ * @brief Enable SRAM3 content retention in Stop mode
+ * @rmtoll CR1 RRSTP LL_PWR_EnableSRAM3Retention
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableSRAM3Retention(void)
+{
+ SET_BIT(PWR->CR1, PWR_CR1_RRSTP);
+}
+
+/**
+ * @brief Disable SRAM3 content retention in Stop mode
+ * @rmtoll CR1 RRSTP LL_PWR_DisableSRAM3Retention
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableSRAM3Retention(void)
+{
+ CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP);
+}
+
+/**
+ * @brief Check if SRAM3 content retention in Stop mode is enabled
+ * @rmtoll CR1 RRSTP LL_PWR_IsEnabledSRAM3Retention
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM3Retention(void)
+{
+ return ((READ_BIT(PWR->CR1, PWR_CR1_RRSTP) == (PWR_CR1_RRSTP)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_RRSTP */
+
+#if defined(PWR_CR3_DSIPDEN)
+/**
+ * @brief Enable pull-down activation on DSI pins
+ * @rmtoll CR3 DSIPDEN LL_PWR_EnableDSIPinsPDActivation
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableDSIPinsPDActivation(void)
+{
+ SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN);
+}
+
+/**
+ * @brief Disable pull-down activation on DSI pins
+ * @rmtoll CR3 DSIPDEN LL_PWR_DisableDSIPinsPDActivation
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableDSIPinsPDActivation(void)
+{
+ CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN);
+}
+
+/**
+ * @brief Check if pull-down activation on DSI pins is enabled
+ * @rmtoll CR3 DSIPDEN LL_PWR_IsEnabledDSIPinsPDActivation
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPinsPDActivation(void)
+{
+ return ((READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR3_DSIPDEN */
+
+#if defined(PWR_CR2_USV)
+/**
+ * @brief Enable VDDUSB supply
+ * @rmtoll CR2 USV LL_PWR_EnableVddUSB
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableVddUSB(void)
+{
+ SET_BIT(PWR->CR2, PWR_CR2_USV);
+}
+
+/**
+ * @brief Disable VDDUSB supply
+ * @rmtoll CR2 USV LL_PWR_DisableVddUSB
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableVddUSB(void)
+{
+ CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
+}
+
+/**
+ * @brief Check if VDDUSB supply is enabled
+ * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
+{
+ return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL);
+}
+#endif
+
+#if defined(PWR_CR2_IOSV)
+/**
+ * @brief Enable VDDIO2 supply
+ * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableVddIO2(void)
+{
+ SET_BIT(PWR->CR2, PWR_CR2_IOSV);
+}
+
+/**
+ * @brief Disable VDDIO2 supply
+ * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableVddIO2(void)
+{
+ CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
+}
+
+/**
+ * @brief Check if VDDIO2 supply is enabled
+ * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
+{
+ return ((READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)) ? 1UL : 0UL);
+}
+#endif
+
+/**
+ * @brief Enable the Power Voltage Monitoring on a peripheral
+ * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n
+ * CR2 PVME2 LL_PWR_EnablePVM\n
+ * CR2 PVME3 LL_PWR_EnablePVM\n
+ * CR2 PVME4 LL_PWR_EnablePVM
+ * @param PeriphVoltage This parameter can be one of the following values:
+ * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
+ * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)
+ * @arg @ref LL_PWR_PVM_VDDA_1_62V
+ * @arg @ref LL_PWR_PVM_VDDA_2_2V
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
+{
+ SET_BIT(PWR->CR2, PeriphVoltage);
+}
+
+/**
+ * @brief Disable the Power Voltage Monitoring on a peripheral
+ * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n
+ * CR2 PVME2 LL_PWR_DisablePVM\n
+ * CR2 PVME3 LL_PWR_DisablePVM\n
+ * CR2 PVME4 LL_PWR_DisablePVM
+ * @param PeriphVoltage This parameter can be one of the following values:
+ * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
+ * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)
+ * @arg @ref LL_PWR_PVM_VDDA_1_62V
+ * @arg @ref LL_PWR_PVM_VDDA_2_2V
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
+{
+ CLEAR_BIT(PWR->CR2, PeriphVoltage);
+}
+
+/**
+ * @brief Check if Power Voltage Monitoring is enabled on a peripheral
+ * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n
+ * CR2 PVME2 LL_PWR_IsEnabledPVM\n
+ * CR2 PVME3 LL_PWR_IsEnabledPVM\n
+ * CR2 PVME4 LL_PWR_IsEnabledPVM
+ * @param PeriphVoltage This parameter can be one of the following values:
+ * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
+ * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)
+ * @arg @ref LL_PWR_PVM_VDDA_1_62V
+ * @arg @ref LL_PWR_PVM_VDDA_2_2V
+ *
+ * (*) value not defined in all devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
+{
+ return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the voltage threshold detected by the Power Voltage Detector
+ * @rmtoll CR2 PLS LL_PWR_SetPVDLevel
+ * @param PVDLevel This parameter can be one of the following values:
+ * @arg @ref LL_PWR_PVDLEVEL_0
+ * @arg @ref LL_PWR_PVDLEVEL_1
+ * @arg @ref LL_PWR_PVDLEVEL_2
+ * @arg @ref LL_PWR_PVDLEVEL_3
+ * @arg @ref LL_PWR_PVDLEVEL_4
+ * @arg @ref LL_PWR_PVDLEVEL_5
+ * @arg @ref LL_PWR_PVDLEVEL_6
+ * @arg @ref LL_PWR_PVDLEVEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
+{
+ MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
+}
+
+/**
+ * @brief Get the voltage threshold detection
+ * @rmtoll CR2 PLS LL_PWR_GetPVDLevel
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_PVDLEVEL_0
+ * @arg @ref LL_PWR_PVDLEVEL_1
+ * @arg @ref LL_PWR_PVDLEVEL_2
+ * @arg @ref LL_PWR_PVDLEVEL_3
+ * @arg @ref LL_PWR_PVDLEVEL_4
+ * @arg @ref LL_PWR_PVDLEVEL_5
+ * @arg @ref LL_PWR_PVDLEVEL_6
+ * @arg @ref LL_PWR_PVDLEVEL_7
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
+}
+
+/**
+ * @brief Enable Power Voltage Detector
+ * @rmtoll CR2 PVDE LL_PWR_EnablePVD
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnablePVD(void)
+{
+ SET_BIT(PWR->CR2, PWR_CR2_PVDE);
+}
+
+/**
+ * @brief Disable Power Voltage Detector
+ * @rmtoll CR2 PVDE LL_PWR_DisablePVD
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisablePVD(void)
+{
+ CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
+}
+
+/**
+ * @brief Check if Power Voltage Detector is enabled
+ * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
+{
+ return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Internal Wake-up line
+ * @rmtoll CR3 EIWF LL_PWR_EnableInternWU
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableInternWU(void)
+{
+ SET_BIT(PWR->CR3, PWR_CR3_EIWF);
+}
+
+/**
+ * @brief Disable Internal Wake-up line
+ * @rmtoll CR3 EIWF LL_PWR_DisableInternWU
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableInternWU(void)
+{
+ CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
+}
+
+/**
+ * @brief Check if Internal Wake-up line is enabled
+ * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
+{
+ return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable pull-up and pull-down configuration
+ * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
+{
+ SET_BIT(PWR->CR3, PWR_CR3_APC);
+}
+
+/**
+ * @brief Disable pull-up and pull-down configuration
+ * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
+{
+ CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
+}
+
+/**
+ * @brief Check if pull-up and pull-down configuration is enabled
+ * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
+{
+ return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL);
+}
+
+#if defined(PWR_CR3_DSIPDEN)
+/**
+ * @brief Enable pull-down activation on DSI pins
+ * @rmtoll CR3 DSIPDEN LL_PWR_EnableDSIPullDown
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableDSIPullDown(void)
+{
+ SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN);
+}
+
+/**
+ * @brief Disable pull-down activation on DSI pins
+ * @rmtoll CR3 DSIPDEN LL_PWR_DisableDSIPullDown
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableDSIPullDown(void)
+{
+ CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN);
+}
+
+/**
+ * @brief Check if pull-down activation on DSI pins is enabled
+ * @rmtoll CR3 DSIPDEN LL_PWR_IsEnabledDSIPullDown
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPullDown(void)
+{
+ return ((READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR3_DSIPDEN */
+
+#if defined(PWR_CR3_ENULP)
+/**
+ * @brief Enable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes
+ * @rmtoll CR3 ENULP LL_PWR_EnableBORPVD_ULP
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableBORPVD_ULP(void)
+{
+ SET_BIT(PWR->CR3, PWR_CR3_ENULP);
+}
+
+/**
+ * @brief Disable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes
+ * @rmtoll CR3 ENULP LL_PWR_DisableBORPVD_ULP
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableBORPVD_ULP(void)
+{
+ CLEAR_BIT(PWR->CR3, PWR_CR3_ENULP);
+}
+
+/**
+ * @brief Check if Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes is enabled
+ * @rmtoll CR3 ENULP LL_PWR_IsEnabledBORPVD_ULP
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBORPVD_ULP(void)
+{
+ return ((READ_BIT(PWR->CR3, PWR_CR3_ENULP) == (PWR_CR3_ENULP)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR3_ENULP */
+
+/**
+ * @brief Enable SRAM2 full content retention in Standby mode
+ * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void)
+{
+ MODIFY_REG(PWR->CR3, PWR_CR3_RRS, LL_PWR_FULL_SRAM2_RETENTION);
+}
+
+/**
+ * @brief Disable SRAM2 content retention in Standby mode
+ * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void)
+{
+ CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
+}
+
+/**
+ * @brief Check if SRAM2 full content retention in Standby mode is enabled
+ * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void)
+{
+ return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (LL_PWR_FULL_SRAM2_RETENTION)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set SRAM2 content retention in Standby mode
+ * @rmtoll CR3 RRS LL_PWR_SetSRAM2ContentRetention
+ * @param SRAM2Size This parameter can be one of the following values:
+ * @arg @ref LL_PWR_NO_SRAM2_RETENTION
+ * @arg @ref LL_PWR_FULL_SRAM2_RETENTION
+ * @arg @ref LL_PWR_4KBYTES_SRAM2_RETENTION
+ * @note LL_PWR_4KBYTES_SRAM2_RETENTION parameter is not available on all devices
+ * @note Setting LL_PWR_NO_SRAM2_RETENTION is same as calling LL_PWR_DisableSRAM2Retention()
+ * @note Setting LL_PWR_FULL_SRAM2_RETENTION is same as calling LL_PWR_EnableSRAM2Retention()
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetSRAM2ContentRetention(uint32_t SRAM2Size)
+{
+ MODIFY_REG(PWR->CR3, PWR_CR3_RRS, SRAM2Size);
+}
+
+/**
+ * @brief Get SRAM2 content retention in Standby mode
+ * @rmtoll CR3 RRS LL_PWR_GetSRAM2ContentRetention
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_NO_SRAM2_RETENTION
+ * @arg @ref LL_PWR_FULL_SRAM2_RETENTION
+ * @arg @ref LL_PWR_4KBYTES_SRAM2_RETENTION
+ * @note LL_PWR_4KBYTES_SRAM2_RETENTION parameter is not available on all devices
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetSRAM2ContentRetention(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_RRS));
+}
+
+/**
+ * @brief Enable the WakeUp PINx functionality
+ * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
+ * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
+ * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n
+ * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n
+ * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
+{
+ SET_BIT(PWR->CR3, WakeUpPin);
+}
+
+/**
+ * @brief Disable the WakeUp PINx functionality
+ * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
+ * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
+ * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n
+ * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n
+ * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
+{
+ CLEAR_BIT(PWR->CR3, WakeUpPin);
+}
+
+/**
+ * @brief Check if the WakeUp PINx functionality is enabled
+ * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
+ * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
+ * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
+ * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
+ * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
+{
+ return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
+}
+
+#if defined(PWR_CR4_EXT_SMPS_ON)
+/**
+ * @brief Enable the CFLDO working @ 0.95V
+ * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the
+ * internal CFLDO can be reduced to 0.95V.
+ * @rmtoll CR4 EXT_SMPS_ON LL_PWR_EnableExtSMPS_0V95
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableExtSMPS_0V95(void)
+{
+ SET_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);
+}
+
+/**
+ * @brief Disable the CFLDO working @ 0.95V
+ * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the
+ * internal CFLDO can be reduced to 0.95V.
+ * @rmtoll CR4 EXT_SMPS_ON LL_PWR_DisableExtSMPS_0V95
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableExtSMPS_0V95(void)
+{
+ CLEAR_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);
+}
+
+/**
+ * @brief Check if CFLDO is working @ 0.95V
+ * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the
+ * internal CFLDO can be reduced to 0.95V.
+ * @rmtoll CR4 EXT_SMPS_ON LL_PWR_IsEnabledExtSMPS_0V95
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledExtSMPS_0V95(void)
+{
+ return ((READ_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON) == (PWR_CR4_EXT_SMPS_ON)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR4_EXT_SMPS_ON */
+
+/**
+ * @brief Set the resistor impedance
+ * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor
+ * @param Resistor This parameter can be one of the following values:
+ * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
+ * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
+{
+ MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
+}
+
+/**
+ * @brief Get the resistor impedance
+ * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
+ * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
+}
+
+/**
+ * @brief Enable battery charging
+ * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
+{
+ SET_BIT(PWR->CR4, PWR_CR4_VBE);
+}
+
+/**
+ * @brief Disable battery charging
+ * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
+{
+ CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
+}
+
+/**
+ * @brief Check if battery charging is enabled
+ * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
+{
+ return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the Wake-Up pin polarity low for the event detection
+ * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n
+ * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n
+ * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n
+ * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n
+ * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
+{
+ SET_BIT(PWR->CR4, WakeUpPin);
+}
+
+/**
+ * @brief Set the Wake-Up pin polarity high for the event detection
+ * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n
+ * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n
+ * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n
+ * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n
+ * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
+{
+ CLEAR_BIT(PWR->CR4, WakeUpPin);
+}
+
+/**
+ * @brief Get the Wake-Up pin polarity for the event detection
+ * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n
+ * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n
+ * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n
+ * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n
+ * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN4
+ * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
+{
+ return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable GPIO pull-up state in Standby and Shutdown modes
+ * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
+ * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
+ * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
+ * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n
+ * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n
+ * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n
+ * PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n
+ * PUCRH PU0-15 LL_PWR_EnableGPIOPullUp\n
+ * PUCRI PU0-11 LL_PWR_EnableGPIOPullUp
+ * @param GPIO This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_A
+ * @arg @ref LL_PWR_GPIO_B
+ * @arg @ref LL_PWR_GPIO_C
+ * @arg @ref LL_PWR_GPIO_D
+ * @arg @ref LL_PWR_GPIO_E
+ * @arg @ref LL_PWR_GPIO_F (*)
+ * @arg @ref LL_PWR_GPIO_G (*)
+ * @arg @ref LL_PWR_GPIO_H
+ * @arg @ref LL_PWR_GPIO_I (*)
+ *
+ * (*) value not defined in all devices
+ * @param GPIONumber This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_BIT_0
+ * @arg @ref LL_PWR_GPIO_BIT_1
+ * @arg @ref LL_PWR_GPIO_BIT_2
+ * @arg @ref LL_PWR_GPIO_BIT_3
+ * @arg @ref LL_PWR_GPIO_BIT_4
+ * @arg @ref LL_PWR_GPIO_BIT_5
+ * @arg @ref LL_PWR_GPIO_BIT_6
+ * @arg @ref LL_PWR_GPIO_BIT_7
+ * @arg @ref LL_PWR_GPIO_BIT_8
+ * @arg @ref LL_PWR_GPIO_BIT_9
+ * @arg @ref LL_PWR_GPIO_BIT_10
+ * @arg @ref LL_PWR_GPIO_BIT_11
+ * @arg @ref LL_PWR_GPIO_BIT_12
+ * @arg @ref LL_PWR_GPIO_BIT_13
+ * @arg @ref LL_PWR_GPIO_BIT_14
+ * @arg @ref LL_PWR_GPIO_BIT_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
+{
+ SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
+}
+
+/**
+ * @brief Disable GPIO pull-up state in Standby and Shutdown modes
+ * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
+ * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n
+ * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n
+ * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n
+ * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n
+ * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n
+ * PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n
+ * PUCRH PU0-15 LL_PWR_DisableGPIOPullUp\n
+ * PUCRI PU0-11 LL_PWR_DisableGPIOPullUp
+ * @param GPIO This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_A
+ * @arg @ref LL_PWR_GPIO_B
+ * @arg @ref LL_PWR_GPIO_C
+ * @arg @ref LL_PWR_GPIO_D
+ * @arg @ref LL_PWR_GPIO_E
+ * @arg @ref LL_PWR_GPIO_F (*)
+ * @arg @ref LL_PWR_GPIO_G (*)
+ * @arg @ref LL_PWR_GPIO_H
+ * @arg @ref LL_PWR_GPIO_I (*)
+ *
+ * (*) value not defined in all devices
+ * @param GPIONumber This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_BIT_0
+ * @arg @ref LL_PWR_GPIO_BIT_1
+ * @arg @ref LL_PWR_GPIO_BIT_2
+ * @arg @ref LL_PWR_GPIO_BIT_3
+ * @arg @ref LL_PWR_GPIO_BIT_4
+ * @arg @ref LL_PWR_GPIO_BIT_5
+ * @arg @ref LL_PWR_GPIO_BIT_6
+ * @arg @ref LL_PWR_GPIO_BIT_7
+ * @arg @ref LL_PWR_GPIO_BIT_8
+ * @arg @ref LL_PWR_GPIO_BIT_9
+ * @arg @ref LL_PWR_GPIO_BIT_10
+ * @arg @ref LL_PWR_GPIO_BIT_11
+ * @arg @ref LL_PWR_GPIO_BIT_12
+ * @arg @ref LL_PWR_GPIO_BIT_13
+ * @arg @ref LL_PWR_GPIO_BIT_14
+ * @arg @ref LL_PWR_GPIO_BIT_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
+{
+ CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
+}
+
+/**
+ * @brief Check if GPIO pull-up state is enabled
+ * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
+ * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
+ * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
+ * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
+ * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
+ * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
+ * PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
+ * PUCRH PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
+ * PUCRI PU0-11 LL_PWR_IsEnabledGPIOPullUp
+ * @param GPIO This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_A
+ * @arg @ref LL_PWR_GPIO_B
+ * @arg @ref LL_PWR_GPIO_C
+ * @arg @ref LL_PWR_GPIO_D
+ * @arg @ref LL_PWR_GPIO_E
+ * @arg @ref LL_PWR_GPIO_F (*)
+ * @arg @ref LL_PWR_GPIO_G (*)
+ * @arg @ref LL_PWR_GPIO_H
+ * @arg @ref LL_PWR_GPIO_I (*)
+ *
+ * (*) value not defined in all devices
+ * @param GPIONumber This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_BIT_0
+ * @arg @ref LL_PWR_GPIO_BIT_1
+ * @arg @ref LL_PWR_GPIO_BIT_2
+ * @arg @ref LL_PWR_GPIO_BIT_3
+ * @arg @ref LL_PWR_GPIO_BIT_4
+ * @arg @ref LL_PWR_GPIO_BIT_5
+ * @arg @ref LL_PWR_GPIO_BIT_6
+ * @arg @ref LL_PWR_GPIO_BIT_7
+ * @arg @ref LL_PWR_GPIO_BIT_8
+ * @arg @ref LL_PWR_GPIO_BIT_9
+ * @arg @ref LL_PWR_GPIO_BIT_10
+ * @arg @ref LL_PWR_GPIO_BIT_11
+ * @arg @ref LL_PWR_GPIO_BIT_12
+ * @arg @ref LL_PWR_GPIO_BIT_13
+ * @arg @ref LL_PWR_GPIO_BIT_14
+ * @arg @ref LL_PWR_GPIO_BIT_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
+{
+ return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable GPIO pull-down state in Standby and Shutdown modes
+ * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
+ * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n
+ * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n
+ * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n
+ * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n
+ * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n
+ * PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n
+ * PDCRH PD0-15 LL_PWR_EnableGPIOPullDown\n
+ * PDCRI PD0-11 LL_PWR_EnableGPIOPullDown
+ * @param GPIO This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_A
+ * @arg @ref LL_PWR_GPIO_B
+ * @arg @ref LL_PWR_GPIO_C
+ * @arg @ref LL_PWR_GPIO_D
+ * @arg @ref LL_PWR_GPIO_E
+ * @arg @ref LL_PWR_GPIO_F (*)
+ * @arg @ref LL_PWR_GPIO_G (*)
+ * @arg @ref LL_PWR_GPIO_H
+ * @arg @ref LL_PWR_GPIO_I (*)
+ *
+ * (*) value not defined in all devices
+ * @param GPIONumber This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_BIT_0
+ * @arg @ref LL_PWR_GPIO_BIT_1
+ * @arg @ref LL_PWR_GPIO_BIT_2
+ * @arg @ref LL_PWR_GPIO_BIT_3
+ * @arg @ref LL_PWR_GPIO_BIT_4
+ * @arg @ref LL_PWR_GPIO_BIT_5
+ * @arg @ref LL_PWR_GPIO_BIT_6
+ * @arg @ref LL_PWR_GPIO_BIT_7
+ * @arg @ref LL_PWR_GPIO_BIT_8
+ * @arg @ref LL_PWR_GPIO_BIT_9
+ * @arg @ref LL_PWR_GPIO_BIT_10
+ * @arg @ref LL_PWR_GPIO_BIT_11
+ * @arg @ref LL_PWR_GPIO_BIT_12
+ * @arg @ref LL_PWR_GPIO_BIT_13
+ * @arg @ref LL_PWR_GPIO_BIT_14
+ * @arg @ref LL_PWR_GPIO_BIT_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
+{
+ SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
+}
+
+/**
+ * @brief Disable GPIO pull-down state in Standby and Shutdown modes
+ * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
+ * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n
+ * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n
+ * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n
+ * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n
+ * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n
+ * PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n
+ * PDCRH PD0-15 LL_PWR_DisableGPIOPullDown\n
+ * PDCRI PD0-11 LL_PWR_DisableGPIOPullDown
+ * @param GPIO This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_A
+ * @arg @ref LL_PWR_GPIO_B
+ * @arg @ref LL_PWR_GPIO_C
+ * @arg @ref LL_PWR_GPIO_D
+ * @arg @ref LL_PWR_GPIO_E
+ * @arg @ref LL_PWR_GPIO_F (*)
+ * @arg @ref LL_PWR_GPIO_G (*)
+ * @arg @ref LL_PWR_GPIO_H
+ * @arg @ref LL_PWR_GPIO_I (*)
+ *
+ * (*) value not defined in all devices
+ * @param GPIONumber This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_BIT_0
+ * @arg @ref LL_PWR_GPIO_BIT_1
+ * @arg @ref LL_PWR_GPIO_BIT_2
+ * @arg @ref LL_PWR_GPIO_BIT_3
+ * @arg @ref LL_PWR_GPIO_BIT_4
+ * @arg @ref LL_PWR_GPIO_BIT_5
+ * @arg @ref LL_PWR_GPIO_BIT_6
+ * @arg @ref LL_PWR_GPIO_BIT_7
+ * @arg @ref LL_PWR_GPIO_BIT_8
+ * @arg @ref LL_PWR_GPIO_BIT_9
+ * @arg @ref LL_PWR_GPIO_BIT_10
+ * @arg @ref LL_PWR_GPIO_BIT_11
+ * @arg @ref LL_PWR_GPIO_BIT_12
+ * @arg @ref LL_PWR_GPIO_BIT_13
+ * @arg @ref LL_PWR_GPIO_BIT_14
+ * @arg @ref LL_PWR_GPIO_BIT_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
+{
+ CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
+}
+
+/**
+ * @brief Check if GPIO pull-down state is enabled
+ * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
+ * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
+ * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
+ * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
+ * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
+ * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
+ * PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
+ * PDCRH PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
+ * PDCRI PD0-11 LL_PWR_IsEnabledGPIOPullDown
+ * @param GPIO This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_A
+ * @arg @ref LL_PWR_GPIO_B
+ * @arg @ref LL_PWR_GPIO_C
+ * @arg @ref LL_PWR_GPIO_D
+ * @arg @ref LL_PWR_GPIO_E
+ * @arg @ref LL_PWR_GPIO_F (*)
+ * @arg @ref LL_PWR_GPIO_G (*)
+ * @arg @ref LL_PWR_GPIO_H
+ * @arg @ref LL_PWR_GPIO_I (*)
+ *
+ * (*) value not defined in all devices
+ * @param GPIONumber This parameter can be one of the following values:
+ * @arg @ref LL_PWR_GPIO_BIT_0
+ * @arg @ref LL_PWR_GPIO_BIT_1
+ * @arg @ref LL_PWR_GPIO_BIT_2
+ * @arg @ref LL_PWR_GPIO_BIT_3
+ * @arg @ref LL_PWR_GPIO_BIT_4
+ * @arg @ref LL_PWR_GPIO_BIT_5
+ * @arg @ref LL_PWR_GPIO_BIT_6
+ * @arg @ref LL_PWR_GPIO_BIT_7
+ * @arg @ref LL_PWR_GPIO_BIT_8
+ * @arg @ref LL_PWR_GPIO_BIT_9
+ * @arg @ref LL_PWR_GPIO_BIT_10
+ * @arg @ref LL_PWR_GPIO_BIT_11
+ * @arg @ref LL_PWR_GPIO_BIT_12
+ * @arg @ref LL_PWR_GPIO_BIT_13
+ * @arg @ref LL_PWR_GPIO_BIT_14
+ * @arg @ref LL_PWR_GPIO_BIT_15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
+{
+ return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Internal Wake-up line Flag
+ * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
+{
+ return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL);
+}
+
+#if defined(PWR_SR1_EXT_SMPS_RDY)
+/**
+ * @brief Get Ready Flag for switching to external SMPS
+ * @rmtoll SR1 EXT_SMPS_RDY LL_PWR_IsActiveFlag_ExtSMPSReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ExtSMPSReady(void)
+{
+ return ((READ_BIT(PWR->SR1, PWR_SR1_EXT_SMPS_RDY) == (PWR_SR1_EXT_SMPS_RDY)) ? 1UL : 0UL);
+}
+#endif /* PWR_SR1_EXT_SMPS_RDY */
+
+/**
+ * @brief Get Stand-By Flag
+ * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
+{
+ return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Wake-up Flag 5
+ * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
+{
+ return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Wake-up Flag 4
+ * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
+{
+ return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Wake-up Flag 3
+ * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
+{
+ return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Wake-up Flag 2
+ * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
+{
+ return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get Wake-up Flag 1
+ * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
+{
+ return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear Stand-By Flag
+ * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
+{
+ WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
+}
+
+/**
+ * @brief Clear Wake-up Flags
+ * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
+{
+ WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
+}
+
+/**
+ * @brief Clear Wake-up Flag 5
+ * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
+{
+ WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
+}
+
+/**
+ * @brief Clear Wake-up Flag 4
+ * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
+{
+ WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
+}
+
+/**
+ * @brief Clear Wake-up Flag 3
+ * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
+{
+ WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
+}
+
+/**
+ * @brief Clear Wake-up Flag 2
+ * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
+{
+ WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
+}
+
+/**
+ * @brief Clear Wake-up Flag 1
+ * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
+{
+ WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
+}
+
+/**
+ * @brief Indicate whether VDDA voltage is below or above PVM4 threshold
+ * @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void)
+{
+ return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether VDDA voltage is below or above PVM3 threshold
+ * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
+{
+ return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL);
+}
+
+#if defined(PWR_SR2_PVMO2)
+/**
+ * @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold
+ * @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void)
+{
+ return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2)) ? 1UL : 0UL);
+}
+#endif /* PWR_SR2_PVMO2 */
+
+#if defined(PWR_SR2_PVMO1)
+/**
+ * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold
+ * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void)
+{
+ return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)) ? 1UL : 0UL);
+}
+#endif /* PWR_SR2_PVMO1 */
+
+/**
+ * @brief Indicate whether VDD voltage is below or above the selected PVD threshold
+ * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
+{
+ return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
+ * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
+{
+ return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether the regulator is ready in main mode or is in low-power mode
+ * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
+ * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
+{
+ return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate whether or not the low-power regulator is ready
+ * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
+{
+ return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup PWR_LL_EF_Init De-initialization function
+ * @{
+ */
+ErrorStatus LL_PWR_DeInit(void);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name
+ * @{
+ */
+/* Old functions name kept for legacy purpose, to be replaced by the */
+/* current functions name. */
+#define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(PWR) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L4xx_LL_PWR_H */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h
new file mode 100644
index 0000000..cc05c56
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h
@@ -0,0 +1,6233 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_rcc.h
+ * @author MCD Application Team
+ * @brief Header file of RCC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L4xx_LL_RCC_H
+#define STM32L4xx_LL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Constants RCC Private Constants
+ * @{
+ */
+/* Defines used to perform offsets*/
+/* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */
+#define RCC_OFFSET_CCIPR 0U
+#define RCC_OFFSET_CCIPR2 0x14U
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Private_Macros RCC Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Exported_Types RCC Exported Types
+ * @{
+ */
+
+/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+ * @{
+ */
+
+/**
+ * @brief RCC Clocks Frequency Structure
+ */
+typedef struct
+{
+ uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
+ uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
+ uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
+ uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
+} LL_RCC_ClocksTypeDef;
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+ * @{
+ */
+
+/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+ * @brief Defines used to adapt values of different oscillators
+ * @note These values could be modified in the user environment according to
+ * HW set-up.
+ * @{
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined (LSE_VALUE)
+#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined (LSI_VALUE)
+#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
+#endif /* LSI_VALUE */
+#if defined(RCC_HSI48_SUPPORT)
+
+#if !defined (HSI48_VALUE)
+#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
+#endif /* HSI48_VALUE */
+#endif /* RCC_HSI48_SUPPORT */
+
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+#define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+#if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
+#define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */
+#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_RCC_WriteReg function
+ * @{
+ */
+#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */
+#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
+#define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */
+#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
+#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
+#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
+#endif /* RCC_HSI48_SUPPORT */
+#if defined(RCC_PLLSAI1_SUPPORT)
+#define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */
+#endif /* RCC_PLLSAI1_SUPPORT */
+#if defined(RCC_PLLSAI2_SUPPORT)
+#define LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC /*!< PLLSAI2 Ready Interrupt Clear */
+#endif /* RCC_PLLSAI2_SUPPORT */
+#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
+#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_RCC_ReadReg function
+ * @{
+ */
+#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
+#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
+#define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */
+#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
+#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
+#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
+#endif /* RCC_HSI48_SUPPORT */
+#if defined(RCC_PLLSAI1_SUPPORT)
+#define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */
+#endif /* RCC_PLLSAI1_SUPPORT */
+#if defined(RCC_PLLSAI2_SUPPORT)
+#define LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */
+#endif /* RCC_PLLSAI2_SUPPORT */
+#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
+#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
+#define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF /*!< Firewall reset flag */
+#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
+#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
+#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
+#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
+#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
+#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
+#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
+ * @{
+ */
+#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */
+#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
+#define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */
+#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
+#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
+#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
+#endif /* RCC_HSI48_SUPPORT */
+#if defined(RCC_PLLSAI1_SUPPORT)
+#define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /*!< PLLSAI1 Ready Interrupt Enable */
+#endif /* RCC_PLLSAI1_SUPPORT */
+#if defined(RCC_PLLSAI2_SUPPORT)
+#define LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE /*!< PLLSAI2 Ready Interrupt Enable */
+#endif /* RCC_PLLSAI2_SUPPORT */
+#define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
+ * @{
+ */
+#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
+#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
+#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
+#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
+ * @{
+ */
+#define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */
+#define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */
+#define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */
+#define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */
+#define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */
+#define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */
+#define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */
+#define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */
+#define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */
+#define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */
+#define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */
+#define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MSISRANGE MSI range after Standby mode
+ * @{
+ */
+#define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1 /*!< MSI = 1 MHz */
+#define LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2 /*!< MSI = 2 MHz */
+#define LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4 /*!< MSI = 4 MHz */
+#define LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8 /*!< MSI = 8 MHz */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
+ * @{
+ */
+#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
+#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
+ * @{
+ */
+#define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
+ * @{
+ */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
+ * @{
+ */
+#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
+#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
+#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
+#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
+#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
+#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
+#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
+ * @{
+ */
+#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
+#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
+#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
+#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
+#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
+ * @{
+ */
+#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
+#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
+#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
+#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
+#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
+ * @{
+ */
+#define LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */
+#define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
+ * @{
+ */
+#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
+#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */
+#endif /* RCC_HSI48_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
+ * @{
+ */
+#define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
+#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
+#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
+#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
+#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+ * @{
+ */
+#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
+#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
+ * @{
+ */
+#define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */
+#define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */
+#if defined(RCC_CCIPR_USART3SEL)
+#define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U) /*!< PCLK1 clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */
+#endif /* RCC_CCIPR_USART3SEL */
+/**
+ * @}
+ */
+
+#if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
+/** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection
+ * @{
+ */
+#if defined(RCC_CCIPR_UART4SEL)
+#define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR_UART4SEL << 16U) /*!< PCLK1 clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_1) /*!< HSI clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL) /*!< LSE clock used as UART4 clock source */
+#endif /* RCC_CCIPR_UART4SEL */
+#if defined(RCC_CCIPR_UART5SEL)
+#define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR_UART5SEL << 16U) /*!< PCLK1 clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_1) /*!< HSI clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL) /*!< LSE clock used as UART5 clock source */
+#endif /* RCC_CCIPR_UART5SEL */
+/**
+ * @}
+ */
+#endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
+
+/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection
+ * @{
+ */
+#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPUART1 clock source */
+#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */
+#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */
+#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE clock used as LPUART1 clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
+ * @{
+ */
+#define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
+#define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
+#define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
+#if defined(RCC_CCIPR_I2C2SEL)
+#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */
+#endif /* RCC_CCIPR_I2C2SEL */
+#define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
+#if defined(RCC_CCIPR2_I2C4SEL)
+#define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */
+#define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
+#define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
+#endif /* RCC_CCIPR2_I2C4SEL */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
+ * @{
+ */
+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM1SEL /*!< PCLK1 clock used as LPTIM1 clock source */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /*!< LSI clock used as LPTIM1 clock source */
+#define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /*!< HSI clock used as LPTIM1 clock source */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U)) /*!< LSE clock used as LPTIM1 clock source */
+#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM2SEL /*!< PCLK1 clock used as LPTIM2 clock source */
+#define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /*!< LSI clock used as LPTIM2 clock source */
+#define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /*!< HSI clock used as LPTIM2 clock source */
+#define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U)) /*!< LSE clock used as LPTIM2 clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection
+ * @{
+ */
+#if defined(RCC_CCIPR2_SAI1SEL)
+#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLLSAI1 (PLLSAI1CLK) clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLLSAI2 (PLLSAI2CLK) clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PLL ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLL (PLLSAI3CLK) clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */
+#elif defined(RCC_CCIPR_SAI1SEL)
+#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI1SEL /*!< PLLSAI1 clock used as SAI1 clock source */
+#if defined(RCC_PLLSAI2_SUPPORT)
+#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI1 clock source */
+#endif /* RCC_PLLSAI2_SUPPORT */
+#define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_1 >> 16U)) /*!< PLL clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PIN (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL >> 16U)) /*!< External input clock used as SAI1 clock source */
+#endif /* RCC_CCIPR2_SAI1SEL */
+
+#if defined(RCC_CCIPR2_SAI2SEL)
+#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (RCC_CCIPR2_SAI2SEL << 16U) /*!< PLLSAI1 (PLLSAI1CLK) clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0) /*!< PLLSAI2 (PLLSAI2CLK) clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLL ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1) /*!< PLL (PLLSAI3CLK) clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0)) /*!< External input clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2) /*!< HSI clock used as SAI2 clock source */
+#elif defined(RCC_CCIPR_SAI2SEL)
+#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI2SEL /*!< PLLSAI1 clock used as SAI2 clock source */
+#if defined(RCC_PLLSAI2_SUPPORT)
+#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI2 clock source */
+#endif /* RCC_PLLSAI2_SUPPORT */
+#define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_1 >> 16U)) /*!< PLL clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PIN (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL >> 16U)) /*!< External input clock used as SAI2 clock source */
+#endif /* RCC_CCIPR2_SAI2SEL */
+/**
+ * @}
+ */
+
+#if defined(RCC_CCIPR2_SDMMCSEL)
+/** @defgroup RCC_LL_EC_SDMMC1_KERNELCLKSOURCE Peripheral SDMMC kernel clock source selection
+ * @{
+ */
+#define LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK 0x00000000U /*!< 48MHz clock from internal multiplexor used as SDMMC1 clock source */
+#define LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLLSAI3CLK clock used as SDMMC1 clock source */
+/**
+ * @}
+ */
+#endif /* RCC_CCIPR2_SDMMCSEL */
+
+#if defined(SDMMC1)
+/** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection
+ * @{
+ */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_SDMMC1_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as SDMMC1 clock source */
+#else
+#define LL_RCC_SDMMC1_CLKSOURCE_NONE 0x00000000U /*!< No clock used as SDMMC1 clock source */
+#endif
+#if defined(RCC_PLLSAI1_SUPPORT)
+#define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as SDMMC1 clock source */
+#endif /* RCC_PLLSAI1_SUPPORT */
+#define LL_RCC_SDMMC1_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as SDMMC1 clock source */
+#define LL_RCC_SDMMC1_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as SDMMC1 clock source */
+/**
+ * @}
+ */
+#endif /* SDMMC1 */
+
+/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
+ * @{
+ */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as RNG clock source */
+#else
+#define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RNG clock source */
+#endif
+#if defined(RCC_PLLSAI1_SUPPORT)
+#define LL_RCC_RNG_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as RNG clock source */
+#endif /* RCC_PLLSAI1_SUPPORT */
+#define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as RNG clock source */
+#define LL_RCC_RNG_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as RNG clock source */
+/**
+ * @}
+ */
+
+#if defined(USB_OTG_FS) || defined(USB)
+/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
+ * @{
+ */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */
+#else
+#define LL_RCC_USB_CLKSOURCE_NONE 0x00000000U /*!< No clock used as USB clock source */
+#endif
+#if defined(RCC_PLLSAI1_SUPPORT)
+#define LL_RCC_USB_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as USB clock source */
+#endif /* RCC_PLLSAI1_SUPPORT */
+#define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as USB clock source */
+#define LL_RCC_USB_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as USB clock source */
+/**
+ * @}
+ */
+
+#endif /* USB_OTG_FS || USB */
+
+/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
+ * @{
+ */
+#define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as ADC clock source */
+#if defined(RCC_PLLSAI1_SUPPORT)
+#define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 clock used as ADC clock source */
+#endif /* RCC_PLLSAI1_SUPPORT */
+#if defined(RCC_PLLSAI2_SUPPORT) && !defined(LTDC)
+#define LL_RCC_ADC_CLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 /*!< PLLSAI2 clock used as ADC clock source */
+#endif /* RCC_PLLSAI2_SUPPORT */
+#if defined(RCC_CCIPR_ADCSEL)
+#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK clock used as ADC clock source */
+#else
+#define LL_RCC_ADC_CLKSOURCE_SYSCLK 0x30000000U /*!< SYSCLK clock used as ADC clock source */
+#endif
+/**
+ * @}
+ */
+
+#if defined(SWPMI1)
+/** @defgroup RCC_LL_EC_SWPMI1_CLKSOURCE Peripheral SWPMI1 clock source selection
+ * @{
+ */
+#define LL_RCC_SWPMI1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 used as SWPMI1 clock source */
+#define LL_RCC_SWPMI1_CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL /*!< HSI used as SWPMI1 clock source */
+/**
+ * @}
+ */
+#endif /* SWPMI1 */
+
+#if defined(DFSDM1_Channel0)
+#if defined(RCC_CCIPR2_ADFSDM1SEL)
+/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM1 Audio clock source selection
+ * @{
+ */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /*!< SAI1 clock used as DFSDM1 Audio clock */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 /*!< HSI clock used as DFSDM1 Audio clock */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 /*!< MSI clock used as DFSDM1 Audio clock */
+/**
+ * @}
+ */
+#endif /* RCC_CCIPR2_ADFSDM1SEL */
+
+/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM1 clock source selection
+ * @{
+ */
+#if defined(RCC_CCIPR2_DFSDM1SEL)
+#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 used as DFSDM1 clock source */
+#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL /*!< SYSCLK used as DFSDM1 clock source */
+#else
+#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 used as DFSDM1 clock source */
+#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL /*!< SYSCLK used as DFSDM1 clock source */
+#endif /* RCC_CCIPR2_DFSDM1SEL */
+/**
+ * @}
+ */
+#endif /* DFSDM1_Channel0 */
+
+#if defined(DSI)
+/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
+ * @{
+ */
+#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */
+#define LL_RCC_DSI_CLKSOURCE_PLL RCC_CCIPR2_DSISEL /*!< PLL clock used as DSI byte lane clock source */
+/**
+ * @}
+ */
+#endif /* DSI */
+
+#if defined(LTDC)
+/** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection
+ * @{
+ */
+#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 0x00000000U /*!< PLLSAI2DIVR divided by 2 used as LTDC clock source */
+#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 /*!< PLLSAI2DIVR divided by 4 used as LTDC clock source */
+#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 /*!< PLLSAI2DIVR divided by 8 used as LTDC clock source */
+#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 RCC_CCIPR2_PLLSAI2DIVR /*!< PLLSAI2DIVR divided by 16 used as LTDC clock source */
+/**
+ * @}
+ */
+#endif /* LTDC */
+
+#if defined(OCTOSPI1)
+/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source
+ * @{
+ */
+#define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as OctoSPI clock source */
+#define LL_RCC_OCTOSPI_CLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 /*!< MSI used as OctoSPI clock source */
+#define LL_RCC_OCTOSPI_CLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 /*!< PLL used as OctoSPI clock source */
+/**
+ * @}
+ */
+#endif /* OCTOSPI1 */
+
+/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
+ * @{
+ */
+#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
+#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
+#if defined(RCC_CCIPR_USART3SEL)
+#define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */
+#endif /* RCC_CCIPR_USART3SEL */
+/**
+ * @}
+ */
+
+#if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
+/** @defgroup RCC_LL_EC_UART4 Peripheral UART get clock source
+ * @{
+ */
+#if defined(RCC_CCIPR_UART4SEL)
+#define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL /*!< UART4 Clock source selection */
+#endif /* RCC_CCIPR_UART4SEL */
+#if defined(RCC_CCIPR_UART5SEL)
+#define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL /*!< UART5 Clock source selection */
+#endif /* RCC_CCIPR_UART5SEL */
+/**
+ * @}
+ */
+#endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
+
+/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
+ * @{
+ */
+#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
+ * @{
+ */
+#define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
+#if defined(RCC_CCIPR_I2C2SEL)
+#define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
+#endif /* RCC_CCIPR_I2C2SEL */
+#define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
+#if defined(RCC_CCIPR2_I2C4SEL)
+#define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
+#endif /* RCC_CCIPR2_I2C4SEL */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
+ * @{
+ */
+#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 Clock source selection */
+#define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 Clock source selection */
+/**
+ * @}
+ */
+
+#if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL)
+/** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source
+ * @{
+ */
+#if defined(RCC_CCIPR2_SAI1SEL)
+#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */
+#else
+#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */
+#endif /* RCC_CCIPR2_SAI1SEL */
+#if defined(RCC_CCIPR2_SAI2SEL)
+#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL /*!< SAI2 Clock source selection */
+#elif defined(RCC_CCIPR_SAI2SEL)
+#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL /*!< SAI2 Clock source selection */
+#endif /* RCC_CCIPR2_SAI2SEL */
+/**
+ * @}
+ */
+#endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */
+
+#if defined(SDMMC1)
+#if defined(RCC_CCIPR2_SDMMCSEL)
+/** @defgroup RCC_LL_EC_SDMMC1_KERNEL Peripheral SDMMC get kernel clock source
+ * @{
+ */
+#define LL_RCC_SDMMC1_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL /*!< SDMMC1 Kernel Clock source selection */
+/**
+ * @}
+ */
+#endif /* RCC_CCIPR2_SDMMCSEL */
+
+/** @defgroup RCC_LL_EC_SDMMC1 Peripheral SDMMC get clock source
+ * @{
+ */
+#define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< SDMMC1 Clock source selection */
+/**
+ * @}
+ */
+#endif /* SDMMC1 */
+
+/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
+ * @{
+ */
+#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */
+/**
+ * @}
+ */
+
+#if defined(USB_OTG_FS) || defined(USB)
+/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
+ * @{
+ */
+#define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */
+/**
+ * @}
+ */
+#endif /* USB_OTG_FS || USB */
+
+/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
+ * @{
+ */
+#if defined(RCC_CCIPR_ADCSEL)
+#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */
+#else
+#define LL_RCC_ADC_CLKSOURCE 0x30000000U /*!< ADC Clock source selection */
+#endif
+/**
+ * @}
+ */
+
+#if defined(SWPMI1)
+/** @defgroup RCC_LL_EC_SWPMI1 Peripheral SWPMI1 get clock source
+ * @{
+ */
+#define LL_RCC_SWPMI1_CLKSOURCE RCC_CCIPR_SWPMI1SEL /*!< SWPMI1 Clock source selection */
+/**
+ * @}
+ */
+#endif /* SWPMI1 */
+
+#if defined(DFSDM1_Channel0)
+#if defined(RCC_CCIPR2_ADFSDM1SEL)
+/** @defgroup RCC_LL_EC_DFSDM1_AUDIO Peripheral DFSDM1 Audio get clock source
+ * @{
+ */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_CCIPR2_ADFSDM1SEL /* DFSDM1 Audio Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* RCC_CCIPR2_ADFSDM1SEL */
+/** @defgroup RCC_LL_EC_DFSDM1 Peripheral DFSDM1 get clock source
+ * @{
+ */
+#if defined(RCC_CCIPR2_DFSDM1SEL)
+#define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR2_DFSDM1SEL /*!< DFSDM1 Clock source selection */
+#else
+#define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL /*!< DFSDM1 Clock source selection */
+#endif /* RCC_CCIPR2_DFSDM1SEL */
+/**
+ * @}
+ */
+#endif /* DFSDM1_Channel0 */
+
+#if defined(DSI)
+/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
+ * @{
+ */
+#define LL_RCC_DSI_CLKSOURCE RCC_CCIPR2_DSISEL /*!< DSI Clock source selection */
+/**
+ * @}
+ */
+#endif /* DSI */
+
+#if defined(LTDC)
+/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
+ * @{
+ */
+#define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR2_PLLSAI2DIVR /*!< LTDC Clock source selection */
+/**
+ * @}
+ */
+#endif /* LTDC */
+
+#if defined(OCTOSPI1)
+/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source
+ * @{
+ */
+#define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OSPISEL /*!< OctoSPI Clock source selection */
+/**
+ * @}
+ */
+#endif /* OCTOSPI1 */
+
+
+/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
+ * @{
+ */
+#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLSAI1 and PLLSAI2 entry clock source
+ * @{
+ */
+#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */
+#define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor
+ * @{
+ */
+#define LL_RCC_PLLM_DIV_1 0x00000000U /*!< Main PLL division factor for PLLM input by 1 */
+#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 2 */
+#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 3 */
+#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 4 */
+#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 5 */
+#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 6 */
+#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 7 */
+#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 8 */
+#if defined(RCC_PLLM_DIV_1_16_SUPPORT)
+#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3) /*!< Main PLL division factor for PLLM input by 9 */
+#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 10 */
+#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 11 */
+#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 12 */
+#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 13 */
+#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 14 */
+#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 15 */
+#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 16 */
+#endif /* RCC_PLLM_DIV_1_16_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
+ * @{
+ */
+#define LL_RCC_PLLR_DIV_2 0x00000000U /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
+#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
+#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
+#define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
+/**
+ * @}
+ */
+
+#if defined(RCC_PLLP_SUPPORT)
+/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
+ * @{
+ */
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
+#define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 2 */
+#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 3 */
+#define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 4 */
+#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 5 */
+#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 6 */
+#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 7 */
+#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 8 */
+#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 9 */
+#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 10 */
+#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 11 */
+#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 12 */
+#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 13 */
+#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 14 */
+#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 15 */
+#define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 16 */
+#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 17 */
+#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 18 */
+#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 19 */
+#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 20 */
+#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 21 */
+#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 22 */
+#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 23 */
+#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 24 */
+#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 25 */
+#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 26 */
+#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 27 */
+#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 28 */
+#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 29 */
+#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 30 */
+#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 31 */
+#else
+#define LL_RCC_PLLP_DIV_7 0x00000000U /*!< Main PLL division factor for PLLP output by 7 */
+#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP) /*!< Main PLL division factor for PLLP output by 17 */
+#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
+/**
+ * @}
+ */
+#endif /* RCC_PLLP_SUPPORT */
+
+/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
+ * @{
+ */
+#define LL_RCC_PLLQ_DIV_2 0x00000000U /*!< Main PLL division factor for PLLQ output by 2 */
+#define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
+#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
+#define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */
+/**
+ * @}
+ */
+
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
+/** @defgroup RCC_LL_EC_PLLSAI1M PLLSAI1 division factor (PLLSAI1M)
+ * @{
+ */
+#define LL_RCC_PLLSAI1M_DIV_1 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1M input by 1 */
+#define LL_RCC_PLLSAI1M_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 2 */
+#define LL_RCC_PLLSAI1M_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 3 */
+#define LL_RCC_PLLSAI1M_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 4 */
+#define LL_RCC_PLLSAI1M_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 5 */
+#define LL_RCC_PLLSAI1M_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 6 */
+#define LL_RCC_PLLSAI1M_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 7 */
+#define LL_RCC_PLLSAI1M_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 8 */
+#define LL_RCC_PLLSAI1M_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1M_3) /*!< PLLSAI1 division factor for PLLSAI1M input by 9 */
+#define LL_RCC_PLLSAI1M_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 10 */
+#define LL_RCC_PLLSAI1M_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 11 */
+#define LL_RCC_PLLSAI1M_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 12 */
+#define LL_RCC_PLLSAI1M_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 13 */
+#define LL_RCC_PLLSAI1M_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 14 */
+#define LL_RCC_PLLSAI1M_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 15 */
+#define LL_RCC_PLLSAI1M_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 16 */
+/**
+ * @}
+ */
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
+
+#if defined(RCC_PLLSAI1_SUPPORT)
+/** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q)
+ * @{
+ */
+#define LL_RCC_PLLSAI1Q_DIV_2 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */
+#define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */
+#define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */
+#define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q) /*!< PLLSAI1 division factor for PLLSAI1Q output by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLSAI1P)
+ * @{
+ */
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+#define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 2 */
+#define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 3 */
+#define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 4 */
+#define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 5 */
+#define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 6 */
+#define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */
+#define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 8 */
+#define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 9 */
+#define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 10 */
+#define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 1 */
+#define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 12 */
+#define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 13 */
+#define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 14 */
+#define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 15 */
+#define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 16 */
+#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */
+#define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 18 */
+#define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 19 */
+#define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 20 */
+#define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division fctor for PLLSAI1P output by 21 */
+#define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 22 */
+#define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 23 */
+#define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 24 */
+#define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 25 */
+#define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 26 */
+#define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 27 */
+#define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 28 */
+#define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 29 */
+#define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 30 */
+#define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */
+#else
+#define LL_RCC_PLLSAI1P_DIV_7 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */
+#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */
+#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLSAI1R)
+ * @{
+ */
+#define LL_RCC_PLLSAI1R_DIV_2 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */
+#define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */
+#define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */
+#define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R) /*!< PLLSAI1 division factor for PLLSAI1R output by 8 */
+/**
+ * @}
+ */
+#endif /* RCC_PLLSAI1_SUPPORT */
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
+/** @defgroup RCC_LL_EC_PLLSAI2M PLLSAI1 division factor (PLLSAI2M)
+ * @{
+ */
+#define LL_RCC_PLLSAI2M_DIV_1 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2M input by 1 */
+#define LL_RCC_PLLSAI2M_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 2 */
+#define LL_RCC_PLLSAI2M_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 3 */
+#define LL_RCC_PLLSAI2M_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 4 */
+#define LL_RCC_PLLSAI2M_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 5 */
+#define LL_RCC_PLLSAI2M_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 6 */
+#define LL_RCC_PLLSAI2M_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 7 */
+#define LL_RCC_PLLSAI2M_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 8 */
+#define LL_RCC_PLLSAI2M_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2M_3) /*!< PLLSAI2 division factor for PLLSAI2M input by 9 */
+#define LL_RCC_PLLSAI2M_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 10 */
+#define LL_RCC_PLLSAI2M_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 11 */
+#define LL_RCC_PLLSAI2M_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 12 */
+#define LL_RCC_PLLSAI2M_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 13 */
+#define LL_RCC_PLLSAI2M_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 14 */
+#define LL_RCC_PLLSAI2M_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 15 */
+#define LL_RCC_PLLSAI2M_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 16 */
+/**
+ * @}
+ */
+#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
+
+#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
+/** @defgroup RCC_LL_EC_PLLSAI2Q PLLSAI2 division factor (PLLSAI2Q)
+ * @{
+ */
+#define LL_RCC_PLLSAI2Q_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2Q output by 2 */
+#define LL_RCC_PLLSAI2Q_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2Q_0) /*!< PLLSAI2 division factor for PLLSAI2Q output by 4 */
+#define LL_RCC_PLLSAI2Q_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2Q_1) /*!< PLLSAI2 division factor for PLLSAI2Q output by 6 */
+#define LL_RCC_PLLSAI2Q_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2Q) /*!< PLLSAI2 division factor for PLLSAI2Q output by 8 */
+/**
+ * @}
+ */
+#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
+
+/** @defgroup RCC_LL_EC_PLLSAI2P PLLSAI2 division factor (PLLSAI2P)
+ * @{
+ */
+#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
+#define LL_RCC_PLLSAI2P_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 2 */
+#define LL_RCC_PLLSAI2P_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 3 */
+#define LL_RCC_PLLSAI2P_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 4 */
+#define LL_RCC_PLLSAI2P_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 5 */
+#define LL_RCC_PLLSAI2P_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 6 */
+#define LL_RCC_PLLSAI2P_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */
+#define LL_RCC_PLLSAI2P_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 8 */
+#define LL_RCC_PLLSAI2P_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 9 */
+#define LL_RCC_PLLSAI2P_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 10 */
+#define LL_RCC_PLLSAI2P_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 1 */
+#define LL_RCC_PLLSAI2P_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 12 */
+#define LL_RCC_PLLSAI2P_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 13 */
+#define LL_RCC_PLLSAI2P_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 14 */
+#define LL_RCC_PLLSAI2P_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 15 */
+#define LL_RCC_PLLSAI2P_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4) /*!< PLLSAI2 division factor for PLLSAI2P output by 16 */
+#define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */
+#define LL_RCC_PLLSAI2P_DIV_18 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 18 */
+#define LL_RCC_PLLSAI2P_DIV_19 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 19 */
+#define LL_RCC_PLLSAI2P_DIV_20 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 20 */
+#define LL_RCC_PLLSAI2P_DIV_21 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division fctor for PLLSAI2P output by 21 */
+#define LL_RCC_PLLSAI2P_DIV_22 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 22 */
+#define LL_RCC_PLLSAI2P_DIV_23 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 23 */
+#define LL_RCC_PLLSAI2P_DIV_24 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 24 */
+#define LL_RCC_PLLSAI2P_DIV_25 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 25 */
+#define LL_RCC_PLLSAI2P_DIV_26 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 26 */
+#define LL_RCC_PLLSAI2P_DIV_27 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 27 */
+#define LL_RCC_PLLSAI2P_DIV_28 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 28 */
+#define LL_RCC_PLLSAI2P_DIV_29 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 29 */
+#define LL_RCC_PLLSAI2P_DIV_30 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 30 */
+#define LL_RCC_PLLSAI2P_DIV_31 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */
+#else
+#define LL_RCC_PLLSAI2P_DIV_7 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */
+#define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */
+#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLLSAI2R PLLSAI2 division factor (PLLSAI2R)
+ * @{
+ */
+#define LL_RCC_PLLSAI2R_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2R output by 2 */
+#define LL_RCC_PLLSAI2R_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2R_0) /*!< PLLSAI2 division factor for PLLSAI2R output by 4 */
+#define LL_RCC_PLLSAI2R_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2R_1) /*!< PLLSAI2 division factor for PLLSAI2R output by 6 */
+#define LL_RCC_PLLSAI2R_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2R) /*!< PLLSAI2 division factor for PLLSAI2R output by 8 */
+/**
+ * @}
+ */
+
+#if defined(RCC_CCIPR2_PLLSAI2DIVR)
+/** @defgroup RCC_LL_EC_PLLSAI2DIVR PLLSAI2DIVR division factor (PLLSAI2DIVR)
+ * @{
+ */
+#define LL_RCC_PLLSAI2DIVR_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 2 */
+#define LL_RCC_PLLSAI2DIVR_DIV_4 RCC_CCIPR2_PLLSAI2DIVR_0 /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 4 */
+#define LL_RCC_PLLSAI2DIVR_DIV_8 RCC_CCIPR2_PLLSAI2DIVR_1 /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 8 */
+#define LL_RCC_PLLSAI2DIVR_DIV_16 (RCC_CCIPR2_PLLSAI2DIVR_1 | RCC_CCIPR2_PLLSAI2DIVR_0) /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 16 */
+/**
+ * @}
+ */
+#endif /* RCC_CCIPR2_PLLSAI2DIVR */
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection
+ * @{
+ */
+#define LL_RCC_MSIRANGESEL_STANDBY 0U /*!< MSI Range is provided by MSISRANGE */
+#define LL_RCC_MSIRANGESEL_RUN 1U /*!< MSI Range is provided by MSIRANGE */
+/**
+ * @}
+ */
+
+#if defined(RCC_CSR_LSIPREDIV)
+/** @defgroup RCC_LL_EC_LSIPREDIV LSI division factor
+ * @{
+ */
+#define LL_RCC_LSI_PREDIV_1 0x00000000U /*!< LSI division factor by 1 */
+#define LL_RCC_LSI_PREDIV_128 RCC_CSR_LSIPREDIV /*!< LSI division factor by 128 */
+/**
+ * @}
+ */
+#endif /* RCC_CSR_LSIPREDIV */
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+*/
+#if defined(DFSDM1_Channel0)
+#define LL_RCC_DFSDM1_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+#define LL_RCC_DFSDM_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+#define LL_RCC_DFSDM_CLKSOURCE_SYSCLK LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+#define LL_RCC_DFSDM_CLKSOURCE LL_RCC_DFSDM1_CLKSOURCE
+#endif /* DFSDM1_Channel0 */
+#if defined(SWPMI1)
+#define LL_RCC_SWPMI1_CLKSOURCE_PCLK LL_RCC_SWPMI1_CLKSOURCE_PCLK1
+#endif /* SWPMI1 */
+/**
+@endcond
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+ * @{
+ */
+
+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in RCC register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in RCC register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+ * @{
+ */
+
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency on system domain
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_16 (*)
+ *
+ * (*) value not defined in all devices.
+ * @param __PLLN__ Between 8 and 86 or 127 depending on devices
+ * @param __PLLR__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLR_DIV_2
+ * @arg @ref LL_RCC_PLLR_DIV_4
+ * @arg @ref LL_RCC_PLLR_DIV_6
+ * @arg @ref LL_RCC_PLLR_DIV_8
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
+ ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
+
+#if defined(RCC_PLLSAI1_SUPPORT)
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_16 (*)
+ *
+ * (*) value not defined in all devices.
+ * @param __PLLN__ Between 8 and 86 or 127 depending on devices
+ * @param __PLLP__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLP_DIV_2
+ * @arg @ref LL_RCC_PLLP_DIV_3
+ * @arg @ref LL_RCC_PLLP_DIV_4
+ * @arg @ref LL_RCC_PLLP_DIV_5
+ * @arg @ref LL_RCC_PLLP_DIV_6
+ * @arg @ref LL_RCC_PLLP_DIV_7
+ * @arg @ref LL_RCC_PLLP_DIV_8
+ * @arg @ref LL_RCC_PLLP_DIV_9
+ * @arg @ref LL_RCC_PLLP_DIV_10
+ * @arg @ref LL_RCC_PLLP_DIV_11
+ * @arg @ref LL_RCC_PLLP_DIV_12
+ * @arg @ref LL_RCC_PLLP_DIV_13
+ * @arg @ref LL_RCC_PLLP_DIV_14
+ * @arg @ref LL_RCC_PLLP_DIV_15
+ * @arg @ref LL_RCC_PLLP_DIV_16
+ * @arg @ref LL_RCC_PLLP_DIV_17
+ * @arg @ref LL_RCC_PLLP_DIV_18
+ * @arg @ref LL_RCC_PLLP_DIV_19
+ * @arg @ref LL_RCC_PLLP_DIV_20
+ * @arg @ref LL_RCC_PLLP_DIV_21
+ * @arg @ref LL_RCC_PLLP_DIV_22
+ * @arg @ref LL_RCC_PLLP_DIV_23
+ * @arg @ref LL_RCC_PLLP_DIV_24
+ * @arg @ref LL_RCC_PLLP_DIV_25
+ * @arg @ref LL_RCC_PLLP_DIV_26
+ * @arg @ref LL_RCC_PLLP_DIV_27
+ * @arg @ref LL_RCC_PLLP_DIV_28
+ * @arg @ref LL_RCC_PLLP_DIV_29
+ * @arg @ref LL_RCC_PLLP_DIV_30
+ * @arg @ref LL_RCC_PLLP_DIV_31
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
+ ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))
+
+#else
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @param __PLLN__ Between 8 and 86
+ * @param __PLLP__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLP_DIV_7
+ * @arg @ref LL_RCC_PLLP_DIV_17
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
+ (((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7U : 17U))
+
+#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
+#endif /* RCC_PLLSAI1_SUPPORT */
+
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_16 (*)
+ *
+ * (*) value not defined in all devices.
+ * @param __PLLN__ Between 8 and 86 or 127 depending on devices
+ * @param __PLLQ__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLQ_DIV_2
+ * @arg @ref LL_RCC_PLLQ_DIV_4
+ * @arg @ref LL_RCC_PLLQ_DIV_6
+ * @arg @ref LL_RCC_PLLQ_DIV_8
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
+ ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
+
+#if defined(RCC_PLLSAI1_SUPPORT)
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
+ * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLSAI1M__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_16
+ * @param __PLLSAI1N__ Between 8 and 86 or 127 depending on devices
+ * @param __PLLSAI1P__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_16
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_17
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_18
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_19
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_20
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_21
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_22
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_23
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_24
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_25
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_26
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_27
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_28
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_29
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_30
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_31
+ * @retval PLLSAI1 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__) \
+ ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
+ ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
+
+#elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @param __PLLSAI1N__ Between 8 and 86 or 127 depending on devices
+ * @param __PLLSAI1P__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_16
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_17
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_18
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_19
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_20
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_21
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_22
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_23
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_24
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_25
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_26
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_27
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_28
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_29
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_30
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_31
+ * @retval PLLSAI1 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
+ ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
+ ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
+
+#else
+/**
+ * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @param __PLLSAI1N__ Between 8 and 86
+ * @param __PLLSAI1P__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_17
+ * @retval PLLSAI1 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
+ ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
+ (((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7U : 17U))
+
+#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
+
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
+ * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLSAI1M__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_16
+ * @param __PLLSAI1N__ Between 8 and 86 or 127 depending on devices
+ * @param __PLLSAI1Q__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
+ * @retval PLLSAI1 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1Q__) \
+ ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
+ ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
+
+#else
+/**
+ * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @param __PLLSAI1N__ Between 8 and 86
+ * @param __PLLSAI1Q__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
+ * @retval PLLSAI1 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) \
+ ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
+ ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
+
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
+
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
+ * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLSAI1M__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_16
+ * @param __PLLSAI1N__ Between 8 and 86 or 127 depending on devices
+ * @param __PLLSAI1R__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_8
+ * @retval PLLSAI1 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1R__) \
+ ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
+ ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
+
+#else
+/**
+ * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @param __PLLSAI1N__ Between 8 and 86
+ * @param __PLLSAI1R__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_8
+ * @retval PLLSAI1 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) \
+ ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
+ ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
+
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
+#endif /* RCC_PLLSAI1_SUPPORT */
+
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
+ * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLSAI2M__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_16
+ * @param __PLLSAI2N__ Between 8 and 86 or 127 depending on devices
+ * @param __PLLSAI2P__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_16
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_17
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_18
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_19
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_20
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_21
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_22
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_23
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_24
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_25
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_26
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_27
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_28
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_29
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_30
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_31
+ * @retval PLLSAI2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \
+ ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
+ ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
+
+#elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @param __PLLSAI2N__ Between 8 and 86 or 127 depending on devices
+ * @param __PLLSAI2P__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_16
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_17
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_18
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_19
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_20
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_21
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_22
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_23
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_24
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_25
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_26
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_27
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_28
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_29
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_30
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_31
+ * @retval PLLSAI2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \
+ ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \
+ ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
+
+#else
+/**
+ * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @param __PLLSAI2N__ Between 8 and 86
+ * @param __PLLSAI2P__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_17
+ * @retval PLLSAI2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \
+ ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1)) * (__PLLSAI2N__) / \
+ (((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7U : 17U))
+
+#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
+
+#if defined(LTDC)
+/**
+ * @brief Helper macro to calculate the PLLSAI2 frequency used for LTDC domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI2_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
+ * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR (), @ref LL_RCC_PLLSAI2_GetDIVR ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI)
+ * @param __PLLSAI2M__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_16
+ * @param __PLLSAI2N__ Between 8 and 127
+ * @param __PLLSAI2R__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_8
+ * @param __PLLSAI2DIVR__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
+ * @retval PLLSAI2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2R__, __PLLSAI2DIVR__) \
+ (((__INPUTFREQ__) / (((__PLLSAI2M__)>> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
+ (((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U) * (2UL << ((__PLLSAI2DIVR__) >> RCC_CCIPR2_PLLSAI2DIVR_Pos))))
+#elif defined(RCC_PLLSAI2_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLSAI2 frequency used on ADC domain
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @param __PLLSAI2N__ Between 8 and 86
+ * @param __PLLSAI2R__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_8
+ * @retval PLLSAI2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__) \
+ ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \
+ ((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U))
+
+#endif /* LTDC */
+
+#if defined(DSI)
+/**
+ * @brief Helper macro to calculate the PLLDSICLK frequency used on DSI
+ * @note ex: @ref __LL_RCC_CALC_PLLSAI2_DSI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
+ * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetQ ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI)
+ * @param __PLLSAI2M__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_16
+ * @param __PLLSAI2N__ Between 8 and 127
+ * @param __PLLSAI2Q__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_8
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLSAI2_DSI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2Q__) \
+ ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
+ ((((__PLLSAI2Q__) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) << 1U))
+#endif /* DSI */
+
+
+
+/**
+ * @brief Helper macro to calculate the HCLK frequency
+ * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
+ * @param __AHBPRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ * @retval HCLK clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
+
+/**
+ * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
+ * @param __HCLKFREQ__ HCLK frequency
+ * @param __APB1PRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ * @retval PCLK1 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
+
+/**
+ * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
+ * @param __HCLKFREQ__ HCLK frequency
+ * @param __APB2PRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ * @retval PCLK2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
+
+/**
+ * @brief Helper macro to calculate the MSI frequency (in Hz)
+ * @note __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect()
+ * @note if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY,
+ * __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby()
+ * else by LL_RCC_MSI_GetRange()
+ * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ * (LL_RCC_MSI_IsEnabledRangeSelect()?
+ * LL_RCC_MSI_GetRange():
+ * LL_RCC_MSI_GetRangeAfterStandby()))
+ * @param __MSISEL__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MSIRANGESEL_STANDBY
+ * @arg @ref LL_RCC_MSIRANGESEL_RUN
+ * @param __MSIRANGE__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MSIRANGE_0
+ * @arg @ref LL_RCC_MSIRANGE_1
+ * @arg @ref LL_RCC_MSIRANGE_2
+ * @arg @ref LL_RCC_MSIRANGE_3
+ * @arg @ref LL_RCC_MSIRANGE_4
+ * @arg @ref LL_RCC_MSIRANGE_5
+ * @arg @ref LL_RCC_MSIRANGE_6
+ * @arg @ref LL_RCC_MSIRANGE_7
+ * @arg @ref LL_RCC_MSIRANGE_8
+ * @arg @ref LL_RCC_MSIRANGE_9
+ * @arg @ref LL_RCC_MSIRANGE_10
+ * @arg @ref LL_RCC_MSIRANGE_11
+ * @arg @ref LL_RCC_MSISRANGE_4
+ * @arg @ref LL_RCC_MSISRANGE_5
+ * @arg @ref LL_RCC_MSISRANGE_6
+ * @arg @ref LL_RCC_MSISRANGE_7
+ * @retval MSI clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
+ (MSIRangeTable[(__MSIRANGE__) >> 8U]) : \
+ (MSIRangeTable[(__MSIRANGE__) >> 4U]))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+ * @{
+ */
+
+/** @defgroup RCC_LL_EF_HSE HSE
+ * @{
+ */
+
+/**
+ * @brief Enable the Clock Security System.
+ * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+ * @brief Enable HSE external oscillator (HSE Bypass)
+ * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+ * @brief Disable HSE external oscillator (HSE Bypass)
+ * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+ * @brief Enable HSE crystal oscillator (HSE ON)
+ * @rmtoll CR HSEON LL_RCC_HSE_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+ * @brief Disable HSE crystal oscillator (HSE ON)
+ * @rmtoll CR HSEON LL_RCC_HSE_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+ * @brief Check if HSE oscillator Ready
+ * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_HSI HSI
+ * @{
+ */
+
+/**
+ * @brief Enable HSI even in stop mode
+ * @note HSI oscillator is forced ON even in Stop mode
+ * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSIKERON);
+}
+
+/**
+ * @brief Disable HSI in stop mode
+ * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
+}
+
+/**
+ * @brief Check if HSI is enabled in stop mode
+ * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable HSI oscillator
+ * @rmtoll CR HSION LL_RCC_HSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+ * @brief Disable HSI oscillator
+ * @rmtoll CR HSION LL_RCC_HSI_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+ * @brief Check if HSI clock is ready
+ * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable HSI Automatic from stop mode
+ * @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSIASFS);
+}
+
+/**
+ * @brief Disable HSI Automatic from stop mode
+ * @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
+}
+/**
+ * @brief Get HSI Calibration value
+ * @note When HSITRIM is written, HSICAL is updated with the sum of
+ * HSITRIM and the factory trim value
+ * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
+ * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
+{
+ return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
+}
+
+/**
+ * @brief Set HSI Calibration trimming
+ * @note user-programmable trimming value that is added to the HSICAL
+ * @note Default value is 16 on STM32L43x/STM32L44x/STM32L47x/STM32L48x or 64 on other devices,
+ * which, when added to the HSICAL value, should trim the HSI to 16 MHz +/- 1 %
+ * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
+ * @param Value Between Min_Data = 0 and Max_Data = 31 on STM32L43x/STM32L44x/STM32L47x/STM32L48x or
+ * between Min_Data = 0 and Max_Data = 127 on other devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
+{
+ MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
+}
+
+/**
+ * @brief Get HSI Calibration trimming
+ * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
+ * @retval Between Min_Data = 0 and Max_Data = 31 on STM32L43x/STM32L44x/STM32L47x/STM32L48x or
+ * between Min_Data = 0 and Max_Data = 127 on other devices
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
+{
+ return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
+}
+
+/**
+ * @}
+ */
+
+#if defined(RCC_HSI48_SUPPORT)
+/** @defgroup RCC_LL_EF_HSI48 HSI48
+ * @{
+ */
+
+/**
+ * @brief Enable HSI48
+ * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
+{
+ SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
+}
+
+/**
+ * @brief Disable HSI48
+ * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
+{
+ CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
+}
+
+/**
+ * @brief Check if HSI48 oscillator Ready
+ * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
+{
+ return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RCC_CRRCR_HSI48RDY) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get HSI48 Calibration value
+ * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
+ * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
+}
+
+/**
+ * @}
+ */
+#endif /* RCC_HSI48_SUPPORT */
+
+/** @defgroup RCC_LL_EF_LSE LSE
+ * @{
+ */
+
+/**
+ * @brief Enable Low Speed External (LSE) crystal.
+ * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_Enable(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+ * @brief Disable Low Speed External (LSE) crystal.
+ * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_Disable(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+ * @brief Enable external clock source (LSE bypass).
+ * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+ * @brief Disable external clock source (LSE bypass).
+ * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+ * @brief Set LSE oscillator drive capability
+ * @note The oscillator is in Xtal mode when it is not in bypass mode.
+ * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
+ * @param LSEDrive This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LSEDRIVE_LOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+ * @arg @ref LL_RCC_LSEDRIVE_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
+{
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
+}
+
+/**
+ * @brief Get LSE oscillator drive capability
+ * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_LSEDRIVE_LOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+ * @arg @ref LL_RCC_LSEDRIVE_HIGH
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
+{
+ return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
+}
+
+/**
+ * @brief Enable Clock security system on LSE.
+ * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
+}
+
+/**
+ * @brief Disable Clock security system on LSE.
+ * @note Clock security system can be disabled only after a LSE
+ * failure detection. In that case it MUST be disabled by software.
+ * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
+}
+
+/**
+ * @brief Check if LSE oscillator Ready
+ * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
+{
+ return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if CSS on LSE failure Detection
+ * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
+{
+ return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL);
+}
+
+#if defined(RCC_BDCR_LSESYSDIS)
+/**
+ * @brief Disable LSE oscillator propagation
+ * @note LSE clock is not propagated to any peripheral except to RTC which remains clocked
+ * @note A 2 LSE-clock delay is needed for LSESYSDIS setting to be taken into account
+ * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_DisablePropagation
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
+}
+
+/**
+ * @brief Enable LSE oscillator propagation
+ * @note A 2 LSE-clock delay is needed for LSESYSDIS resetting to be taken into account
+ * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_EnablePropagation
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
+}
+
+/**
+ * @brief Check if LSE oscillator propagation is enabled
+ * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_IsPropagationEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationEnabled(void)
+{
+ return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS) == 0U) ? 1UL : 0UL);
+}
+#endif /* RCC_BDCR_LSESYSDIS */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_LSI LSI
+ * @{
+ */
+
+/**
+ * @brief Enable LSI Oscillator
+ * @rmtoll CSR LSION LL_RCC_LSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSI_Enable(void)
+{
+ SET_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+ * @brief Disable LSI Oscillator
+ * @rmtoll CSR LSION LL_RCC_LSI_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSI_Disable(void)
+{
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+ * @brief Check if LSI is Ready
+ * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
+{
+ return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) ? 1UL : 0UL);
+}
+
+#if defined(RCC_CSR_LSIPREDIV)
+/**
+ * @brief Set LSI division factor
+ * @rmtoll CSR LSIPREDIV LL_RCC_LSI_SetPrediv
+ * @param LSI_PREDIV This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LSI_PREDIV_1
+ * @arg @ref LL_RCC_LSI_PREDIV_128
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSI_SetPrediv(uint32_t LSI_PREDIV)
+{
+ MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, LSI_PREDIV);
+}
+
+/**
+ * @brief Get LSI division factor
+ * @rmtoll CSR LSIPREDIV LL_RCC_LSI_GetPrediv
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_LSI_PREDIV_1
+ * @arg @ref LL_RCC_LSI_PREDIV_128
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSI_GetPrediv(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_LSIPREDIV));
+}
+#endif /* RCC_CSR_LSIPREDIV */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_MSI MSI
+ * @{
+ */
+
+/**
+ * @brief Enable MSI oscillator
+ * @rmtoll CR MSION LL_RCC_MSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSI_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_MSION);
+}
+
+/**
+ * @brief Disable MSI oscillator
+ * @rmtoll CR MSION LL_RCC_MSI_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSI_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_MSION);
+}
+
+/**
+ * @brief Check if MSI oscillator Ready
+ * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE)
+ * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
+ * and ready (LSERDY set by hardware)
+ * @note hardware protection to avoid enabling MSIPLLEN if LSE is not
+ * ready
+ * @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
+}
+
+/**
+ * @brief Disable MSI-PLL mode
+ * @note cleared by hardware when LSE is disabled (LSEON = 0) or when
+ * the Clock Security System on LSE detects a LSE failure
+ * @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
+}
+
+/**
+ * @brief Enable MSI clock range selection with MSIRANGE register
+ * @note Write 0 has no effect. After a standby or a reset
+ * MSIRGSEL is at 0 and the MSI range value is provided by
+ * MSISRANGE
+ * @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
+}
+
+/**
+ * @brief Check if MSI clock range is selected with MSIRANGE register
+ * @rmtoll CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RCC_CR_MSIRGSEL) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
+ * @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange
+ * @param Range This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MSIRANGE_0
+ * @arg @ref LL_RCC_MSIRANGE_1
+ * @arg @ref LL_RCC_MSIRANGE_2
+ * @arg @ref LL_RCC_MSIRANGE_3
+ * @arg @ref LL_RCC_MSIRANGE_4
+ * @arg @ref LL_RCC_MSIRANGE_5
+ * @arg @ref LL_RCC_MSIRANGE_6
+ * @arg @ref LL_RCC_MSIRANGE_7
+ * @arg @ref LL_RCC_MSIRANGE_8
+ * @arg @ref LL_RCC_MSIRANGE_9
+ * @arg @ref LL_RCC_MSIRANGE_10
+ * @arg @ref LL_RCC_MSIRANGE_11
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
+{
+ MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
+}
+
+/**
+ * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
+ * @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_MSIRANGE_0
+ * @arg @ref LL_RCC_MSIRANGE_1
+ * @arg @ref LL_RCC_MSIRANGE_2
+ * @arg @ref LL_RCC_MSIRANGE_3
+ * @arg @ref LL_RCC_MSIRANGE_4
+ * @arg @ref LL_RCC_MSIRANGE_5
+ * @arg @ref LL_RCC_MSIRANGE_6
+ * @arg @ref LL_RCC_MSIRANGE_7
+ * @arg @ref LL_RCC_MSIRANGE_8
+ * @arg @ref LL_RCC_MSIRANGE_9
+ * @arg @ref LL_RCC_MSIRANGE_10
+ * @arg @ref LL_RCC_MSIRANGE_11
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE));
+}
+
+/**
+ * @brief Configure MSI range used after standby
+ * @rmtoll CSR MSISRANGE LL_RCC_MSI_SetRangeAfterStandby
+ * @param Range This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MSISRANGE_4
+ * @arg @ref LL_RCC_MSISRANGE_5
+ * @arg @ref LL_RCC_MSISRANGE_6
+ * @arg @ref LL_RCC_MSISRANGE_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)
+{
+ MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range);
+}
+
+/**
+ * @brief Get MSI range used after standby
+ * @rmtoll CSR MSISRANGE LL_RCC_MSI_GetRangeAfterStandby
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_MSISRANGE_4
+ * @arg @ref LL_RCC_MSISRANGE_5
+ * @arg @ref LL_RCC_MSISRANGE_6
+ * @arg @ref LL_RCC_MSISRANGE_7
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE));
+}
+
+/**
+ * @brief Get MSI Calibration value
+ * @note When MSITRIM is written, MSICAL is updated with the sum of
+ * MSITRIM and the factory trim value
+ * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
+ * @retval Between Min_Data = 0 and Max_Data = 255
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
+{
+ return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
+}
+
+/**
+ * @brief Set MSI Calibration trimming
+ * @note user-programmable trimming value that is added to the MSICAL
+ * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
+ * @param Value Between Min_Data = 0 and Max_Data = 255
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
+{
+ MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
+}
+
+/**
+ * @brief Get MSI Calibration trimming
+ * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
+ * @retval Between 0 and 255
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
+{
+ return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_LSCO LSCO
+ * @{
+ */
+
+/**
+ * @brief Enable Low speed clock
+ * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSCO_Enable(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
+}
+
+/**
+ * @brief Disable Low speed clock
+ * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSCO_Disable(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
+}
+
+/**
+ * @brief Configure Low speed clock selection
+ * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
+}
+
+/**
+ * @brief Get Low speed clock selection
+ * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_System System
+ * @{
+ */
+
+/**
+ * @brief Configure the system clock source
+ * @rmtoll CFGR SW LL_RCC_SetSysClkSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+}
+
+/**
+ * @brief Get the system clock source
+ * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+}
+
+/**
+ * @brief Set AHB prescaler
+ * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+}
+
+/**
+ * @brief Set APB1 prescaler
+ * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
+}
+
+/**
+ * @brief Set APB2 prescaler
+ * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
+}
+
+/**
+ * @brief Get AHB prescaler
+ * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
+}
+
+/**
+ * @brief Get APB1 prescaler
+ * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
+}
+
+/**
+ * @brief Get APB2 prescaler
+ * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
+}
+
+/**
+ * @brief Set Clock After Wake-Up From Stop mode
+ * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
+ * @param Clock This parameter can be one of the following values:
+ * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
+ * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
+}
+
+/**
+ * @brief Get Clock After Wake-Up From Stop mode
+ * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
+ * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_MCO MCO
+ * @{
+ */
+
+/**
+ * @brief Configure MCOx
+ * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
+ * CFGR MCOPRE LL_RCC_ConfigMCO
+ * @param MCOxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
+ * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
+ * @arg @ref LL_RCC_MCO1SOURCE_MSI
+ * @arg @ref LL_RCC_MCO1SOURCE_HSI
+ * @arg @ref LL_RCC_MCO1SOURCE_HSE
+ * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
+ * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
+ * @arg @ref LL_RCC_MCO1SOURCE_LSI
+ * @arg @ref LL_RCC_MCO1SOURCE_LSE
+ *
+ * (*) value not defined in all devices.
+ * @param MCOxPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MCO1_DIV_1
+ * @arg @ref LL_RCC_MCO1_DIV_2
+ * @arg @ref LL_RCC_MCO1_DIV_4
+ * @arg @ref LL_RCC_MCO1_DIV_8
+ * @arg @ref LL_RCC_MCO1_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+ * @{
+ */
+
+/**
+ * @brief Configure USARTx clock source
+ * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
+ * @param USARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
+{
+ MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
+}
+
+#if defined(UART4) || defined(UART5)
+/**
+ * @brief Configure UARTx clock source
+ * @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource
+ * @param UARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
+{
+ MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
+}
+#endif /* UART4 || UART5 */
+
+/**
+ * @brief Configure LPUART1x clock source
+ * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
+ * @param LPUARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
+{
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
+}
+
+/**
+ * @brief Configure I2Cx clock source
+ * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
+ * @param I2CxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
+{
+ __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
+ MODIFY_REG(*reg, 3UL << ((I2CxSource & 0x001F0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x001F0000U) >> 16U)));
+}
+
+/**
+ * @brief Configure LPTIMx clock source
+ * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
+ * @param LPTIMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
+{
+ MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U));
+}
+
+#if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL)
+/**
+ * @brief Configure SAIx clock source
+ @if STM32L4S9xx
+ * @rmtoll CCIPR2 SAIxSEL LL_RCC_SetSAIClockSource
+ @else
+ * @rmtoll CCIPR SAIxSEL LL_RCC_SetSAIClockSource
+ @endif
+ * @param SAIxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
+{
+#if defined(RCC_CCIPR2_SAI1SEL)
+ MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU));
+#else
+ MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
+#endif /* RCC_CCIPR2_SAI1SEL */
+}
+#endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */
+
+#if defined(RCC_CCIPR2_SDMMCSEL)
+/**
+ * @brief Configure SDMMC1 kernel clock source
+ * @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource
+ * @param SDMMCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*)
+ * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource)
+{
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource);
+}
+#endif /* RCC_CCIPR2_SDMMCSEL */
+
+/**
+ * @brief Configure SDMMC1 clock source
+ * @rmtoll CCIPR CLK48SEL LL_RCC_SetSDMMCClockSource
+ * @param SDMMCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)
+ * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)
+ * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)
+ * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
+{
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource);
+}
+
+/**
+ * @brief Configure RNG clock source
+ * @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource
+ * @param RNGxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*)
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*)
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 (*)
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
+{
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
+}
+
+#if defined(USB_OTG_FS) || defined(USB)
+/**
+ * @brief Configure USB clock source
+ * @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
+ * @param USBxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
+{
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
+}
+#endif /* USB_OTG_FS || USB */
+
+#if defined(RCC_CCIPR_ADCSEL)
+/**
+ * @brief Configure ADC clock source
+ * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
+ * @param ADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*)
+ * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
+ * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
+{
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
+}
+#endif /* RCC_CCIPR_ADCSEL */
+
+#if defined(SWPMI1)
+/**
+ * @brief Configure SWPMI clock source
+ * @rmtoll CCIPR SWPMI1SEL LL_RCC_SetSWPMIClockSource
+ * @param SWPMIxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource)
+{
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, SWPMIxSource);
+}
+#endif /* SWPMI1 */
+
+#if defined(DFSDM1_Channel0)
+#if defined(RCC_CCIPR2_ADFSDM1SEL)
+/**
+ * @brief Configure DFSDM Audio clock source
+ * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, Source);
+}
+#endif /* RCC_CCIPR2_ADFSDM1SEL */
+
+/**
+ * @brief Configure DFSDM Kernel clock source
+ @if STM32L4S9xx
+ * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_SetDFSDMClockSource
+ @else
+ * @rmtoll CCIPR DFSDM1SEL LL_RCC_SetDFSDMClockSource
+ @endif
+ * @param DFSDMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)
+{
+#if defined(RCC_CCIPR2_DFSDM1SEL)
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, DFSDMxSource);
+#else
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource);
+#endif /* RCC_CCIPR2_DFSDM1SEL */
+}
+#endif /* DFSDM1_Channel0 */
+
+#if defined(DSI)
+/**
+ * @brief Configure DSI clock source
+ * @rmtoll CCIPR2 DSISEL LL_RCC_SetDSIClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+ * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, Source);
+}
+#endif /* DSI */
+
+#if defined(LTDC)
+/**
+ * @brief Configure LTDC Clock Source
+ * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_SetLTDCClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, Source);
+}
+#endif /* LTDC */
+
+#if defined(OCTOSPI1)
+/**
+ * @brief Configure OCTOSPI clock source
+ * @rmtoll CCIPR2 OSPISEL LL_RCC_SetOCTOSPIClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, Source);
+}
+#endif /* OCTOSPI1 */
+
+/**
+ * @brief Get USARTx clock source
+ * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
+ * @param USARTx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE
+ * @arg @ref LL_RCC_USART2_CLKSOURCE
+ * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
+}
+
+#if defined(UART4) || defined(UART5)
+/**
+ * @brief Get UARTx clock source
+ * @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource
+ * @param UARTx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_UART4_CLKSOURCE
+ * @arg @ref LL_RCC_UART5_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16U));
+}
+#endif /* UART4 || UART5 */
+
+/**
+ * @brief Get LPUARTx clock source
+ * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
+ * @param LPUARTx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
+}
+
+/**
+ * @brief Get I2Cx clock source
+ * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
+ * @param I2Cx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
+{
+ __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
+ return (uint32_t)((READ_BIT(*reg, 3UL << ((I2Cx & 0x001F0000U) >> 16U)) >> ((I2Cx & 0x001F0000U) >> 16U)) | (I2Cx & 0xFFFF0000U));
+}
+
+/**
+ * @brief Get LPTIMx clock source
+ * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
+ * @param LPTIMx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
+{
+ return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16U) | LPTIMx);
+}
+
+#if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL)
+/**
+ * @brief Get SAIx clock source
+ @if STM32L4S9xx
+ * @rmtoll CCIPR2 SAIxSEL LL_RCC_GetSAIClockSource
+ @else
+ * @rmtoll CCIPR SAIxSEL LL_RCC_GetSAIClockSource
+ @endif
+ * @param SAIx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
+{
+#if defined(RCC_CCIPR2_SAI1SEL)
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U));
+#else
+ return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16U | SAIx);
+#endif /* RCC_CCIPR2_SAI1SEL */
+}
+#endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */
+
+#if defined(SDMMC1)
+#if defined(RCC_CCIPR2_SDMMCSEL)
+/**
+ * @brief Get SDMMCx kernel clock source
+ * @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource
+ * @param SDMMCx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*)
+ * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLL (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx));
+}
+#endif /* RCC_CCIPR2_SDMMCSEL */
+
+/**
+ * @brief Get SDMMCx clock source
+ * @rmtoll CCIPR CLK48SEL LL_RCC_GetSDMMCClockSource
+ * @param SDMMCx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)
+ * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)
+ * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)
+ * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx));
+}
+#endif /* SDMMC1 */
+
+/**
+ * @brief Get RNGx clock source
+ * @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource
+ * @param RNGx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RNG_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*)
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*)
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 (*)
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
+}
+
+#if defined(USB_OTG_FS) || defined(USB)
+/**
+ * @brief Get USBx clock source
+ * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
+ * @param USBx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
+}
+#endif /* USB_OTG_FS || USB */
+
+/**
+ * @brief Get ADCx clock source
+ * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
+ * @param ADCx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*)
+ * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
+ * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
+{
+#if defined(RCC_CCIPR_ADCSEL)
+ return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
+#else
+ (void)ADCx; /* unused */
+ return ((READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U) ? LL_RCC_ADC_CLKSOURCE_SYSCLK : LL_RCC_ADC_CLKSOURCE_NONE);
+#endif /* RCC_CCIPR_ADCSEL */
+}
+
+#if defined(SWPMI1)
+/**
+ * @brief Get SWPMIx clock source
+ * @rmtoll CCIPR SWPMI1SEL LL_RCC_GetSWPMIClockSource
+ * @param SPWMIx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SWPMI1_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR, SPWMIx));
+}
+#endif /* SWPMI1 */
+
+#if defined(DFSDM1_Channel0)
+#if defined(RCC_CCIPR2_ADFSDM1SEL)
+/**
+ * @brief Get DFSDM Audio Clock Source
+ * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource
+ * @param DFSDMx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));
+}
+#endif /* RCC_CCIPR2_ADFSDM1SEL */
+
+/**
+ * @brief Get DFSDMx Kernel clock source
+ @if STM32L4S9xx
+ * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_GetDFSDMClockSource
+ @else
+ * @rmtoll CCIPR DFSDM1SEL LL_RCC_GetDFSDMClockSource
+ @endif
+ * @param DFSDMx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
+{
+#if defined(RCC_CCIPR2_DFSDM1SEL)
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));
+#else
+ return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx));
+#endif /* RCC_CCIPR2_DFSDM1SEL */
+}
+#endif /* DFSDM1_Channel0 */
+
+#if defined(DSI)
+/**
+ * @brief Get DSI Clock Source
+ * @rmtoll CCIPR2 DSISEL LL_RCC_GetDSIClockSource
+ * @param DSIx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DSI_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+ * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, DSIx));
+}
+#endif /* DSI */
+
+#if defined(LTDC)
+/**
+ * @brief Get LTDC Clock Source
+ * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_GetLTDCClockSource
+ * @param LTDCx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, LTDCx));
+}
+#endif /* LTDC */
+
+#if defined(OCTOSPI1)
+/**
+ * @brief Get OCTOSPI clock source
+ * @rmtoll CCIPR2 OSPISEL LL_RCC_GetOCTOSPIClockSource
+ * @param OCTOSPIx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx));
+}
+#endif /* OCTOSPI1 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_RTC RTC
+ * @{
+ */
+
+/**
+ * @brief Set RTC Clock Source
+ * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
+ * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
+ * set). The BDRST bit can be used to reset them.
+ * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
+}
+
+/**
+ * @brief Get RTC Clock Source
+ * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
+}
+
+/**
+ * @brief Enable RTC
+ * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableRTC(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+ * @brief Disable RTC
+ * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableRTC(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+ * @brief Check if RTC has been enabled or not
+ * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
+{
+ return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == RCC_BDCR_RTCEN) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Force the Backup domain reset
+ * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+ * @brief Release the Backup domain reset
+ * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_LL_EF_PLL PLL
+ * @{
+ */
+
+/**
+ * @brief Enable PLL
+ * @rmtoll CR PLLON LL_RCC_PLL_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+ * @brief Disable PLL
+ * @note Cannot be disabled if the PLL clock is used as the system clock
+ * @rmtoll CR PLLON LL_RCC_PLL_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+ * @brief Check if PLL Ready
+ * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure PLL used for SYSCLK Domain
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLN/PLLR can be written only when PLL is disabled.
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
+ * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
+ * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
+ * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_16 (*)
+ *
+ * (*) value not defined in all devices.
+ * @param PLLN Between 8 and 86 or 127 depending on devices
+ * @param PLLR This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLR_DIV_2
+ * @arg @ref LL_RCC_PLLR_DIV_4
+ * @arg @ref LL_RCC_PLLR_DIV_6
+ * @arg @ref LL_RCC_PLLR_DIV_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
+ Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
+}
+
+#if defined(RCC_PLLP_SUPPORT)
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
+/**
+ * @brief Configure PLL used for SAI domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLN/PLLP can be written only when PLL is disabled.
+ * @note This can be selected for SAI1 or SAI2 (*)
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
+ * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
+ * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
+ * PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_SAI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_16 (*)
+ *
+ * (*) value not defined in all devices.
+ * @param PLLN Between 8 and 86 or 127 depending on devices
+ * @param PLLP This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLP_DIV_2
+ * @arg @ref LL_RCC_PLLP_DIV_3
+ * @arg @ref LL_RCC_PLLP_DIV_4
+ * @arg @ref LL_RCC_PLLP_DIV_5
+ * @arg @ref LL_RCC_PLLP_DIV_6
+ * @arg @ref LL_RCC_PLLP_DIV_7
+ * @arg @ref LL_RCC_PLLP_DIV_8
+ * @arg @ref LL_RCC_PLLP_DIV_9
+ * @arg @ref LL_RCC_PLLP_DIV_10
+ * @arg @ref LL_RCC_PLLP_DIV_11
+ * @arg @ref LL_RCC_PLLP_DIV_12
+ * @arg @ref LL_RCC_PLLP_DIV_13
+ * @arg @ref LL_RCC_PLLP_DIV_14
+ * @arg @ref LL_RCC_PLLP_DIV_15
+ * @arg @ref LL_RCC_PLLP_DIV_16
+ * @arg @ref LL_RCC_PLLP_DIV_17
+ * @arg @ref LL_RCC_PLLP_DIV_18
+ * @arg @ref LL_RCC_PLLP_DIV_19
+ * @arg @ref LL_RCC_PLLP_DIV_20
+ * @arg @ref LL_RCC_PLLP_DIV_21
+ * @arg @ref LL_RCC_PLLP_DIV_22
+ * @arg @ref LL_RCC_PLLP_DIV_23
+ * @arg @ref LL_RCC_PLLP_DIV_24
+ * @arg @ref LL_RCC_PLLP_DIV_25
+ * @arg @ref LL_RCC_PLLP_DIV_26
+ * @arg @ref LL_RCC_PLLP_DIV_27
+ * @arg @ref LL_RCC_PLLP_DIV_28
+ * @arg @ref LL_RCC_PLLP_DIV_29
+ * @arg @ref LL_RCC_PLLP_DIV_30
+ * @arg @ref LL_RCC_PLLP_DIV_31
+ * @retval None
+ */
+#else
+/**
+ * @brief Configure PLL used for SAI domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLN/PLLP can be written only when PLL is disabled.
+ * @note This can be selected for SAI1 or SAI2 (*)
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
+ * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
+ * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
+ * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @param PLLN Between 8 and 86
+ * @param PLLP This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLP_DIV_7
+ * @arg @ref LL_RCC_PLLP_DIV_17
+ * @retval None
+ */
+#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV,
+ Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
+#else
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
+ Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
+#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
+}
+#endif /* RCC_PLLP_SUPPORT */
+
+/**
+ * @brief Configure PLL used for 48Mhz domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLN/PLLQ can be written only when PLL is disabled.
+ * @note This can be selected for USB, RNG, SDMMC
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
+ * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
+ * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
+ * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_16 (*)
+ *
+ * (*) value not defined in all devices.
+ * @param PLLN Between 8 and 86 or 127 depending on devices
+ * @param PLLQ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLQ_DIV_2
+ * @arg @ref LL_RCC_PLLQ_DIV_4
+ * @arg @ref LL_RCC_PLLQ_DIV_6
+ * @arg @ref LL_RCC_PLLQ_DIV_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
+ Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
+}
+
+/**
+ * @brief Configure PLL clock source
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
+ * @param PLLSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
+}
+
+/**
+ * @brief Get the oscillator used as PLL clock source.
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
+}
+
+/**
+ * @brief Get Main PLL multiplication factor for VCO
+ * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
+ * @retval Between 8 and 86 or 127 depending on devices
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+}
+
+#if defined(RCC_PLLP_SUPPORT)
+#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
+/**
+ * @brief Get Main PLL division factor for PLLP
+ * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock)
+ * @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLP_DIV_2
+ * @arg @ref LL_RCC_PLLP_DIV_3
+ * @arg @ref LL_RCC_PLLP_DIV_4
+ * @arg @ref LL_RCC_PLLP_DIV_5
+ * @arg @ref LL_RCC_PLLP_DIV_6
+ * @arg @ref LL_RCC_PLLP_DIV_7
+ * @arg @ref LL_RCC_PLLP_DIV_8
+ * @arg @ref LL_RCC_PLLP_DIV_9
+ * @arg @ref LL_RCC_PLLP_DIV_10
+ * @arg @ref LL_RCC_PLLP_DIV_11
+ * @arg @ref LL_RCC_PLLP_DIV_12
+ * @arg @ref LL_RCC_PLLP_DIV_13
+ * @arg @ref LL_RCC_PLLP_DIV_14
+ * @arg @ref LL_RCC_PLLP_DIV_15
+ * @arg @ref LL_RCC_PLLP_DIV_16
+ * @arg @ref LL_RCC_PLLP_DIV_17
+ * @arg @ref LL_RCC_PLLP_DIV_18
+ * @arg @ref LL_RCC_PLLP_DIV_19
+ * @arg @ref LL_RCC_PLLP_DIV_20
+ * @arg @ref LL_RCC_PLLP_DIV_21
+ * @arg @ref LL_RCC_PLLP_DIV_22
+ * @arg @ref LL_RCC_PLLP_DIV_23
+ * @arg @ref LL_RCC_PLLP_DIV_24
+ * @arg @ref LL_RCC_PLLP_DIV_25
+ * @arg @ref LL_RCC_PLLP_DIV_26
+ * @arg @ref LL_RCC_PLLP_DIV_27
+ * @arg @ref LL_RCC_PLLP_DIV_28
+ * @arg @ref LL_RCC_PLLP_DIV_29
+ * @arg @ref LL_RCC_PLLP_DIV_30
+ * @arg @ref LL_RCC_PLLP_DIV_31
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV));
+}
+#else
+/**
+ * @brief Get Main PLL division factor for PLLP
+ * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock)
+ * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLP_DIV_7
+ * @arg @ref LL_RCC_PLLP_DIV_17
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
+}
+#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
+#endif /* RCC_PLLP_SUPPORT */
+
+/**
+ * @brief Get Main PLL division factor for PLLQ
+ * @note Used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock)
+ * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLQ_DIV_2
+ * @arg @ref LL_RCC_PLLQ_DIV_4
+ * @arg @ref LL_RCC_PLLQ_DIV_6
+ * @arg @ref LL_RCC_PLLQ_DIV_8
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
+}
+
+/**
+ * @brief Get Main PLL division factor for PLLR
+ * @note Used for PLLCLK (system clock)
+ * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLR_DIV_2
+ * @arg @ref LL_RCC_PLLR_DIV_4
+ * @arg @ref LL_RCC_PLLR_DIV_6
+ * @arg @ref LL_RCC_PLLR_DIV_8
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
+}
+
+/**
+ * @brief Get Division factor for the main PLL and other PLL
+ * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @arg @ref LL_RCC_PLLM_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLM_DIV_16 (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
+}
+
+#if defined(RCC_PLLP_SUPPORT)
+/**
+ * @brief Enable PLL output mapped on SAI domain clock
+ * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
+{
+ SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
+}
+
+/**
+ * @brief Disable PLL output mapped on SAI domain clock
+ * @note Cannot be disabled if the PLL clock is used as the system
+ * clock
+ * @note In order to save power, when the PLLCLK of the PLL is
+ * not used, should be 0
+ * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
+{
+ CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
+}
+
+/**
+ * @brief Check if PLL output mapped on SAI domain clock is enabled
+ * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_SAI
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SAI(void)
+{
+ return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
+}
+
+#endif /* RCC_PLLP_SUPPORT */
+
+/**
+ * @brief Enable PLL output mapped on 48MHz domain clock
+ * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
+{
+ SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
+}
+
+/**
+ * @brief Disable PLL output mapped on 48MHz domain clock
+ * @note Cannot be disabled if the PLL clock is used as the system
+ * clock
+ * @note In order to save power, when the PLLCLK of the PLL is
+ * not used, should be 0
+ * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
+{
+ CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
+}
+
+/**
+ * @brief Check if PLL output mapped on 48MHz domain clock is enabled
+ * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_48M
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_48M(void)
+{
+ return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable PLL output mapped on SYSCLK domain
+ * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
+{
+ SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
+}
+
+/**
+ * @brief Disable PLL output mapped on SYSCLK domain
+ * @note Cannot be disabled if the PLL clock is used as the system
+ * clock
+ * @note In order to save power, when the PLLCLK of the PLL is
+ * not used, Main PLL should be 0
+ * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
+{
+ CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
+}
+
+/**
+ * @brief Check if PLL output mapped on SYSCLK domain clock is enabled
+ * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void)
+{
+ return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+#if defined(RCC_PLLSAI1_SUPPORT)
+/** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1
+ * @{
+ */
+
+/**
+ * @brief Enable PLLSAI1
+ * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
+}
+
+/**
+ * @brief Disable PLLSAI1
+ * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
+}
+
+/**
+ * @brief Check if PLLSAI1 Ready
+ * @rmtoll CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RCC_CR_PLLSAI1RDY) ? 1UL : 0UL);
+}
+
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
+/**
+ * @brief Configure PLLSAI1 used for 48Mhz domain clock
+ * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLSAI1M/PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.
+ * @note This can be selected for USB, RNG, SDMMC
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
+ * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_48M\n
+ * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n
+ * PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_16
+ * @param PLLN Between 8 and 86 or 127 depending on devices
+ * @param PLLQ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q,
+ PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLQ);
+}
+#else
+/**
+ * @brief Configure PLLSAI1 used for 48Mhz domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.
+ * @note This can be selected for USB, RNG, SDMMC
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
+ * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n
+ * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n
+ * PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @param PLLN Between 8 and 86 or 127 depending on devices
+ * @param PLLQ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ);
+}
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
+
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+/**
+ * @brief Configure PLLSAI1 used for SAI domain clock
+ * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLSAI1M/PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.
+ * @note This can be selected for SAI1 or SAI2
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
+ * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_SAI\n
+ * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
+ * PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_16
+ * @param PLLN Between 8 and 86 or 127 depending on devices
+ * @param PLLP This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_16
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_17
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_18
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_19
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_20
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_21
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_22
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_23
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_24
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_25
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_26
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_27
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_28
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_29
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_30
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
+ PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLP);
+}
+#elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+/**
+ * @brief Configure PLLSAI1 used for SAI domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.
+ * @note This can be selected for SAI1 or SAI2 (*)
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
+ * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
+ * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
+ * PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @param PLLN Between 8 and 86 or 127 depending on devices
+ * @param PLLP This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_16
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_17
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_18
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_19
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_20
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_21
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_22
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_23
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_24
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_25
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_26
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_27
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_28
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_29
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_30
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
+ PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP);
+}
+#else
+/**
+ * @brief Configure PLLSAI1 used for SAI domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLSAI1N/PLLSAI1P can be written only when PLLSAI1 is disabled.
+ * @note This can be selected for SAI1 or SAI2 (*)
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
+ * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
+ * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
+ * PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_ConfigDomain_SAI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @param PLLN Between 8 and 86
+ * @param PLLP This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_17
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP);
+}
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT && RCC_PLLSAI1P_DIV_2_31_SUPPORT */
+
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
+/**
+ * @brief Configure PLLSAI1 used for ADC domain clock
+ * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLSAI1M/PLLSAI1N/PLLSAI1R can be written only when PLLSAI1 is disabled.
+ * @note This can be selected for ADC
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
+ * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_ADC\n
+ * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n
+ * PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_16
+ * @param PLLN Between 8 and 86 or 127 depending on devices
+ * @param PLLR This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R,
+ PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLR);
+}
+#else
+/**
+ * @brief Configure PLLSAI1 used for ADC domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLN/PLLR can be written only when PLLSAI1 is disabled.
+ * @note This can be selected for ADC
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
+ * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n
+ * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n
+ * PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @param PLLN Between 8 and 86 or 127 depending on devices
+ * @param PLLR This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR);
+}
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
+
+/**
+ * @brief Get SAI1PLL multiplication factor for VCO
+ * @rmtoll PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN
+ * @retval Between 8 and 86 or 127 depending on devices
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
+}
+
+#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
+/**
+ * @brief Get SAI1PLL division factor for PLLSAI1P
+ * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
+ * @rmtoll PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_16
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_17
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_18
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_19
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_20
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_21
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_22
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_23
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_24
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_25
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_26
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_27
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_28
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_29
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_30
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_31
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV));
+}
+#else
+/**
+ * @brief Get SAI1PLL division factor for PLLSAI1P
+ * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
+ * @rmtoll PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1P_DIV_17
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P));
+}
+#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
+
+/**
+ * @brief Get SAI1PLL division factor for PLLSAI1Q
+ * @note Used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock)
+ * @rmtoll PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q));
+}
+
+/**
+ * @brief Get PLLSAI1 division factor for PLLSAIR
+ * @note Used for PLLADC1CLK (ADC clock)
+ * @rmtoll PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1R_DIV_8
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R));
+}
+
+#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
+/**
+ * @brief Get Division factor for the PLLSAI1
+ * @rmtoll PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_GetDivider
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI1M_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetDivider(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M));
+}
+#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
+
+/**
+ * @brief Enable PLLSAI1 output mapped on SAI domain clock
+ * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
+{
+ SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
+}
+
+/**
+ * @brief Disable PLLSAI1 output mapped on SAI domain clock
+ * @note In order to save power, when of the PLLSAI1 is
+ * not used, should be 0
+ * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_DisableDomain_SAI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
+{
+ CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
+}
+
+/**
+ * @brief Check if PLLSAI1 output mapped on SAI domain clock is enabled
+ * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_IsEnabledDomain_SAI
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_SAI(void)
+{
+ return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN) == (RCC_PLLSAI1CFGR_PLLSAI1PEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable PLLSAI1 output mapped on 48MHz domain clock
+ * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
+{
+ SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
+}
+
+/**
+ * @brief Disable PLLSAI1 output mapped on 48MHz domain clock
+ * @note In order to save power, when of the PLLSAI1 is
+ * not used, should be 0
+ * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_DisableDomain_48M
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
+{
+ CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
+}
+
+/**
+ * @brief Check if PLLSAI1 output mapped on SAI domain clock is enabled
+ * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_IsEnabledDomain_48M
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_48M(void)
+{
+ return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN) == (RCC_PLLSAI1CFGR_PLLSAI1QEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable PLLSAI1 output mapped on ADC domain clock
+ * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
+{
+ SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
+}
+
+/**
+ * @brief Disable PLLSAI1 output mapped on ADC domain clock
+ * @note In order to save power, when of the PLLSAI1 is
+ * not used, Main PLLSAI1 should be 0
+ * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_DisableDomain_ADC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
+{
+ CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
+}
+
+/**
+ * @brief Check if PLLSAI1 output mapped on ADC domain clock is enabled
+ * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_IsEnabledDomain_ADC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_ADC(void)
+{
+ return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN) == (RCC_PLLSAI1CFGR_PLLSAI1REN)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+#endif /* RCC_PLLSAI1_SUPPORT */
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+/** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2
+ * @{
+ */
+
+/**
+ * @brief Enable PLLSAI2
+ * @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
+}
+
+/**
+ * @brief Disable PLLSAI2
+ * @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
+}
+
+/**
+ * @brief Check if PLLSAI2 Ready
+ * @rmtoll CR PLLSAI2RDY LL_RCC_PLLSAI2_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RCC_CR_PLLSAI2RDY) ? 1UL : 0UL);
+}
+
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
+/**
+ * @brief Configure PLLSAI2 used for SAI domain clock
+ * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLSAI2M/PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled.
+ * @note This can be selected for SAI1 or SAI2
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
+ * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_SAI\n
+ * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
+ * PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_16
+ * @param PLLN Between 8 and 86 or 127 depending on devices
+ * @param PLLP This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_16
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_17
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_18
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_19
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_20
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_21
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_22
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_23
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_24
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_25
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_26
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_27
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_28
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_29
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_30
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+ MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
+ PLLM | (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLP);
+}
+#elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
+/**
+ * @brief Configure PLLSAI2 used for SAI domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLSAI1 and PLLSAI2 are disabled.
+ * @note PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled.
+ * @note This can be selected for SAI1 or SAI2
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
+ * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n
+ * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
+ * PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @param PLLN Between 8 and 86 or 127 depending on devices
+ * @param PLLP This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_16
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_17
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_18
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_19
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_20
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_21
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_22
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_23
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_24
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_25
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_26
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_27
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_28
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_29
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_30
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+ MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP);
+}
+#else
+/**
+ * @brief Configure PLLSAI2 used for SAI domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLSAI2 and PLLSAI2 are disabled.
+ * @note PLLSAI2N/PLLSAI2P can be written only when PLLSAI2 is disabled.
+ * @note This can be selected for SAI1 or SAI2
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
+ * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n
+ * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
+ * PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_ConfigDomain_SAI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @param PLLN Between 8 and 86
+ * @param PLLP This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_17
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+ MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP);
+}
+#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2P_DIV_2_31_SUPPORT */
+
+#if defined(DSI)
+/**
+ * @brief Configure PLLSAI2 used for DSI domain clock
+ * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLSAI2M/PLLSAI2N/PLLSAI2Q can be written only when PLLSAI2 is disabled.
+ * @note This can be selected for DSI
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_DSI\n
+ * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_DSI\n
+ * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_DSI\n
+ * PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_ConfigDomain_DSI
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_16
+ * @param PLLN Between 8 and 127
+ * @param PLLQ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+ MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q,
+ (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLQ | PLLM);
+}
+#endif /* DSI */
+
+#if defined(LTDC)
+/**
+ * @brief Configure PLLSAI2 used for LTDC domain clock
+ * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
+ * @note PLLSAI2M/PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled.
+ * @note This can be selected for LTDC
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
+ * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
+ * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
+ * PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
+ * CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_ConfigDomain_LTDC
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_16
+ * @param PLLN Between 8 and 127
+ * @param PLLR This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_8
+ * @param PLLDIVR This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+ MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R,
+ (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLR | PLLM);
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, PLLDIVR);
+}
+#else
+/**
+ * @brief Configure PLLSAI2 used for ADC domain clock
+ * @note PLL Source and PLLM Divider can be written only when PLL,
+ * PLLSAI2 and PLLSAI2 are disabled.
+ * @note PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled.
+ * @note This can be selected for ADC
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_ADC\n
+ * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_ADC\n
+ * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_ADC\n
+ * PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_ADC
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_MSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLM This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @param PLLN Between 8 and 86
+ * @param PLLR This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+ MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR);
+}
+#endif /* LTDC */
+
+/**
+ * @brief Get SAI2PLL multiplication factor for VCO
+ * @rmtoll PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_GetN
+ * @retval Between 8 and 86 or 127 depending on devices
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
+}
+
+#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
+/**
+ * @brief Get SAI2PLL division factor for PLLSAI2P
+ * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock).
+ * @rmtoll PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_GetP
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_16
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_17
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_18
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_19
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_20
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_21
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_22
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_23
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_24
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_25
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_26
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_27
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_28
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_29
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_30
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_31
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV));
+}
+#else
+/**
+ * @brief Get SAI2PLL division factor for PLLSAI2P
+ * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock).
+ * @rmtoll PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_GetP
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2P_DIV_17
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P));
+}
+#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
+
+#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
+/**
+ * @brief Get division factor for PLLSAI2Q
+ * @note Used for PLLDSICLK (DSI clock)
+ * @rmtoll PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_GetQ
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2Q_DIV_8
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetQ(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q));
+}
+#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
+
+/**
+ * @brief Get SAI2PLL division factor for PLLSAI2R
+ * @note Used for PLLADC2CLK (ADC clock) or PLLLCDCLK (LTDC clock) depending on devices
+ * @rmtoll PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_GetR
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2R_DIV_8
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R));
+}
+
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
+/**
+ * @brief Get Division factor for the PLLSAI2
+ * @rmtoll PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_GetDivider
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_1
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_3
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_5
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_6
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_7
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_9
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_10
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_11
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_12
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_13
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_14
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_15
+ * @arg @ref LL_RCC_PLLSAI2M_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDivider(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M));
+}
+#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
+
+#if defined(RCC_CCIPR2_PLLSAI2DIVR)
+/**
+ * @brief Get PLLSAI2 division factor for PLLSAI2DIVR
+ * @note Used for LTDC domain clock
+ * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_GetDIVR
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
+ * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDIVR(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR));
+}
+#endif /* RCC_CCIPR2_PLLSAI2DIVR */
+
+/**
+ * @brief Enable PLLSAI2 output mapped on SAI domain clock
+ * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void)
+{
+ SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
+}
+
+/**
+ * @brief Disable PLLSAI2 output mapped on SAI domain clock
+ * @note In order to save power, when of the PLLSAI2 is
+ * not used, should be 0
+ * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_DisableDomain_SAI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void)
+{
+ CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
+}
+
+/**
+ * @brief Check if PLLSAI2 output mapped on SAI domain clock is enabled
+ * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_IsEnabledDomain_SAI
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_SAI(void)
+{
+ return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN) == (RCC_PLLSAI2CFGR_PLLSAI2PEN)) ? 1UL : 0UL);
+}
+
+#if defined(DSI)
+/**
+ * @brief Enable PLLSAI2 output mapped on DSI domain clock
+ * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_EnableDomain_DSI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_DSI(void)
+{
+ SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);
+}
+
+/**
+ * @brief Disable PLLSAI2 output mapped on DSI domain clock
+ * @note In order to save power, when of the PLLSAI2 is
+ * not used, Main PLLSAI2 should be 0
+ * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_DisableDomain_DSI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_DSI(void)
+{
+ CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);
+}
+
+/**
+ * @brief Check if PLLSAI2 output mapped on DSI domain clock is enabled
+ * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_IsEnabledDomain_DSI
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_DSI(void)
+{
+ return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN) == (RCC_PLLSAI2CFGR_PLLSAI2QEN)) ? 1UL : 0UL);
+}
+#endif /* DSI */
+
+#if defined(LTDC)
+/**
+ * @brief Enable PLLSAI2 output mapped on LTDC domain clock
+ * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_LTDC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_LTDC(void)
+{
+ SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
+}
+
+/**
+ * @brief Disable PLLSAI2 output mapped on LTDC domain clock
+ * @note In order to save power, when of the PLLSAI2 is
+ * not used, Main PLLSAI2 should be 0
+ * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_LTDC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_LTDC(void)
+{
+ CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
+}
+
+/**
+ * @brief Check if PLLSAI2 output mapped on LTDC domain clock is enabled
+ * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_IsEnabledDomain_LTDC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_LTDC(void)
+{
+ return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN) == (RCC_PLLSAI2CFGR_PLLSAI2REN)) ? 1UL : 0UL);
+}
+#else
+/**
+ * @brief Enable PLLSAI2 output mapped on ADC domain clock
+ * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void)
+{
+ SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
+}
+
+/**
+ * @brief Disable PLLSAI2 output mapped on ADC domain clock
+ * @note In order to save power, when of the PLLSAI2 is
+ * not used, Main PLLSAI2 should be 0
+ * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_ADC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void)
+{
+ CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
+}
+
+/**
+ * @brief Check if PLLSAI2 output mapped on ADC domain clock is enabled
+ * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_IsEnabledDomain_ADC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_ADC(void)
+{
+ return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN) == (RCC_PLLSAI2CFGR_PLLSAI2REN)) ? 1UL : 0UL);
+}
+#endif /* LTDC */
+
+/**
+ * @}
+ */
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+#if defined(OCTOSPI1)
+/** @defgroup RCC_LL_EF_OCTOSPI OCTOSPI
+ * @{
+ */
+
+/**
+ * @brief Configure OCTOSPI1 DQS delay
+ * @rmtoll DLYCFGR OCTOSPI1_DLY LL_RCC_OCTOSPI1_DelayConfig
+ * @param Delay OCTOSPI1 DQS delay between 0 and 15
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_OCTOSPI1_DelayConfig(uint32_t Delay)
+{
+ MODIFY_REG(RCC->DLYCFGR, RCC_DLYCFGR_OCTOSPI1_DLY, Delay);
+}
+
+#if defined(OCTOSPI2)
+/**
+ * @brief Configure OCTOSPI2 DQS delay
+ * @rmtoll DLYCFGR OCTOSPI2_DLY LL_RCC_OCTOSPI2_DelayConfig
+ * @param Delay OCTOSPI2 DQS delay between 0 and 15
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_OCTOSPI2_DelayConfig(uint32_t Delay)
+{
+ MODIFY_REG(RCC->DLYCFGR, RCC_DLYCFGR_OCTOSPI2_DLY, (Delay << RCC_DLYCFGR_OCTOSPI2_DLY_Pos));
+}
+#endif /* OCTOSPI2 */
+
+/**
+ * @}
+ */
+#endif /* OCTOSPI1 */
+
+/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Clear LSI ready interrupt flag
+ * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
+}
+
+/**
+ * @brief Clear LSE ready interrupt flag
+ * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
+}
+
+/**
+ * @brief Clear MSI ready interrupt flag
+ * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
+}
+
+/**
+ * @brief Clear HSI ready interrupt flag
+ * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
+}
+
+/**
+ * @brief Clear HSE ready interrupt flag
+ * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
+}
+
+/**
+ * @brief Clear PLL ready interrupt flag
+ * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
+}
+
+#if defined(RCC_HSI48_SUPPORT)
+/**
+ * @brief Clear HSI48 ready interrupt flag
+ * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
+}
+#endif /* RCC_HSI48_SUPPORT */
+
+#if defined(RCC_PLLSAI1_SUPPORT)
+/**
+ * @brief Clear PLLSAI1 ready interrupt flag
+ * @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);
+}
+#endif /* RCC_PLLSAI1_SUPPORT */
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+/**
+ * @brief Clear PLLSAI1 ready interrupt flag
+ * @rmtoll CICR PLLSAI2RDYC LL_RCC_ClearFlag_PLLSAI2RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC);
+}
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/**
+ * @brief Clear Clock security system interrupt flag
+ * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_CSSC);
+}
+
+/**
+ * @brief Clear LSE Clock security system interrupt flag
+ * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
+{
+ SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
+}
+
+/**
+ * @brief Check if LSI ready interrupt occurred or not
+ * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if LSE ready interrupt occurred or not
+ * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if MSI ready interrupt occurred or not
+ * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == RCC_CIFR_MSIRDYF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if HSI ready interrupt occurred or not
+ * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if HSE ready interrupt occurred or not
+ * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if PLL ready interrupt occurred or not
+ * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == RCC_CIFR_PLLRDYF) ? 1UL : 0UL);
+}
+
+#if defined(RCC_HSI48_SUPPORT)
+/**
+ * @brief Check if HSI48 ready interrupt occurred or not
+ * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL);
+}
+#endif /* RCC_HSI48_SUPPORT */
+
+#if defined(RCC_PLLSAI1_SUPPORT)
+/**
+ * @brief Check if PLLSAI1 ready interrupt occurred or not
+ * @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) ? 1UL : 0UL);
+}
+#endif /* RCC_PLLSAI1_SUPPORT */
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+/**
+ * @brief Check if PLLSAI1 ready interrupt occurred or not
+ * @rmtoll CIFR PLLSAI2RDYF LL_RCC_IsActiveFlag_PLLSAI2RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) ? 1UL : 0UL);
+}
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/**
+ * @brief Check if Clock security system interrupt occurred or not
+ * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == RCC_CIFR_CSSF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if LSE Clock security system interrupt occurred or not
+ * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
+{
+ return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == RCC_CIFR_LSECSSF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag FW reset is set or not.
+ * @rmtoll CSR FWRSTF LL_RCC_IsActiveFlag_FWRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)
+{
+ return ((READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == RCC_CSR_FWRSTF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag Independent Watchdog reset is set or not.
+ * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
+{
+ return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag Low Power reset is set or not.
+ * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
+{
+ return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag is set or not.
+ * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
+{
+ return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag Pin reset is set or not.
+ * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
+{
+ return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag Software reset is set or not.
+ * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
+{
+ return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag Window Watchdog reset is set or not.
+ * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
+{
+ return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if RCC flag BOR reset is set or not.
+ * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
+{
+ return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == RCC_CSR_BORRSTF) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set RMVF bit to clear the reset flags.
+ * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
+{
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_IT_Management IT Management
+ * @{
+ */
+
+/**
+ * @brief Enable LSI ready interrupt
+ * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+ * @brief Enable LSE ready interrupt
+ * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+ * @brief Enable MSI ready interrupt
+ * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
+}
+
+/**
+ * @brief Enable HSI ready interrupt
+ * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+ * @brief Enable HSE ready interrupt
+ * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+ * @brief Enable PLL ready interrupt
+ * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
+}
+
+#if defined(RCC_HSI48_SUPPORT)
+/**
+ * @brief Enable HSI48 ready interrupt
+ * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
+}
+#endif /* RCC_HSI48_SUPPORT */
+
+#if defined(RCC_PLLSAI1_SUPPORT)
+/**
+ * @brief Enable PLLSAI1 ready interrupt
+ * @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
+}
+#endif /* RCC_PLLSAI1_SUPPORT */
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+/**
+ * @brief Enable PLLSAI2 ready interrupt
+ * @rmtoll CIER PLLSAI2RDYIE LL_RCC_EnableIT_PLLSAI2RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
+}
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/**
+ * @brief Enable LSE clock security system interrupt
+ * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
+{
+ SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
+}
+
+/**
+ * @brief Disable LSI ready interrupt
+ * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+ * @brief Disable LSE ready interrupt
+ * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+ * @brief Disable MSI ready interrupt
+ * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
+}
+
+/**
+ * @brief Disable HSI ready interrupt
+ * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+ * @brief Disable HSE ready interrupt
+ * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+ * @brief Disable PLL ready interrupt
+ * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
+}
+
+#if defined(RCC_HSI48_SUPPORT)
+/**
+ * @brief Disable HSI48 ready interrupt
+ * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
+}
+#endif /* RCC_HSI48_SUPPORT */
+
+#if defined(RCC_PLLSAI1_SUPPORT)
+/**
+ * @brief Disable PLLSAI1 ready interrupt
+ * @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
+}
+#endif /* RCC_PLLSAI1_SUPPORT */
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+/**
+ * @brief Disable PLLSAI2 ready interrupt
+ * @rmtoll CIER PLLSAI2RDYIE LL_RCC_DisableIT_PLLSAI2RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
+}
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/**
+ * @brief Disable LSE clock security system interrupt
+ * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
+{
+ CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
+}
+
+/**
+ * @brief Checks if LSI ready interrupt source is enabled or disabled.
+ * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Checks if LSE ready interrupt source is enabled or disabled.
+ * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Checks if MSI ready interrupt source is enabled or disabled.
+ * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == RCC_CIER_MSIRDYIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Checks if HSI ready interrupt source is enabled or disabled.
+ * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Checks if HSE ready interrupt source is enabled or disabled.
+ * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Checks if PLL ready interrupt source is enabled or disabled.
+ * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == RCC_CIER_PLLRDYIE) ? 1UL : 0UL);
+}
+
+#if defined(RCC_HSI48_SUPPORT)
+/**
+ * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
+ * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL);
+}
+#endif /* RCC_HSI48_SUPPORT */
+
+#if defined(RCC_PLLSAI1_SUPPORT)
+/**
+ * @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled.
+ * @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == RCC_CIER_PLLSAI1RDYIE) ? 1UL : 0UL);
+}
+#endif /* RCC_PLLSAI1_SUPPORT */
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+/**
+ * @brief Checks if PLLSAI2 ready interrupt source is enabled or disabled.
+ * @rmtoll CIER PLLSAI2RDYIE LL_RCC_IsEnabledIT_PLLSAI2RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == RCC_CIER_PLLSAI2RDYIE) ? 1UL : 0UL);
+}
+#endif /* RCC_PLLSAI2_SUPPORT */
+
+/**
+ * @brief Checks if LSECSS interrupt source is enabled or disabled.
+ * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
+{
+ return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EF_Init De-initialization function
+ * @{
+ */
+ErrorStatus LL_RCC_DeInit(void);
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
+ * @{
+ */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
+uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
+#if defined(UART4) || defined(UART5)
+uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
+#endif /* UART4 || UART5 */
+uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
+uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
+uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
+#if defined(SAI1)
+uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
+#endif /* SAI1 */
+#if defined(SDMMC1)
+#if defined(RCC_CCIPR2_SDMMCSEL)
+uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource);
+#endif
+uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
+#endif /* SDMMC1 */
+uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
+#if defined(USB_OTG_FS) || defined(USB)
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
+#endif /* USB_OTG_FS || USB */
+uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
+#if defined(SWPMI1)
+uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource);
+#endif /* SWPMI1 */
+#if defined(DFSDM1_Channel0)
+uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
+#if defined(RCC_CCIPR2_DFSDM1SEL)
+uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
+#endif /* RCC_CCIPR2_DFSDM1SEL */
+#endif /* DFSDM1_Channel0 */
+#if defined(LTDC)
+uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
+#endif /* LTDC */
+#if defined(DSI)
+uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
+#endif /* DSI */
+#if defined(OCTOSPI1)
+uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource);
+#endif /* OCTOSPI1 */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RCC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L4xx_LL_RCC_H */
+
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h
new file mode 100644
index 0000000..d377cca
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h
@@ -0,0 +1,1418 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_spi.h
+ * @author MCD Application Team
+ * @brief Header file of SPI LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L4xx_LL_SPI_H
+#define STM32L4xx_LL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined (SPI1) || defined (SPI2) || defined (SPI3)
+
+/** @defgroup SPI_LL SPI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief SPI Init structures definition
+ */
+typedef struct
+{
+ uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
+ This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
+
+ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
+ This parameter can be a value of @ref SPI_LL_EC_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
+
+ uint32_t DataWidth; /*!< Specifies the SPI data width.
+ This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
+
+ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_LL_EC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
+
+ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_LL_EC_PHASE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
+
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
+
+ uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
+ @note The communication clock is derived from the master clock. The slave clock does not need to be set.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
+
+ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
+
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
+ This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
+
+ This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
+
+ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
+
+} LL_SPI_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
+ * @{
+ */
+
+/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_SPI_ReadReg function
+ * @{
+ */
+#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
+#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
+#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
+#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
+#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
+#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
+#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
+ * @{
+ */
+#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
+#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
+#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_MODE Operation Mode
+ * @{
+ */
+#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
+#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
+ * @{
+ */
+#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
+#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_PHASE Clock Phase
+ * @{
+ */
+#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
+#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
+#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
+ * @{
+ */
+#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
+ * @{
+ */
+#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
+#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
+ * @{
+ */
+#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
+#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
+#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
+#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
+ * @{
+ */
+#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
+#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
+#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
+ * @{
+ */
+#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */
+#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */
+#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */
+#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */
+#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */
+#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */
+#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */
+#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */
+#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */
+#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */
+#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */
+#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */
+#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
+ * @{
+ */
+#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
+#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
+ * @{
+ */
+#define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */
+#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
+ * @{
+ */
+#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */
+#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit) */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
+ * @{
+ */
+#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */
+#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */
+#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */
+#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
+ * @{
+ */
+#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */
+#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */
+#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */
+#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
+ * @{
+ */
+#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */
+#define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
+ * @{
+ */
+
+/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in SPI register
+ * @param __INSTANCE__ SPI Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in SPI register
+ * @param __INSTANCE__ SPI Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
+ * @{
+ */
+
+/** @defgroup SPI_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable SPI peripheral
+ * @rmtoll CR1 SPE LL_SPI_Enable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+ * @brief Disable SPI peripheral
+ * @note When disabling the SPI, follow the procedure described in the Reference Manual.
+ * @rmtoll CR1 SPE LL_SPI_Disable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+ * @brief Check if SPI peripheral is enabled
+ * @rmtoll CR1 SPE LL_SPI_IsEnabled
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set SPI operation mode to Master or Slave
+ * @note This bit should not be changed when communication is ongoing.
+ * @rmtoll CR1 MSTR LL_SPI_SetMode\n
+ * CR1 SSI LL_SPI_SetMode
+ * @param SPIx SPI Instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_SPI_MODE_MASTER
+ * @arg @ref LL_SPI_MODE_SLAVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
+}
+
+/**
+ * @brief Get SPI operation mode (Master or Slave)
+ * @rmtoll CR1 MSTR LL_SPI_GetMode\n
+ * CR1 SSI LL_SPI_GetMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_MODE_MASTER
+ * @arg @ref LL_SPI_MODE_SLAVE
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
+}
+
+/**
+ * @brief Set serial protocol used
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR2 FRF LL_SPI_SetStandard
+ * @param SPIx SPI Instance
+ * @param Standard This parameter can be one of the following values:
+ * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+ * @arg @ref LL_SPI_PROTOCOL_TI
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+ MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
+}
+
+/**
+ * @brief Get serial protocol used
+ * @rmtoll CR2 FRF LL_SPI_GetStandard
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+ * @arg @ref LL_SPI_PROTOCOL_TI
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
+}
+
+/**
+ * @brief Set clock phase
+ * @note This bit should not be changed when communication is ongoing.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
+ * @param SPIx SPI Instance
+ * @param ClockPhase This parameter can be one of the following values:
+ * @arg @ref LL_SPI_PHASE_1EDGE
+ * @arg @ref LL_SPI_PHASE_2EDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
+}
+
+/**
+ * @brief Get clock phase
+ * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_PHASE_1EDGE
+ * @arg @ref LL_SPI_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
+}
+
+/**
+ * @brief Set clock polarity
+ * @note This bit should not be changed when communication is ongoing.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
+ * @param SPIx SPI Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_SPI_POLARITY_LOW
+ * @arg @ref LL_SPI_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
+}
+
+/**
+ * @brief Get clock polarity
+ * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_POLARITY_LOW
+ * @arg @ref LL_SPI_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
+}
+
+/**
+ * @brief Set baud rate prescaler
+ * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
+ * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
+ * @param SPIx SPI Instance
+ * @param BaudRate This parameter can be one of the following values:
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
+}
+
+/**
+ * @brief Get baud rate prescaler
+ * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
+}
+
+/**
+ * @brief Set transfer bit order
+ * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+ * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
+ * @param SPIx SPI Instance
+ * @param BitOrder This parameter can be one of the following values:
+ * @arg @ref LL_SPI_LSB_FIRST
+ * @arg @ref LL_SPI_MSB_FIRST
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
+}
+
+/**
+ * @brief Get transfer bit order
+ * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_LSB_FIRST
+ * @arg @ref LL_SPI_MSB_FIRST
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
+}
+
+/**
+ * @brief Set transfer direction mode
+ * @note For Half-Duplex mode, Rx Direction is set by default.
+ * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
+ * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
+ * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
+ * CR1 BIDIOE LL_SPI_SetTransferDirection
+ * @param SPIx SPI Instance
+ * @param TransferDirection This parameter can be one of the following values:
+ * @arg @ref LL_SPI_FULL_DUPLEX
+ * @arg @ref LL_SPI_SIMPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_TX
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
+}
+
+/**
+ * @brief Get transfer direction mode
+ * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
+ * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
+ * CR1 BIDIOE LL_SPI_GetTransferDirection
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_FULL_DUPLEX
+ * @arg @ref LL_SPI_SIMPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_TX
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
+}
+
+/**
+ * @brief Set frame data width
+ * @rmtoll CR2 DS LL_SPI_SetDataWidth
+ * @param SPIx SPI Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_SPI_DATAWIDTH_4BIT
+ * @arg @ref LL_SPI_DATAWIDTH_5BIT
+ * @arg @ref LL_SPI_DATAWIDTH_6BIT
+ * @arg @ref LL_SPI_DATAWIDTH_7BIT
+ * @arg @ref LL_SPI_DATAWIDTH_8BIT
+ * @arg @ref LL_SPI_DATAWIDTH_9BIT
+ * @arg @ref LL_SPI_DATAWIDTH_10BIT
+ * @arg @ref LL_SPI_DATAWIDTH_11BIT
+ * @arg @ref LL_SPI_DATAWIDTH_12BIT
+ * @arg @ref LL_SPI_DATAWIDTH_13BIT
+ * @arg @ref LL_SPI_DATAWIDTH_14BIT
+ * @arg @ref LL_SPI_DATAWIDTH_15BIT
+ * @arg @ref LL_SPI_DATAWIDTH_16BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
+{
+ MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
+}
+
+/**
+ * @brief Get frame data width
+ * @rmtoll CR2 DS LL_SPI_GetDataWidth
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_DATAWIDTH_4BIT
+ * @arg @ref LL_SPI_DATAWIDTH_5BIT
+ * @arg @ref LL_SPI_DATAWIDTH_6BIT
+ * @arg @ref LL_SPI_DATAWIDTH_7BIT
+ * @arg @ref LL_SPI_DATAWIDTH_8BIT
+ * @arg @ref LL_SPI_DATAWIDTH_9BIT
+ * @arg @ref LL_SPI_DATAWIDTH_10BIT
+ * @arg @ref LL_SPI_DATAWIDTH_11BIT
+ * @arg @ref LL_SPI_DATAWIDTH_12BIT
+ * @arg @ref LL_SPI_DATAWIDTH_13BIT
+ * @arg @ref LL_SPI_DATAWIDTH_14BIT
+ * @arg @ref LL_SPI_DATAWIDTH_15BIT
+ * @arg @ref LL_SPI_DATAWIDTH_16BIT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
+}
+
+/**
+ * @brief Set threshold of RXFIFO that triggers an RXNE event
+ * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
+ * @param SPIx SPI Instance
+ * @param Threshold This parameter can be one of the following values:
+ * @arg @ref LL_SPI_RX_FIFO_TH_HALF
+ * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
+{
+ MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
+}
+
+/**
+ * @brief Get threshold of RXFIFO that triggers an RXNE event
+ * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_RX_FIFO_TH_HALF
+ * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_CRC_Management CRC Management
+ * @{
+ */
+
+/**
+ * @brief Enable CRC
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+ * @brief Disable CRC
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+ * @brief Check if CRC is enabled
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set CRC Length
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
+ * @param SPIx SPI Instance
+ * @param CRCLength This parameter can be one of the following values:
+ * @arg @ref LL_SPI_CRC_8BIT
+ * @arg @ref LL_SPI_CRC_16BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
+}
+
+/**
+ * @brief Get CRC Length
+ * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_CRC_8BIT
+ * @arg @ref LL_SPI_CRC_16BIT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
+}
+
+/**
+ * @brief Set CRCNext to transfer CRC on the line
+ * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
+ * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
+}
+
+/**
+ * @brief Set polynomial for CRC calculation
+ * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
+ * @param SPIx SPI Instance
+ * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
+{
+ WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
+}
+
+/**
+ * @brief Get polynomial for CRC calculation
+ * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->CRCPR));
+}
+
+/**
+ * @brief Get Rx CRC
+ * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->RXCRCR));
+}
+
+/**
+ * @brief Get Tx CRC
+ * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->TXCRCR));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
+ * @{
+ */
+
+/**
+ * @brief Set NSS mode
+ * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
+ * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
+ * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
+ * @param SPIx SPI Instance
+ * @param NSS This parameter can be one of the following values:
+ * @arg @ref LL_SPI_NSS_SOFT
+ * @arg @ref LL_SPI_NSS_HARD_INPUT
+ * @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
+ MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
+}
+
+/**
+ * @brief Get NSS mode
+ * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
+ * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_NSS_SOFT
+ * @arg @ref LL_SPI_NSS_HARD_INPUT
+ * @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
+{
+ uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
+ uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
+ return (Ssm | Ssoe);
+}
+
+/**
+ * @brief Enable NSS pulse management
+ * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+ * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
+}
+
+/**
+ * @brief Disable NSS pulse management
+ * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+ * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
+}
+
+/**
+ * @brief Check if NSS pulse is enabled
+ * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+ * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Check if Rx buffer is not empty
+ * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Tx buffer is empty
+ * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get CRC error flag
+ * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get mode fault error flag
+ * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get overrun error flag
+ * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get busy flag
+ * @note The BSY flag is cleared under any one of the following conditions:
+ * -When the SPI is correctly disabled
+ * -When a fault is detected in Master mode (MODF bit set to 1)
+ * -In Master mode, when it finishes a data transmission and no new data is ready to be
+ * sent
+ * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
+ * each data transfer.
+ * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get frame format error flag
+ * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get FIFO reception Level
+ * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_RX_FIFO_EMPTY
+ * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
+ * @arg @ref LL_SPI_RX_FIFO_HALF_FULL
+ * @arg @ref LL_SPI_RX_FIFO_FULL
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
+}
+
+/**
+ * @brief Get FIFO Transmission Level
+ * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_TX_FIFO_EMPTY
+ * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
+ * @arg @ref LL_SPI_TX_FIFO_HALF_FULL
+ * @arg @ref LL_SPI_TX_FIFO_FULL
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
+}
+
+/**
+ * @brief Clear CRC error flag
+ * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
+}
+
+/**
+ * @brief Clear mode fault error flag
+ * @note Clearing this flag is done by a read access to the SPIx_SR
+ * register followed by a write access to the SPIx_CR1 register
+ * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg_sr;
+ tmpreg_sr = SPIx->SR;
+ (void) tmpreg_sr;
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+ * @brief Clear overrun error flag
+ * @note Clearing this flag is done by a read access to the SPIx_DR
+ * register followed by a read access to the SPIx_SR register
+ * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->DR;
+ (void) tmpreg;
+ tmpreg = SPIx->SR;
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear frame format error flag
+ * @note Clearing this flag is done by reading SPIx_SR register
+ * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->SR;
+ (void) tmpreg;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable error interrupt
+ * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+ * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+ * @brief Enable Rx buffer not empty interrupt
+ * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+ * @brief Enable Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+ * @brief Disable error interrupt
+ * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+ * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+ * @brief Disable Rx buffer not empty interrupt
+ * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+ * @brief Disable Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+ * @brief Check if error interrupt is enabled
+ * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Rx buffer not empty interrupt is enabled
+ * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_DMA_Management DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+ * @brief Disable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+ * @brief Check if DMA Rx is enabled
+ * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+ * @brief Disable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+ * @brief Check if DMA Tx is enabled
+ * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set parity of Last DMA reception
+ * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
+ * @param SPIx SPI Instance
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_SPI_DMA_PARITY_ODD
+ * @arg @ref LL_SPI_DMA_PARITY_EVEN
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
+{
+ MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
+}
+
+/**
+ * @brief Get parity configuration for Last DMA reception
+ * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_DMA_PARITY_ODD
+ * @arg @ref LL_SPI_DMA_PARITY_EVEN
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
+}
+
+/**
+ * @brief Set parity of Last DMA transmission
+ * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
+ * @param SPIx SPI Instance
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_SPI_DMA_PARITY_ODD
+ * @arg @ref LL_SPI_DMA_PARITY_EVEN
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
+{
+ MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
+}
+
+/**
+ * @brief Get parity configuration for Last DMA transmission
+ * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_DMA_PARITY_ODD
+ * @arg @ref LL_SPI_DMA_PARITY_EVEN
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
+ * @param SPIx SPI Instance
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
+{
+ return (uint32_t) &(SPIx->DR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_DATA_Management DATA Management
+ * @{
+ */
+
+/**
+ * @brief Read 8-Bits in the data register
+ * @rmtoll DR DR LL_SPI_ReceiveData8
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
+{
+ return (*((__IO uint8_t *)&SPIx->DR));
+}
+
+/**
+ * @brief Read 16-Bits in the data register
+ * @rmtoll DR DR LL_SPI_ReceiveData16
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
+{
+ return (uint16_t)(READ_REG(SPIx->DR));
+}
+
+/**
+ * @brief Write 8-Bits in the data register
+ * @rmtoll DR DR LL_SPI_TransmitData8
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
+{
+#if defined (__GNUC__)
+ __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
+ *spidr = TxData;
+#else
+ *((__IO uint8_t *)&SPIx->DR) = TxData;
+#endif /* __GNUC__ */
+}
+
+/**
+ * @brief Write 16-Bits in the data register
+ * @rmtoll DR DR LL_SPI_TransmitData16
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+#if defined (__GNUC__)
+ __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
+ *spidr = TxData;
+#else
+ SPIx->DR = TxData;
+#endif /* __GNUC__ */
+}
+
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L4xx_LL_SPI_H */
+
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h
new file mode 100644
index 0000000..94b722b
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h
@@ -0,0 +1,1627 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_system.h
+ * @author MCD Application Team
+ * @brief Header file of SYSTEM LL module.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL SYSTEM driver contains a set of generic APIs that can be
+ used by user:
+ (+) Some of the FLASH features need to be handled in the SYSTEM file.
+ (+) Access to DBGCMU registers
+ (+) Access to SYSCFG registers
+ (+) Access to VREFBUF registers
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L4xx_LL_SYSTEM_H
+#define STM32L4xx_LL_SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
+
+/** @defgroup SYSTEM_LL SYSTEM
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+ * @{
+ */
+
+/**
+ * @brief Power-down in Run mode Flash key
+ */
+#define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */
+#define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1
+ to unlock the RUN_PD bit in FLASH_ACR */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+ * @{
+ */
+
+/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
+* @{
+*/
+#define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */
+#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
+#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */
+#if defined(FMC_Bank1_R)
+#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */
+#endif /* FMC_Bank1_R */
+#define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000 */
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_MEMRMP_FB_MODE)
+/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
+ * @{
+ */
+#define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000)
+ and Flash Bank2 mapped at 0x08080000 (and aliased at 0x00080000) */
+#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
+ and Flash Bank1 mapped at 0x08080000 (and aliased at 0x00080000) */
+/**
+ * @}
+ */
+
+#endif /* SYSCFG_MEMRMP_FB_MODE */
+/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
+ * @{
+ */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
+#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
+#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
+#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
+#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
+#if defined(I2C2)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
+#endif /* I2C2 */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
+#if defined(I2C4)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
+#endif /* I2C4 */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
+ * @{
+ */
+#define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
+#define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
+#define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
+#define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
+#define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
+#if defined(GPIOF)
+#define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */
+#endif /* GPIOF */
+#if defined(GPIOG)
+#define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */
+#endif /* GPIOG */
+#define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */
+#if defined(GPIOI)
+#define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */
+#endif /* GPIOI */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
+ * @{
+ */
+#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
+ * @{
+ */
+#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
+ with Break Input of TIM1/8/15/16/17 */
+#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
+ with TIM1/8/15/16/17 Break Input
+ and also the PVDE and PLS bits of the Power Control Interface */
+#define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal
+ with Break Input of TIM1/8/15/16/17 */
+#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4
+ with Break Input of TIM1/15/16/17 */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRP
+ * @{
+ */
+#define LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */
+#define LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */
+#define LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */
+#define LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */
+#define LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */
+#define LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */
+#define LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */
+#define LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */
+#define LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */
+#define LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */
+#define LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */
+#define LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */
+#define LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */
+#define LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
+#define LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
+#define LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
+#if defined(SYSCFG_SWPR_PAGE31)
+#define LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
+#define LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
+#define LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
+#define LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */
+#define LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */
+#define LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */
+#define LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */
+#define LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */
+#define LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */
+#define LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */
+#define LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */
+#define LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */
+#define LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */
+#define LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
+#define LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
+#define LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
+#endif /* SYSCFG_SWPR_PAGE31 */
+#if defined(SYSCFG_SWPR2_PAGE63)
+#define LL_SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */
+#define LL_SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */
+#define LL_SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */
+#define LL_SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */
+#define LL_SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */
+#define LL_SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */
+#define LL_SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */
+#define LL_SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */
+#define LL_SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */
+#define LL_SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */
+#define LL_SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */
+#define LL_SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */
+#define LL_SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */
+#define LL_SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */
+#define LL_SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */
+#define LL_SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */
+#define LL_SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */
+#define LL_SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */
+#define LL_SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */
+#define LL_SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */
+#define LL_SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */
+#define LL_SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */
+#define LL_SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */
+#define LL_SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */
+#define LL_SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */
+#define LL_SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */
+#define LL_SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */
+#define LL_SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */
+#define LL_SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */
+#define LL_SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */
+#define LL_SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */
+#define LL_SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */
+#endif /* SYSCFG_SWPR2_PAGE63 */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
+ * @{
+ */
+#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
+#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+ * @{
+ */
+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/
+#if defined(TIM3)
+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/
+#endif /* TIM3 */
+#if defined(TIM4)
+#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/
+#endif /* TIM4 */
+#if defined(TIM5)
+#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/
+#endif /* TIM5 */
+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/
+#if defined(TIM7)
+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/
+#endif /* TIM7 */
+#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/
+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/
+#if defined(I2C2)
+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/
+#endif /* I2C2 */
+#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen*/
+#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP /*!< The bxCAN receive registers are frozen*/
+#if defined(CAN2)
+#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1FZR1_DBG_CAN2_STOP /*!< The bxCAN2 receive registers are frozen*/
+#endif /* CAN2 */
+#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
+ * @{
+ */
+#if defined(I2C4)
+#define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/
+#endif /* I2C4 */
+#define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+ * @{
+ */
+#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/
+#if defined(TIM8)
+#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/
+#endif /* TIM8 */
+#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/
+#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/
+#if defined(TIM17)
+#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/
+#endif /* TIM17 */
+/**
+ * @}
+ */
+
+#if defined(VREFBUF)
+/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
+ * @{
+ */
+#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
+#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */
+/**
+ * @}
+ */
+#endif /* VREFBUF */
+
+/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
+ * @{
+ */
+#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
+#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
+#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
+#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
+#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
+#if defined(FLASH_ACR_LATENCY_5WS)
+#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
+#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
+#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */
+#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */
+#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */
+#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */
+#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
+#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
+#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
+#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
+#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+ * @{
+ */
+
+/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
+ * @{
+ */
+
+/**
+ * @brief Set memory mapping at address 0x00000000
+ * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
+ * @param Memory This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_REMAP_FLASH
+ * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+ * @arg @ref LL_SYSCFG_REMAP_SRAM
+ * @arg @ref LL_SYSCFG_REMAP_FMC (*)
+ * @arg @ref LL_SYSCFG_REMAP_QUADSPI
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
+{
+ MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
+}
+
+/**
+ * @brief Get memory mapping at address 0x00000000
+ * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_REMAP_FLASH
+ * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+ * @arg @ref LL_SYSCFG_REMAP_SRAM
+ * @arg @ref LL_SYSCFG_REMAP_FMC (*)
+ * @arg @ref LL_SYSCFG_REMAP_QUADSPI
+ *
+ * (*) value not defined in all devices
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
+}
+
+#if defined(SYSCFG_MEMRMP_FB_MODE)
+/**
+ * @brief Select Flash bank mode (Bank flashed at 0x08000000)
+ * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode
+ * @param Bank This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_BANKMODE_BANK1
+ * @arg @ref LL_SYSCFG_BANKMODE_BANK2
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
+{
+ MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);
+}
+
+/**
+ * @brief Get Flash bank mode (Bank flashed at 0x08000000)
+ * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_BANKMODE_BANK1
+ * @arg @ref LL_SYSCFG_BANKMODE_BANK2
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));
+}
+#endif /* SYSCFG_MEMRMP_FB_MODE */
+
+/**
+ * @brief Firewall protection enabled
+ * @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_EnableFirewall
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableFirewall(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS);
+}
+
+/**
+ * @brief Check if Firewall protection is enabled or not
+ * @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_IsEnabledFirewall
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void)
+{
+ return !(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS) == SYSCFG_CFGR1_FWDIS);
+}
+
+/**
+ * @brief Enable I/O analog switch voltage booster.
+ * @note When voltage booster is enabled, I/O analog switches are supplied
+ * by a dedicated voltage booster, from VDD power domain. This is
+ * the recommended configuration with low VDDA voltage operation.
+ * @note The I/O analog switch voltage booster is relevant for peripherals
+ * using I/O in analog input: ADC, COMP, OPAMP.
+ * However, COMP and OPAMP inputs have a high impedance and
+ * voltage booster do not impact performance significantly.
+ * Therefore, the voltage booster is mainly intended for
+ * usage with ADC.
+ * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+ * @brief Disable I/O analog switch voltage booster.
+ * @note When voltage booster is enabled, I/O analog switches are supplied
+ * by a dedicated voltage booster, from VDD power domain. This is
+ * the recommended configuration with low VDDA voltage operation.
+ * @note The I/O analog switch voltage booster is relevant for peripherals
+ * using I/O in analog input: ADC, COMP, OPAMP.
+ * However, COMP and OPAMP inputs have a high impedance and
+ * voltage booster do not impact performance significantly.
+ * Therefore, the voltage booster is mainly intended for
+ * usage with ADC.
+ * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+ * @brief Enable the I2C fast mode plus driving capability.
+ * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
+ * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
+ * @param ConfigFastModePlus This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
+}
+
+/**
+ * @brief Disable the I2C fast mode plus driving capability.
+ * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
+ * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
+ * @param ConfigFastModePlus This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
+}
+
+/**
+ * @brief Enable Floating Point Unit Invalid operation Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
+}
+
+/**
+ * @brief Enable Floating Point Unit Divide-by-zero Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
+}
+
+/**
+ * @brief Enable Floating Point Unit Underflow Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
+}
+
+/**
+ * @brief Enable Floating Point Unit Overflow Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
+}
+
+/**
+ * @brief Enable Floating Point Unit Input denormal Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
+}
+
+/**
+ * @brief Enable Floating Point Unit Inexact Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
+}
+
+/**
+ * @brief Disable Floating Point Unit Invalid operation Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
+}
+
+/**
+ * @brief Disable Floating Point Unit Divide-by-zero Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
+}
+
+/**
+ * @brief Disable Floating Point Unit Underflow Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
+}
+
+/**
+ * @brief Disable Floating Point Unit Overflow Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
+}
+
+/**
+ * @brief Disable Floating Point Unit Input denormal Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
+}
+
+/**
+ * @brief Disable Floating Point Unit Inexact Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
+}
+
+/**
+ * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
+{
+ return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
+}
+
+/**
+ * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
+{
+ return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
+}
+
+/**
+ * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
+{
+ return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
+}
+
+/**
+ * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
+{
+ return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
+}
+
+/**
+ * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
+{
+ return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
+}
+
+/**
+ * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
+{
+ return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
+}
+
+/**
+ * @brief Configure source input for the EXTI external interrupt.
+ * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
+ * @param Port This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_PORTA
+ * @arg @ref LL_SYSCFG_EXTI_PORTB
+ * @arg @ref LL_SYSCFG_EXTI_PORTC
+ * @arg @ref LL_SYSCFG_EXTI_PORTD
+ * @arg @ref LL_SYSCFG_EXTI_PORTE
+ * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
+ * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
+ * @arg @ref LL_SYSCFG_EXTI_PORTH
+ * @arg @ref LL_SYSCFG_EXTI_PORTI (*)
+ *
+ * (*) value not defined in all devices
+ * @param Line This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_LINE0
+ * @arg @ref LL_SYSCFG_EXTI_LINE1
+ * @arg @ref LL_SYSCFG_EXTI_LINE2
+ * @arg @ref LL_SYSCFG_EXTI_LINE3
+ * @arg @ref LL_SYSCFG_EXTI_LINE4
+ * @arg @ref LL_SYSCFG_EXTI_LINE5
+ * @arg @ref LL_SYSCFG_EXTI_LINE6
+ * @arg @ref LL_SYSCFG_EXTI_LINE7
+ * @arg @ref LL_SYSCFG_EXTI_LINE8
+ * @arg @ref LL_SYSCFG_EXTI_LINE9
+ * @arg @ref LL_SYSCFG_EXTI_LINE10
+ * @arg @ref LL_SYSCFG_EXTI_LINE11
+ * @arg @ref LL_SYSCFG_EXTI_LINE12
+ * @arg @ref LL_SYSCFG_EXTI_LINE13
+ * @arg @ref LL_SYSCFG_EXTI_LINE14
+ * @arg @ref LL_SYSCFG_EXTI_LINE15
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
+{
+ MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
+}
+
+/**
+ * @brief Get the configured defined for specific EXTI Line
+ * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
+ * @param Line This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_LINE0
+ * @arg @ref LL_SYSCFG_EXTI_LINE1
+ * @arg @ref LL_SYSCFG_EXTI_LINE2
+ * @arg @ref LL_SYSCFG_EXTI_LINE3
+ * @arg @ref LL_SYSCFG_EXTI_LINE4
+ * @arg @ref LL_SYSCFG_EXTI_LINE5
+ * @arg @ref LL_SYSCFG_EXTI_LINE6
+ * @arg @ref LL_SYSCFG_EXTI_LINE7
+ * @arg @ref LL_SYSCFG_EXTI_LINE8
+ * @arg @ref LL_SYSCFG_EXTI_LINE9
+ * @arg @ref LL_SYSCFG_EXTI_LINE10
+ * @arg @ref LL_SYSCFG_EXTI_LINE11
+ * @arg @ref LL_SYSCFG_EXTI_LINE12
+ * @arg @ref LL_SYSCFG_EXTI_LINE13
+ * @arg @ref LL_SYSCFG_EXTI_LINE14
+ * @arg @ref LL_SYSCFG_EXTI_LINE15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_PORTA
+ * @arg @ref LL_SYSCFG_EXTI_PORTB
+ * @arg @ref LL_SYSCFG_EXTI_PORTC
+ * @arg @ref LL_SYSCFG_EXTI_PORTD
+ * @arg @ref LL_SYSCFG_EXTI_PORTE
+ * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
+ * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
+ * @arg @ref LL_SYSCFG_EXTI_PORTH
+ * @arg @ref LL_SYSCFG_EXTI_PORTI (*)
+ *
+ * (*) value not defined in all devices
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
+}
+
+/**
+ * @brief Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is
+ * automatically cleared at the end of the SRAM2 erase operation.)
+ * @note This bit is write-protected: setting this bit is possible only after the
+ * correct key sequence is written in the SYSCFG_SKR register as described in
+ * the Reference Manual.
+ * @rmtoll SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void)
+{
+ /* Starts a hardware SRAM2 erase operation*/
+ SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER);
+}
+
+/**
+ * @brief Check if SRAM2 erase operation is on going
+ * @rmtoll SYSCFG_SCSR SRAM2BSY LL_SYSCFG_IsSRAM2EraseOngoing
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void)
+{
+ return (READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY));
+}
+
+/**
+ * @brief Set connections to TIM1/8/15/16/17 Break inputs
+ * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
+ * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
+ * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
+ * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
+ * @param Break This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_TIMBREAK_ECC
+ * @arg @ref LL_SYSCFG_TIMBREAK_PVD
+ * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
+ * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
+{
+ MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
+}
+
+/**
+ * @brief Get connections to TIM1/8/15/16/17 Break inputs
+ * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
+ * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
+ * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
+ * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
+ * @retval Returned value can be can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_TIMBREAK_ECC
+ * @arg @ref LL_SYSCFG_TIMBREAK_PVD
+ * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
+ * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
+}
+
+/**
+ * @brief Check if SRAM2 parity error detected
+ * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
+{
+ return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF));
+}
+
+/**
+ * @brief Clear SRAM2 parity error flag
+ * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
+{
+ SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
+}
+
+/**
+ * @brief Enable SRAM2 page write protection for Pages in range 0 to 31
+ * @note Write protection is cleared only by a system reset
+ * @rmtoll SYSCFG_SWPR PxWP LL_SYSCFG_EnableSRAM2PageWRP_0_31
+ * @param SRAM2WRP This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31 (*)
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+/* Legacy define */
+#define LL_SYSCFG_EnableSRAM2PageWRP LL_SYSCFG_EnableSRAM2PageWRP_0_31
+__STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)
+{
+ SET_BIT(SYSCFG->SWPR, SRAM2WRP);
+}
+
+#if defined(SYSCFG_SWPR2_PAGE63)
+/**
+ * @brief Enable SRAM2 page write protection for Pages in range 32 to 63
+ * @note Write protection is cleared only by a system reset
+ * @rmtoll SYSCFG_SWPR2 PxWP LL_SYSCFG_EnableSRAM2PageWRP_32_63
+ * @param SRAM2WRP This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE32 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE33 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE34 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE35 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE36 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE37 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE38 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE39 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE40 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE41 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE42 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE43 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE44 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE45 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE46 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE47 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE48 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE49 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE50 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE51 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE52 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE53 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE54 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE55 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE56 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE57 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE58 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE59 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE60 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE61 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE62 (*)
+ * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE63 (*)
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)
+{
+ SET_BIT(SYSCFG->SWPR2, SRAM2WRP);
+}
+#endif /* SYSCFG_SWPR2_PAGE63 */
+
+/**
+ * @brief SRAM2 page write protection lock prior to erase
+ * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void)
+{
+ /* Writing a wrong key reactivates the write protection */
+ WRITE_REG(SYSCFG->SKR, 0x00);
+}
+
+/**
+ * @brief SRAM2 page write protection unlock prior to erase
+ * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void)
+{
+ /* unlock the write protection of the SRAM2ER bit */
+ WRITE_REG(SYSCFG->SKR, 0xCA);
+ WRITE_REG(SYSCFG->SKR, 0x53);
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+ * @{
+ */
+
+/**
+ * @brief Return the device identifier
+ * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
+ * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
+}
+
+/**
+ * @brief Return the device revision identifier
+ * @note This field indicates the revision of the device.
+ * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
+ * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
+}
+
+/**
+ * @brief Enable the Debug Module during SLEEP mode
+ * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Disable the Debug Module during SLEEP mode
+ * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Enable the Debug Module during STOP mode
+ * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Disable the Debug Module during STOP mode
+ * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Enable the Debug Module during STANDBY mode
+ * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Disable the Debug Module during STANDBY mode
+ * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Set Trace pin assignment control
+ * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
+ * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
+ * @param PinAssignment This parameter can be one of the following values:
+ * @arg @ref LL_DBGMCU_TRACE_NONE
+ * @arg @ref LL_DBGMCU_TRACE_ASYNCH
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
+{
+ MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
+}
+
+/**
+ * @brief Get Trace pin assignment control
+ * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
+ * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DBGMCU_TRACE_NONE
+ * @arg @ref LL_DBGMCU_TRACE_ASYNCH
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
+}
+
+/**
+ * @brief Freeze APB1 peripherals (group1 peripherals)
+ * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
+{
+ SET_BIT(DBGMCU->APB1FZR1, Periphs);
+}
+
+/**
+ * @brief Freeze APB1 peripherals (group2 peripherals)
+ * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
+{
+ SET_BIT(DBGMCU->APB1FZR2, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB1 peripherals (group1 peripherals)
+ * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+ CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB1 peripherals (group2 peripherals)
+ * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
+{
+ CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
+}
+
+/**
+ * @brief Freeze APB2 peripherals
+ * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
+{
+ SET_BIT(DBGMCU->APB2FZ, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB2 peripherals
+ * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+ CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
+}
+
+/**
+ * @}
+ */
+
+#if defined(VREFBUF)
+/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
+ * @{
+ */
+
+/**
+ * @brief Enable Internal voltage reference
+ * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_VREFBUF_Enable(void)
+{
+ SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+
+/**
+ * @brief Disable Internal voltage reference
+ * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_VREFBUF_Disable(void)
+{
+ CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+
+/**
+ * @brief Enable high impedance (VREF+pin is high impedance)
+ * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
+ * @retval None
+ */
+__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
+{
+ SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
+}
+
+/**
+ * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
+ * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
+ * @retval None
+ */
+__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
+{
+ CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
+}
+
+/**
+ * @brief Set the Voltage reference scale
+ * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
+ * @param Scale This parameter can be one of the following values:
+ * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
+ * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
+ * @retval None
+ */
+__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
+{
+ MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
+}
+
+/**
+ * @brief Get the Voltage reference scale
+ * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
+ * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
+ */
+__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
+{
+ return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
+}
+
+/**
+ * @brief Check if Voltage reference buffer is ready
+ * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
+{
+ return (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR));
+}
+
+/**
+ * @brief Get the trimming code for VREFBUF calibration
+ * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
+ * @retval Between 0 and 0x3F
+ */
+__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
+{
+ return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
+}
+
+/**
+ * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
+ * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
+ * @param Value Between 0 and 0x3F
+ * @retval None
+ */
+__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
+{
+ WRITE_REG(VREFBUF->CCR, Value);
+}
+
+/**
+ * @}
+ */
+#endif /* VREFBUF */
+
+/** @defgroup SYSTEM_LL_EF_FLASH FLASH
+ * @{
+ */
+
+/**
+ * @brief Set FLASH Latency
+ * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
+ * @param Latency This parameter can be one of the following values:
+ * @arg @ref LL_FLASH_LATENCY_0
+ * @arg @ref LL_FLASH_LATENCY_1
+ * @arg @ref LL_FLASH_LATENCY_2
+ * @arg @ref LL_FLASH_LATENCY_3
+ * @arg @ref LL_FLASH_LATENCY_4
+ * @arg @ref LL_FLASH_LATENCY_5 (*)
+ * @arg @ref LL_FLASH_LATENCY_6 (*)
+ * @arg @ref LL_FLASH_LATENCY_7 (*)
+ * @arg @ref LL_FLASH_LATENCY_8 (*)
+ * @arg @ref LL_FLASH_LATENCY_9 (*)
+ * @arg @ref LL_FLASH_LATENCY_10 (*)
+ * @arg @ref LL_FLASH_LATENCY_11 (*)
+ * @arg @ref LL_FLASH_LATENCY_12 (*)
+ * @arg @ref LL_FLASH_LATENCY_13 (*)
+ * @arg @ref LL_FLASH_LATENCY_14 (*)
+ * @arg @ref LL_FLASH_LATENCY_15 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
+{
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+}
+
+/**
+ * @brief Get FLASH Latency
+ * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FLASH_LATENCY_0
+ * @arg @ref LL_FLASH_LATENCY_1
+ * @arg @ref LL_FLASH_LATENCY_2
+ * @arg @ref LL_FLASH_LATENCY_3
+ * @arg @ref LL_FLASH_LATENCY_4
+ * @arg @ref LL_FLASH_LATENCY_5 (*)
+ * @arg @ref LL_FLASH_LATENCY_6 (*)
+ * @arg @ref LL_FLASH_LATENCY_7 (*)
+ * @arg @ref LL_FLASH_LATENCY_8 (*)
+ * @arg @ref LL_FLASH_LATENCY_9 (*)
+ * @arg @ref LL_FLASH_LATENCY_10 (*)
+ * @arg @ref LL_FLASH_LATENCY_11 (*)
+ * @arg @ref LL_FLASH_LATENCY_12 (*)
+ * @arg @ref LL_FLASH_LATENCY_13 (*)
+ * @arg @ref LL_FLASH_LATENCY_14 (*)
+ * @arg @ref LL_FLASH_LATENCY_15 (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
+{
+ return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+}
+
+/**
+ * @brief Enable Prefetch
+ * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
+}
+
+/**
+ * @brief Disable Prefetch
+ * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
+}
+
+/**
+ * @brief Check if Prefetch buffer is enabled
+ * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
+{
+ return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
+}
+
+/**
+ * @brief Enable Instruction cache
+ * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
+}
+
+/**
+ * @brief Disable Instruction cache
+ * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
+}
+
+/**
+ * @brief Enable Data cache
+ * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableDataCache(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
+}
+
+/**
+ * @brief Disable Data cache
+ * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableDataCache(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
+}
+
+/**
+ * @brief Enable Instruction cache reset
+ * @note bit can be written only when the instruction cache is disabled
+ * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
+}
+
+/**
+ * @brief Disable Instruction cache reset
+ * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
+}
+
+/**
+ * @brief Enable Data cache reset
+ * @note bit can be written only when the data cache is disabled
+ * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
+}
+
+/**
+ * @brief Disable Data cache reset
+ * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
+}
+
+/**
+ * @brief Enable Flash Power-down mode during run mode or Low-power run mode
+ * @note Flash memory can be put in power-down mode only when the code is executed
+ * from RAM
+ * @note Flash must not be accessed when power down is enabled
+ * @note Flash must not be put in power-down while a program or an erase operation
+ * is on-going
+ * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
+ * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n
+ * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
+{
+ /* Following values must be written consecutively to unlock the RUN_PD bit in
+ FLASH_ACR */
+ WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
+ WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
+ SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
+}
+
+/**
+ * @brief Disable Flash Power-down mode during run mode or Low-power run mode
+ * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n
+ * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n
+ * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
+{
+ /* Following values must be written consecutively to unlock the RUN_PD bit in
+ FLASH_ACR */
+ WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
+ WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
+}
+
+/**
+ * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
+ * @note Flash must not be put in power-down while a program or an erase operation
+ * is on-going
+ * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
+}
+
+/**
+ * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
+ * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L4xx_LL_SYSTEM_H */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h
new file mode 100644
index 0000000..53a2e90
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h
@@ -0,0 +1,5092 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_tim.h
+ * @author MCD Application Team
+ * @brief Header file of TIM LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_TIM_H
+#define __STM32L4xx_LL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
+
+/** @defgroup TIM_LL TIM
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Variables TIM Private Variables
+ * @{
+ */
+static const uint8_t OFFSET_TAB_CCMRx[] =
+{
+ 0x00U, /* 0: TIMx_CH1 */
+ 0x00U, /* 1: TIMx_CH1N */
+ 0x00U, /* 2: TIMx_CH2 */
+ 0x00U, /* 3: TIMx_CH2N */
+ 0x04U, /* 4: TIMx_CH3 */
+ 0x04U, /* 5: TIMx_CH3N */
+ 0x04U, /* 6: TIMx_CH4 */
+ 0x3CU, /* 7: TIMx_CH5 */
+ 0x3CU /* 8: TIMx_CH6 */
+};
+
+static const uint8_t SHIFT_TAB_OCxx[] =
+{
+ 0U, /* 0: OC1M, OC1FE, OC1PE */
+ 0U, /* 1: - NA */
+ 8U, /* 2: OC2M, OC2FE, OC2PE */
+ 0U, /* 3: - NA */
+ 0U, /* 4: OC3M, OC3FE, OC3PE */
+ 0U, /* 5: - NA */
+ 8U, /* 6: OC4M, OC4FE, OC4PE */
+ 0U, /* 7: OC5M, OC5FE, OC5PE */
+ 8U /* 8: OC6M, OC6FE, OC6PE */
+};
+
+static const uint8_t SHIFT_TAB_ICxx[] =
+{
+ 0U, /* 0: CC1S, IC1PSC, IC1F */
+ 0U, /* 1: - NA */
+ 8U, /* 2: CC2S, IC2PSC, IC2F */
+ 0U, /* 3: - NA */
+ 0U, /* 4: CC3S, IC3PSC, IC3F */
+ 0U, /* 5: - NA */
+ 8U, /* 6: CC4S, IC4PSC, IC4F */
+ 0U, /* 7: - NA */
+ 0U /* 8: - NA */
+};
+
+static const uint8_t SHIFT_TAB_CCxP[] =
+{
+ 0U, /* 0: CC1P */
+ 2U, /* 1: CC1NP */
+ 4U, /* 2: CC2P */
+ 6U, /* 3: CC2NP */
+ 8U, /* 4: CC3P */
+ 10U, /* 5: CC3NP */
+ 12U, /* 6: CC4P */
+ 16U, /* 7: CC5P */
+ 20U /* 8: CC6P */
+};
+
+static const uint8_t SHIFT_TAB_OISx[] =
+{
+ 0U, /* 0: OIS1 */
+ 1U, /* 1: OIS1N */
+ 2U, /* 2: OIS2 */
+ 3U, /* 3: OIS2N */
+ 4U, /* 4: OIS3 */
+ 5U, /* 5: OIS3N */
+ 6U, /* 6: OIS4 */
+ 8U, /* 7: OIS5 */
+ 10U /* 8: OIS6 */
+};
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Constants TIM Private Constants
+ * @{
+ */
+
+/* Defines used for the bit position in the register and perform offsets */
+#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
+
+/* Generic bit definitions for TIMx_OR2 register */
+#define TIMx_OR2_BKINP TIM1_OR2_BKINP /*!< BRK BKIN input polarity */
+#define TIMx_OR2_ETRSEL TIM1_OR2_ETRSEL /*!< TIMx ETR source selection */
+
+/* Remap mask definitions */
+#define TIMx_OR1_RMP_SHIFT 16U
+#define TIMx_OR1_RMP_MASK 0x0000FFFFU
+#if defined(ADC3)
+#define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
+#else
+#define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
+#endif /* ADC3 */
+#define TIM2_OR1_RMP_MASK ((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR1_RMP | TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT)
+#define TIM3_OR1_RMP_MASK (TIM3_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
+#if defined(ADC2) && defined(ADC3)
+#define TIM8_OR1_RMP_MASK ((TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
+#else
+#define TIM8_OR1_RMP_MASK (TIM8_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
+#endif /* ADC2 & ADC3 */
+#define TIM15_OR1_RMP_MASK (TIM15_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
+#define TIM16_OR1_RMP_MASK (TIM16_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
+#define TIM17_OR1_RMP_MASK (TIM17_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
+
+/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
+#define DT_DELAY_1 ((uint8_t)0x7F)
+#define DT_DELAY_2 ((uint8_t)0x3F)
+#define DT_DELAY_3 ((uint8_t)0x1F)
+#define DT_DELAY_4 ((uint8_t)0x1F)
+
+/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
+#define DT_RANGE_1 ((uint8_t)0x00)
+#define DT_RANGE_2 ((uint8_t)0x80)
+#define DT_RANGE_3 ((uint8_t)0xC0)
+#define DT_RANGE_4 ((uint8_t)0xE0)
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+ */
+#if defined(DFSDM1_Channel0)
+#define TIMx_OR2_BKDFBK0E TIMx_OR2_BKDF1BK0E
+#define TIMx_OR3_BK2DFBK1E TIMx_OR3_BK2DF1BK1E
+#endif /* DFSDM1_Channel0 */
+/**
+@endcond
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Macros TIM Private Macros
+ * @{
+ */
+/** @brief Convert channel id into channel index.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval none
+ */
+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+ (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
+
+/** @brief Calculate the deadtime sampling period(in ps).
+ * @param __TIMCLK__ timer input clock frequency (in Hz).
+ * @param __CKD__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @retval none
+ */
+#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
+ (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
+ ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+ ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief TIM Time Base configuration structure definition.
+ */
+typedef struct
+{
+ uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetPrescaler().*/
+
+ uint32_t CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetCounterMode().*/
+
+ uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+ Some timer instances may support 32 bits counters. In that case this parameter must
+ be a number between 0x0000 and 0xFFFFFFFF.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetAutoReload().*/
+
+ uint32_t ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetClockDivision().*/
+
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ GP timers: this parameter must be a number between Min_Data = 0x00 and
+ Max_Data = 0xFF.
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+ Max_Data = 0xFFFF.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetRepetitionCounter().*/
+} LL_TIM_InitTypeDef;
+
+/**
+ * @brief TIM Output Compare configuration structure definition.
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the output mode.
+ This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetMode().*/
+
+ uint32_t OCState; /*!< Specifies the TIM Output Compare state.
+ This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+ uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
+ This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+ uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+ This feature can be modified afterwards using unitary function
+ LL_TIM_OC_SetCompareCHx (x=1..6).*/
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetPolarity().*/
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetPolarity().*/
+
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetIdleState().*/
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetIdleState().*/
+} LL_TIM_OC_InitTypeDef;
+
+/**
+ * @brief TIM Input Capture configuration structure definition.
+ */
+
+typedef struct
+{
+
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t ICActiveInput; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetFilter().*/
+} LL_TIM_IC_InitTypeDef;
+
+
+/**
+ * @brief TIM Encoder interface configuration structure definition.
+ */
+typedef struct
+{
+ uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
+ This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetEncoderMode().*/
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
+ This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetFilter().*/
+
+ uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
+ This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetFilter().*/
+
+} LL_TIM_ENCODER_InitTypeDef;
+
+/**
+ * @brief TIM Hall sensor interface configuration structure definition.
+ */
+typedef struct
+{
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
+ Prescaler must be set to get a maximum counter period longer than the
+ time interval between 2 consecutive changes on the Hall inputs.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
+ This parameter can be a value of
+ @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetFilter().*/
+
+ uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
+ A positive pulse (TRGO event) is generated with a programmable delay every time
+ a change occurs on the Hall inputs.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetCompareCH2().*/
+} LL_TIM_HALLSENSOR_InitTypeDef;
+
+/**
+ * @brief BDTR (Break and Dead Time) structure definition
+ */
+typedef struct
+{
+ uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
+ This parameter can be a value of @ref TIM_LL_EC_OSSR
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetOffStates()
+
+ @note This bit-field cannot be modified as long as LOCK level 2 has been
+ programmed. */
+
+ uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
+ This parameter can be a value of @ref TIM_LL_EC_OSSI
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetOffStates()
+
+ @note This bit-field cannot be modified as long as LOCK level 2 has been
+ programmed. */
+
+ uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
+ This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+
+ @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
+ register has been written, their content is frozen until the next reset.*/
+
+ uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
+ switching-on of the outputs.
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetDeadTime()
+
+ @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
+ programmed. */
+
+ uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
+
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+
+ uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_ConfigBRK()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+
+ uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_ConfigBRK()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+
+ uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
+
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+
+ uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_ConfigBRK2()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+
+ uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_ConfigBRK2()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+
+ uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+ This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
+
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+} LL_TIM_BDTR_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+ * @{
+ */
+
+/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_TIM_ReadReg function.
+ * @{
+ */
+#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
+#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
+#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
+#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
+#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
+#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
+#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
+#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
+#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
+#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
+#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
+#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
+#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
+#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
+#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
+#define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+ * @{
+ */
+#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
+#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
+ * @{
+ */
+#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
+#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+ * @{
+ */
+#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
+#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
+ * @{
+ */
+#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
+#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
+#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
+#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
+#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
+#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
+#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
+#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+ * @{
+ */
+#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
+#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+ * @{
+ */
+#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+ * @{
+ */
+#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!TIMx_CCRy else active.*/
+#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/
+#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in TIM register.
+ * @param __INSTANCE__ TIM Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
+ * @{
+ */
+
+/**
+ * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
+ * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
+ * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
+ * to TIMx_CNT register bit 31)
+ * @param __CNT__ Counter value
+ * @retval UIF status bit
+ */
+#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
+ (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
+
+/**
+ * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
+ * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __CKD__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @param __DT__ deadtime duration (in ns)
+ * @retval DTG[0:7]
+ */
+#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
+ ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
+ (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
+ (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
+ (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
+ (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
+ (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
+ (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
+ (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
+ (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
+ 0U)
+
+/**
+ * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+ * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __CNTCLK__ counter clock frequency (in Hz)
+ * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
+ (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
+
+/**
+ * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+ * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __FREQ__ output signal frequency (in Hz)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+ ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
+
+/**
+ * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
+ * active/inactive delay.
+ * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @retval Compare value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
+ ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+ / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+ * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
+ * (when the timer operates in one pulse mode).
+ * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @param __PULSE__ pulse duration (in us)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
+ ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+ * @brief HELPER macro retrieving the ratio of the input capture prescaler
+ * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+ * @param __ICPSC__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+ */
+#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
+ ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+ * @{
+ */
+/**
+ * @brief Enable timer counter.
+ * @rmtoll CR1 CEN LL_TIM_EnableCounter
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+ * @brief Disable timer counter.
+ * @rmtoll CR1 CEN LL_TIM_DisableCounter
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+ * @brief Indicates whether the timer counter is enabled.
+ * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable update event generation.
+ * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+ * @brief Disable update event generation.
+ * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+ * @brief Indicates whether update event generation is enabled.
+ * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
+ * @param TIMx Timer instance
+ * @retval Inverted state of bit (0 or 1).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set update event source
+ * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+ * generate an update interrupt or DMA request if enabled:
+ * - Counter overflow/underflow
+ * - Setting the UG bit
+ * - Update generation through the slave mode controller
+ * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+ * overflow/underflow generates an update interrupt or DMA request if enabled.
+ * @rmtoll CR1 URS LL_TIM_SetUpdateSource
+ * @param TIMx Timer instance
+ * @param UpdateSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+ * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+}
+
+/**
+ * @brief Get actual event update source
+ * @rmtoll CR1 URS LL_TIM_GetUpdateSource
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+ * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+}
+
+/**
+ * @brief Set one pulse mode (one shot v.s. repetitive).
+ * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
+ * @param TIMx Timer instance
+ * @param OnePulseMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+ * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+}
+
+/**
+ * @brief Get actual one pulse mode.
+ * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+ * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+}
+
+/**
+ * @brief Set the timer counter counting mode.
+ * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * check whether or not the counter mode selection feature is supported
+ * by a timer instance.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
+ * CR1 CMS LL_TIM_SetCounterMode
+ * @param TIMx Timer instance
+ * @param CounterMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERMODE_UP
+ * @arg @ref LL_TIM_COUNTERMODE_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+{
+ MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
+}
+
+/**
+ * @brief Get actual counter mode.
+ * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * check whether or not the counter mode selection feature is supported
+ * by a timer instance.
+ * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
+ * CR1 CMS LL_TIM_GetCounterMode
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERMODE_UP
+ * @arg @ref LL_TIM_COUNTERMODE_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
+{
+ uint32_t counter_mode;
+
+ counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
+
+ if (counter_mode == 0U)
+ {
+ counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+ }
+
+ return counter_mode;
+}
+
+/**
+ * @brief Enable auto-reload (ARR) preload.
+ * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+ * @brief Disable auto-reload (ARR) preload.
+ * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+ * @brief Indicates whether auto-reload (ARR) preload is enabled.
+ * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
+ * (when supported) and the digital filters.
+ * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * whether or not the clock division feature is supported by the timer
+ * instance.
+ * @rmtoll CR1 CKD LL_TIM_SetClockDivision
+ * @param TIMx Timer instance
+ * @param ClockDivision This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+}
+
+/**
+ * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
+ * generators (when supported) and the digital filters.
+ * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * whether or not the clock division feature is supported by the timer
+ * instance.
+ * @rmtoll CR1 CKD LL_TIM_GetClockDivision
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+}
+
+/**
+ * @brief Set the counter value.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @rmtoll CNT CNT LL_TIM_SetCounter
+ * @param TIMx Timer instance
+ * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+{
+ WRITE_REG(TIMx->CNT, Counter);
+}
+
+/**
+ * @brief Get the counter value.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @rmtoll CNT CNT LL_TIM_GetCounter
+ * @param TIMx Timer instance
+ * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CNT));
+}
+
+/**
+ * @brief Get the current direction of the counter
+ * @rmtoll CR1 DIR LL_TIM_GetDirection
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERDIRECTION_UP
+ * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+}
+
+/**
+ * @brief Set the prescaler value.
+ * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+ * @note The prescaler can be changed on the fly as this control register is buffered. The new
+ * prescaler ratio is taken into account at the next update event.
+ * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+ * @rmtoll PSC PSC LL_TIM_SetPrescaler
+ * @param TIMx Timer instance
+ * @param Prescaler between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+{
+ WRITE_REG(TIMx->PSC, Prescaler);
+}
+
+/**
+ * @brief Get the prescaler value.
+ * @rmtoll PSC PSC LL_TIM_GetPrescaler
+ * @param TIMx Timer instance
+ * @retval Prescaler value between Min_Data=0 and Max_Data=65535
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->PSC));
+}
+
+/**
+ * @brief Set the auto-reload value.
+ * @note The counter is blocked while the auto-reload value is null.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+ * @rmtoll ARR ARR LL_TIM_SetAutoReload
+ * @param TIMx Timer instance
+ * @param AutoReload between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+{
+ WRITE_REG(TIMx->ARR, AutoReload);
+}
+
+/**
+ * @brief Get the auto-reload value.
+ * @rmtoll ARR ARR LL_TIM_GetAutoReload
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @param TIMx Timer instance
+ * @retval Auto-reload value
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->ARR));
+}
+
+/**
+ * @brief Set the repetition counter value.
+ * @note For advanced timer instances RepetitionCounter can be up to 65535.
+ * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a repetition counter.
+ * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
+ * @param TIMx Timer instance
+ * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
+{
+ WRITE_REG(TIMx->RCR, RepetitionCounter);
+}
+
+/**
+ * @brief Get the repetition counter value.
+ * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a repetition counter.
+ * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
+ * @param TIMx Timer instance
+ * @retval Repetition counter value
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->RCR));
+}
+
+/**
+ * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+ * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
+ * in an atomic way.
+ * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+ * @brief Disable update interrupt flag (UIF) remapping.
+ * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+ * @brief Indicate whether update interrupt flag (UIF) copy is set.
+ * @param Counter Counter value
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
+{
+ return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+ * @{
+ */
+/**
+ * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+ * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
+ * they are updated only when a commutation event (COM) occurs.
+ * @note Only on channels that have a complementary output.
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation event.
+ * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+ * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation event.
+ * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+ * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation event.
+ * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
+ * @param TIMx Timer instance
+ * @param CCUpdateSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
+ * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
+}
+
+/**
+ * @brief Set the trigger of the capture/compare DMA request.
+ * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
+ * @param TIMx Timer instance
+ * @param DMAReqTrigger This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CCDMAREQUEST_CC
+ * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+}
+
+/**
+ * @brief Get actual trigger of the capture/compare DMA request.
+ * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_CCDMAREQUEST_CC
+ * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+}
+
+/**
+ * @brief Set the lock level to freeze the
+ * configuration of several capture/compare parameters.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * the lock mechanism is supported by a timer instance.
+ * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
+ * @param TIMx Timer instance
+ * @param LockLevel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_LOCKLEVEL_OFF
+ * @arg @ref LL_TIM_LOCKLEVEL_1
+ * @arg @ref LL_TIM_LOCKLEVEL_2
+ * @arg @ref LL_TIM_LOCKLEVEL_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
+}
+
+/**
+ * @brief Enable capture/compare channels.
+ * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
+ * CCER CC1NE LL_TIM_CC_EnableChannel\n
+ * CCER CC2E LL_TIM_CC_EnableChannel\n
+ * CCER CC2NE LL_TIM_CC_EnableChannel\n
+ * CCER CC3E LL_TIM_CC_EnableChannel\n
+ * CCER CC3NE LL_TIM_CC_EnableChannel\n
+ * CCER CC4E LL_TIM_CC_EnableChannel\n
+ * CCER CC5E LL_TIM_CC_EnableChannel\n
+ * CCER CC6E LL_TIM_CC_EnableChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+ SET_BIT(TIMx->CCER, Channels);
+}
+
+/**
+ * @brief Disable capture/compare channels.
+ * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
+ * CCER CC1NE LL_TIM_CC_DisableChannel\n
+ * CCER CC2E LL_TIM_CC_DisableChannel\n
+ * CCER CC2NE LL_TIM_CC_DisableChannel\n
+ * CCER CC3E LL_TIM_CC_DisableChannel\n
+ * CCER CC3NE LL_TIM_CC_DisableChannel\n
+ * CCER CC4E LL_TIM_CC_DisableChannel\n
+ * CCER CC5E LL_TIM_CC_DisableChannel\n
+ * CCER CC6E LL_TIM_CC_DisableChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+ CLEAR_BIT(TIMx->CCER, Channels);
+}
+
+/**
+ * @brief Indicate whether channel(s) is(are) enabled.
+ * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC6E LL_TIM_CC_IsEnabledChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+ return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+ * @{
+ */
+/**
+ * @brief Configure an output channel.
+ * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
+ * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
+ * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
+ * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
+ * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
+ * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
+ * CCER CC1P LL_TIM_OC_ConfigOutput\n
+ * CCER CC2P LL_TIM_OC_ConfigOutput\n
+ * CCER CC3P LL_TIM_OC_ConfigOutput\n
+ * CCER CC4P LL_TIM_OC_ConfigOutput\n
+ * CCER CC5P LL_TIM_OC_ConfigOutput\n
+ * CCER CC6P LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS6 LL_TIM_OC_ConfigOutput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+ (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+ MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+ (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Define the behavior of the output reference signal OCxREF from which
+ * OCx and OCxN (when relevant) are derived.
+ * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
+ * CCMR1 OC2M LL_TIM_OC_SetMode\n
+ * CCMR2 OC3M LL_TIM_OC_SetMode\n
+ * CCMR2 OC4M LL_TIM_OC_SetMode\n
+ * CCMR3 OC5M LL_TIM_OC_SetMode\n
+ * CCMR3 OC6M LL_TIM_OC_SetMode
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCMODE_FROZEN
+ * @arg @ref LL_TIM_OCMODE_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_TOGGLE
+ * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_PWM1
+ * @arg @ref LL_TIM_OCMODE_PWM2
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+ * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
+ * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+ * @brief Get the output compare mode of an output channel.
+ * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
+ * CCMR1 OC2M LL_TIM_OC_GetMode\n
+ * CCMR2 OC3M LL_TIM_OC_GetMode\n
+ * CCMR2 OC4M LL_TIM_OC_GetMode\n
+ * CCMR3 OC5M LL_TIM_OC_GetMode\n
+ * CCMR3 OC6M LL_TIM_OC_GetMode
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCMODE_FROZEN
+ * @arg @ref LL_TIM_OCMODE_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_TOGGLE
+ * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_PWM1
+ * @arg @ref LL_TIM_OCMODE_PWM2
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+ * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
+ * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+ * @brief Set the polarity of an output channel.
+ * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
+ * CCER CC1NP LL_TIM_OC_SetPolarity\n
+ * CCER CC2P LL_TIM_OC_SetPolarity\n
+ * CCER CC2NP LL_TIM_OC_SetPolarity\n
+ * CCER CC3P LL_TIM_OC_SetPolarity\n
+ * CCER CC3NP LL_TIM_OC_SetPolarity\n
+ * CCER CC4P LL_TIM_OC_SetPolarity\n
+ * CCER CC5P LL_TIM_OC_SetPolarity\n
+ * CCER CC6P LL_TIM_OC_SetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH
+ * @arg @ref LL_TIM_OCPOLARITY_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Get the polarity of an output channel.
+ * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
+ * CCER CC1NP LL_TIM_OC_GetPolarity\n
+ * CCER CC2P LL_TIM_OC_GetPolarity\n
+ * CCER CC2NP LL_TIM_OC_GetPolarity\n
+ * CCER CC3P LL_TIM_OC_GetPolarity\n
+ * CCER CC3NP LL_TIM_OC_GetPolarity\n
+ * CCER CC4P LL_TIM_OC_GetPolarity\n
+ * CCER CC5P LL_TIM_OC_GetPolarity\n
+ * CCER CC6P LL_TIM_OC_GetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH
+ * @arg @ref LL_TIM_OCPOLARITY_LOW
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Set the IDLE state of an output channel
+ * @note This function is significant only for the timer instances
+ * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
+ * can be used to check whether or not a timer instance provides
+ * a break input.
+ * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS2 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS3 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS3N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS4 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS5 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS6 LL_TIM_OC_SetIdleState
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param IdleState This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Get the IDLE state of an output channel
+ * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS2 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS3 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS3N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS4 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS5 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS6 LL_TIM_OC_GetIdleState
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_HIGH
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Enable fast mode for the output channel.
+ * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
+ * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
+ * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
+ * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
+ * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_EnableFast
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+ * @brief Disable fast mode for the output channel.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
+ * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
+ * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
+ * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
+ * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_DisableFast
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+ * @brief Indicates whether fast mode is enabled for the output channel.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+ return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
+ * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
+ * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
+ * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
+ * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
+ * CCMR3 OC6PE LL_TIM_OC_EnablePreload
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
+ * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
+ * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
+ * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
+ * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
+ * CCMR3 OC6PE LL_TIM_OC_DisablePreload
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+ return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable clearing the output channel on an external event.
+ * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
+ * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
+ * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
+ * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
+ * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
+ * CCMR3 OC6CE LL_TIM_OC_EnableClear
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Disable clearing the output channel on an external event.
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
+ * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
+ * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
+ * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
+ * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
+ * CCMR3 OC6CE LL_TIM_OC_DisableClear
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
+ * @note This function enables clearing the output channel on an external event.
+ * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+ return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
+ * the Ocx and OCxN signals).
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * dead-time insertion feature is supported by a timer instance.
+ * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+ * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
+ * @param TIMx Timer instance
+ * @param DeadTime between Min_Data=0 and Max_Data=255
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
+}
+
+/**
+ * @brief Set compare value for output channel 1 (TIMx_CCR1).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 1 is supported by a timer instance.
+ * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR1, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 2 (TIMx_CCR2).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 2 is supported by a timer instance.
+ * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR2, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 3 (TIMx_CCR3).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * output channel is supported by a timer instance.
+ * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR3, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 4 (TIMx_CCR4).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 4 is supported by a timer instance.
+ * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR4, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 5 (TIMx_CCR5).
+ * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 5 is supported by a timer instance.
+ * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 6 (TIMx_CCR6).
+ * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 6 is supported by a timer instance.
+ * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR6, CompareValue);
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR1) set for output channel 1.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 1 is supported by a timer instance.
+ * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR2) set for output channel 2.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 2 is supported by a timer instance.
+ * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR3) set for output channel 3.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 3 is supported by a timer instance.
+ * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR4) set for output channel 4.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 4 is supported by a timer instance.
+ * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR5) set for output channel 5.
+ * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 5 is supported by a timer instance.
+ * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR6) set for output channel 6.
+ * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 6 is supported by a timer instance.
+ * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR6));
+}
+
+/**
+ * @brief Select on which reference signal the OC5REF is combined to.
+ * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the combined 3-phase PWM mode.
+ * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
+ * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
+ * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
+ * @param TIMx Timer instance
+ * @param GroupCH5 This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_GROUPCH5_NONE
+ * @arg @ref LL_TIM_GROUPCH5_OC1REFC
+ * @arg @ref LL_TIM_GROUPCH5_OC2REFC
+ * @arg @ref LL_TIM_GROUPCH5_OC3REFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
+{
+ MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+ * @{
+ */
+/**
+ * @brief Configure input channel.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
+ * CCMR1 IC1PSC LL_TIM_IC_Config\n
+ * CCMR1 IC1F LL_TIM_IC_Config\n
+ * CCMR1 CC2S LL_TIM_IC_Config\n
+ * CCMR1 IC2PSC LL_TIM_IC_Config\n
+ * CCMR1 IC2F LL_TIM_IC_Config\n
+ * CCMR2 CC3S LL_TIM_IC_Config\n
+ * CCMR2 IC3PSC LL_TIM_IC_Config\n
+ * CCMR2 IC3F LL_TIM_IC_Config\n
+ * CCMR2 CC4S LL_TIM_IC_Config\n
+ * CCMR2 IC4PSC LL_TIM_IC_Config\n
+ * CCMR2 IC4F LL_TIM_IC_Config\n
+ * CCER CC1P LL_TIM_IC_Config\n
+ * CCER CC1NP LL_TIM_IC_Config\n
+ * CCER CC2P LL_TIM_IC_Config\n
+ * CCER CC2NP LL_TIM_IC_Config\n
+ * CCER CC3P LL_TIM_IC_Config\n
+ * CCER CC3NP LL_TIM_IC_Config\n
+ * CCER CC4P LL_TIM_IC_Config\n
+ * CCER CC4NP LL_TIM_IC_Config
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
+ * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+ * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
+ ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
+ << SHIFT_TAB_ICxx[iChannel]);
+ MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+ (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Set the active input.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
+ * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
+ * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
+ * CCMR2 CC4S LL_TIM_IC_SetActiveInput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICActiveInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_TRC
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the current active input.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
+ * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
+ * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
+ * CCMR2 CC4S LL_TIM_IC_GetActiveInput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_TRC
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+ * @brief Set the prescaler of input channel.
+ * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the current prescaler value acting on an input channel.
+ * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+ * @brief Set the input filter duration.
+ * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
+ * CCMR1 IC2F LL_TIM_IC_SetFilter\n
+ * CCMR2 IC3F LL_TIM_IC_SetFilter\n
+ * CCMR2 IC4F LL_TIM_IC_SetFilter
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the input filter duration.
+ * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
+ * CCMR1 IC2F LL_TIM_IC_GetFilter\n
+ * CCMR2 IC3F LL_TIM_IC_GetFilter\n
+ * CCMR2 IC4F LL_TIM_IC_GetFilter
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+ * @brief Set the input channel polarity.
+ * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
+ * CCER CC1NP LL_TIM_IC_SetPolarity\n
+ * CCER CC2P LL_TIM_IC_SetPolarity\n
+ * CCER CC2NP LL_TIM_IC_SetPolarity\n
+ * CCER CC3P LL_TIM_IC_SetPolarity\n
+ * CCER CC3NP LL_TIM_IC_SetPolarity\n
+ * CCER CC4P LL_TIM_IC_SetPolarity\n
+ * CCER CC4NP LL_TIM_IC_SetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_IC_POLARITY_RISING
+ * @arg @ref LL_TIM_IC_POLARITY_FALLING
+ * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+ ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Get the current input channel polarity.
+ * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
+ * CCER CC1NP LL_TIM_IC_GetPolarity\n
+ * CCER CC2P LL_TIM_IC_GetPolarity\n
+ * CCER CC2NP LL_TIM_IC_GetPolarity\n
+ * CCER CC3P LL_TIM_IC_GetPolarity\n
+ * CCER CC3NP LL_TIM_IC_GetPolarity\n
+ * CCER CC4P LL_TIM_IC_GetPolarity\n
+ * CCER CC4NP LL_TIM_IC_GetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_IC_POLARITY_RISING
+ * @arg @ref LL_TIM_IC_POLARITY_FALLING
+ * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+ SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+ * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+ * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get captured value for input channel 1.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 1 is supported by a timer instance.
+ * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+ * @brief Get captured value for input channel 2.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 2 is supported by a timer instance.
+ * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+ * @brief Get captured value for input channel 3.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 3 is supported by a timer instance.
+ * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+ * @brief Get captured value for input channel 4.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 4 is supported by a timer instance.
+ * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+ * @{
+ */
+/**
+ * @brief Enable external clock mode 2.
+ * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+ * @brief Disable external clock mode 2.
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+ * @brief Indicate whether external clock mode 2 is enabled.
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the clock source of the counter clock.
+ * @note when selected clock source is external clock mode 1, the timer input
+ * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+ * function. This timer input must be configured by calling
+ * the @ref LL_TIM_IC_Config() function.
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode1.
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
+ * SMCR ECE LL_TIM_SetClockSource
+ * @param TIMx Timer instance
+ * @param ClockSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+ * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+ * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+}
+
+/**
+ * @brief Set the encoder interface mode.
+ * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the encoder mode.
+ * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
+ * @param TIMx Timer instance
+ * @param EncoderMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+ * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+ * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+ * @{
+ */
+/**
+ * @brief Set the trigger output (TRGO) used for timer synchronization .
+ * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance can operate as a master timer.
+ * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
+ * @param TIMx Timer instance
+ * @param TimerSynchronization This parameter can be one of the following values:
+ * @arg @ref LL_TIM_TRGO_RESET
+ * @arg @ref LL_TIM_TRGO_ENABLE
+ * @arg @ref LL_TIM_TRGO_UPDATE
+ * @arg @ref LL_TIM_TRGO_CC1IF
+ * @arg @ref LL_TIM_TRGO_OC1REF
+ * @arg @ref LL_TIM_TRGO_OC2REF
+ * @arg @ref LL_TIM_TRGO_OC3REF
+ * @arg @ref LL_TIM_TRGO_OC4REF
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+}
+
+/**
+ * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
+ * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance can be used for ADC synchronization.
+ * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
+ * @param TIMx Timer Instance
+ * @param ADCSynchronization This parameter can be one of the following values:
+ * @arg @ref LL_TIM_TRGO2_RESET
+ * @arg @ref LL_TIM_TRGO2_ENABLE
+ * @arg @ref LL_TIM_TRGO2_UPDATE
+ * @arg @ref LL_TIM_TRGO2_CC1F
+ * @arg @ref LL_TIM_TRGO2_OC1
+ * @arg @ref LL_TIM_TRGO2_OC2
+ * @arg @ref LL_TIM_TRGO2_OC3
+ * @arg @ref LL_TIM_TRGO2_OC4
+ * @arg @ref LL_TIM_TRGO2_OC5
+ * @arg @ref LL_TIM_TRGO2_OC6
+ * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
+ * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
+ * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
+ * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
+ * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
+ * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
+}
+
+/**
+ * @brief Set the synchronization mode of a slave timer.
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
+ * @param TIMx Timer instance
+ * @param SlaveMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_SLAVEMODE_DISABLED
+ * @arg @ref LL_TIM_SLAVEMODE_RESET
+ * @arg @ref LL_TIM_SLAVEMODE_GATED
+ * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+ * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+}
+
+/**
+ * @brief Set the selects the trigger input to be used to synchronize the counter.
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR TS LL_TIM_SetTriggerInput
+ * @param TIMx Timer instance
+ * @param TriggerInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_TS_ITR0
+ * @arg @ref LL_TIM_TS_ITR1
+ * @arg @ref LL_TIM_TS_ITR2
+ * @arg @ref LL_TIM_TS_ITR3
+ * @arg @ref LL_TIM_TS_TI1F_ED
+ * @arg @ref LL_TIM_TS_TI1FP1
+ * @arg @ref LL_TIM_TS_TI2FP2
+ * @arg @ref LL_TIM_TS_ETRF
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+}
+
+/**
+ * @brief Enable the Master/Slave mode.
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+ * @brief Disable the Master/Slave mode.
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+ * @brief Indicates whether the Master/Slave mode is enabled.
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the external trigger (ETR) input.
+ * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an external trigger input.
+ * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
+ * SMCR ETPS LL_TIM_ConfigETR\n
+ * SMCR ETF LL_TIM_ConfigETR
+ * @param TIMx Timer instance
+ * @param ETRPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+ * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+ * @param ETRPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+ * @param ETRFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
+ uint32_t ETRFilter)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
+}
+
+/**
+ * @brief Select the external trigger (ETR) input source.
+ * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
+ * not a timer instance supports ETR source selection.
+ * @rmtoll OR2 ETRSEL LL_TIM_SetETRSource
+ * @param TIMx Timer instance
+ * @param ETRSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETRSOURCE_LEGACY
+ * @arg @ref LL_TIM_ETRSOURCE_COMP1
+ * @arg @ref LL_TIM_ETRSOURCE_COMP2
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
+{
+ MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Break_Function Break function configuration
+ * @{
+ */
+/**
+ * @brief Enable the break function.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR BKE LL_TIM_EnableBRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+ * @brief Disable the break function.
+ * @rmtoll BDTR BKE LL_TIM_DisableBRK
+ * @param TIMx Timer instance
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+ * @brief Configure the break input.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
+ * BDTR BKF LL_TIM_ConfigBRK
+ * @param TIMx Timer instance
+ * @param BreakPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_POLARITY_LOW
+ * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+ * @param BreakFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
+ uint32_t BreakFilter)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
+}
+
+/**
+ * @brief Enable the break 2 function.
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+ * @brief Disable the break 2 function.
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+ * @brief Configure the break 2 input.
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
+ * BDTR BK2F LL_TIM_ConfigBRK2
+ * @param TIMx Timer instance
+ * @param Break2Polarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
+ * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
+ * @param Break2Filter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
+}
+
+/**
+ * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
+ * BDTR OSSR LL_TIM_SetOffStates
+ * @param TIMx Timer instance
+ * @param OffStateIdle This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OSSI_DISABLE
+ * @arg @ref LL_TIM_OSSI_ENABLE
+ * @param OffStateRun This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OSSR_DISABLE
+ * @arg @ref LL_TIM_OSSR_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
+}
+
+/**
+ * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+ * @brief Disable automatic output (MOE can be set only by software).
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+ * @brief Indicate whether automatic output is enabled.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
+ * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+ * software and is reset in case of break or break2 event
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+ * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
+ * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+ * software and is reset in case of break or break2 event.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+ * @brief Indicates whether outputs are enabled.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the signals connected to the designated timer break input.
+ * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance allows for break input selection.
+ * @rmtoll OR2 BKINE LL_TIM_EnableBreakInputSource\n
+ * OR2 BKCMP1E LL_TIM_EnableBreakInputSource\n
+ * OR2 BKCMP2E LL_TIM_EnableBreakInputSource\n
+ * OR2 BKDF1BK0E LL_TIM_EnableBreakInputSource\n
+ * OR3 BK2INE LL_TIM_EnableBreakInputSource\n
+ * OR3 BK2CMP1E LL_TIM_EnableBreakInputSource\n
+ * OR3 BK2CMP2E LL_TIM_EnableBreakInputSource\n
+ * OR3 BK2DF1BK1E LL_TIM_EnableBreakInputSource
+ * @param TIMx Timer instance
+ * @param BreakInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_INPUT_BKIN
+ * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+ * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
+{
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
+ SET_BIT(*pReg, Source);
+}
+
+/**
+ * @brief Disable the signals connected to the designated timer break input.
+ * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance allows for break input selection.
+ * @rmtoll OR2 BKINE LL_TIM_DisableBreakInputSource\n
+ * OR2 BKCMP1E LL_TIM_DisableBreakInputSource\n
+ * OR2 BKCMP2E LL_TIM_DisableBreakInputSource\n
+ * OR2 BKDF1BK0E LL_TIM_DisableBreakInputSource\n
+ * OR3 BK2INE LL_TIM_DisableBreakInputSource\n
+ * OR3 BK2CMP1E LL_TIM_DisableBreakInputSource\n
+ * OR3 BK2CMP2E LL_TIM_DisableBreakInputSource\n
+ * OR3 BK2DF1BK1E LL_TIM_DisableBreakInputSource
+ * @param TIMx Timer instance
+ * @param BreakInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_INPUT_BKIN
+ * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+ * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
+{
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
+ CLEAR_BIT(*pReg, Source);
+}
+
+/**
+ * @brief Set the polarity of the break signal for the timer break input.
+ * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance allows for break input selection.
+ * @rmtoll OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n
+ * OR2 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
+ * OR2 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
+ * OR3 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
+ * OR3 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
+ * OR3 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
+ * @param TIMx Timer instance
+ * @param BreakInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_INPUT_BKIN
+ * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
+ * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BKIN_POLARITY_LOW
+ * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
+ uint32_t Polarity)
+{
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
+ MODIFY_REG(*pReg, (TIMx_OR2_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+ * @{
+ */
+/**
+ * @brief Configures the timer DMA burst feature.
+ * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+ * not a timer instance supports the DMA burst mode.
+ * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
+ * DCR DBA LL_TIM_ConfigDMABurst
+ * @param TIMx Timer instance
+ * @param DMABurstBaseAddress This parameter can be one of the following values:
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_OR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_OR3
+ * @param DMABurstLength This parameter can be one of the following values:
+ * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+ * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
+{
+ MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
+ * @{
+ */
+/**
+ * @brief Remap TIM inputs (input channel, internal/external triggers).
+ * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+ * a some timer inputs can be remapped.
+ @if STM32L486xx
+ * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n
+ * TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
+ * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n
+ * TIM8_OR1 ETR_ADC2_RMP LL_TIM_SetRemap\n
+ * TIM8_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
+ * TIM8_OR1 TI1_RMP LL_TIM_SetRemap\n
+ * TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n
+ * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n
+ * TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n
+ * TIM3_OR1 TI1_RMP LL_TIM_SetRemap\n
+ * TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n
+ * TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n
+ * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n
+ * TIM17_OR1 TI1_RMP LL_TIM_SetRemap
+ @endif
+ @if STM32L443xx
+ * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n
+ * TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
+ * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n
+ * TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n
+ * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n
+ * TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n
+ * TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n
+ * TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n
+ * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n
+ @endif
+ * @param TIMx Timer instance
+ * @param Remap Remap param depends on the TIMx. Description available only
+ * in CHM version of the User Manual (not in .pdf).
+ * Otherwise see Reference Manual description of OR registers.
+ *
+ * Below description summarizes "Timer Instance" and "Remap" param combinations:
+ *
+ @if STM32L486xx
+ * TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
+ *
+ * . . ADC1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
+ * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
+ * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
+ * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
+ *
+ * . . ADC3_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC
+ * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1
+ * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2
+ * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3
+ *
+ * . . TI1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
+ * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
+ *
+ * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
+ *
+ * ITR1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
+ * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
+ *
+ * . . ETR1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
+ * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
+ *
+ * . . TI4_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
+ * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
+ * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
+ * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
+ *
+ * TIM3: one of the following values
+ *
+ * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
+ * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
+ * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
+ * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1_COMP2
+ *
+ * TIM8: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
+ *
+ * . . ADC1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC
+ * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1
+ * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2
+ * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3
+ *
+ * . . ADC3_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC
+ * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1
+ * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2
+ * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3
+ *
+ * . . TI1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
+ * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
+ *
+ * TIM15: any combination of TI1_RMP, ENCODER_MODE where
+ *
+ * . . TI1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
+ * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
+ *
+ * . . ENCODER_MODE can be one of the following values
+ * @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
+ * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2
+ * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
+ * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
+ *
+ * TIM16: one of the following values
+ *
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_MSI
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
+ *
+ * TIM17: one of the following values
+ *
+ * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
+ * @arg @ref LL_TIM_TIM17_TI1_RMP_MSI
+ * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
+ * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
+ @endif
+ @if STM32L443xx
+ * TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
+ *
+ * . . ADC1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
+ * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
+ * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
+ * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
+ *
+ * . . TI1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
+ * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
+ *
+ * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
+ *
+ * ITR1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM2_ITR1_RMP_NONE
+ * @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF
+ *
+ * . . ETR1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
+ * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
+ *
+ * . . TI4_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
+ * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
+ * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
+ * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
+ *
+ * TIM15: any combination of TI1_RMP, ENCODER_MODE where
+ *
+ * . . TI1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
+ * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
+ *
+ * . . ENCODER_MODE can be one of the following values
+ * @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
+ * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2
+ * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
+ * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
+ *
+ * TIM16: one of the following values
+ *
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_MSI
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
+ @endif
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
+{
+ MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
+ * @{
+ */
+/**
+ * @brief Set the OCREF clear input source
+ * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
+ * @note This function can only be used in Output compare and PWM modes.
+ * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
+ * @param TIMx Timer instance
+ * @param OCRefClearInputSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCREF_CLR_INT_NC
+ * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+ * @{
+ */
+/**
+ * @brief Clear the update interrupt flag (UIF).
+ * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+}
+
+/**
+ * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+ * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
+ * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
+ * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
+ * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
+ * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
+ * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
+ * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
+ * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
+ * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
+ * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
+ * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
+ * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
+ * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the commutation interrupt flag (COMIF).
+ * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
+}
+
+/**
+ * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
+ * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the trigger interrupt flag (TIF).
+ * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+}
+
+/**
+ * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
+ * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the break interrupt flag (BIF).
+ * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
+}
+
+/**
+ * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
+ * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the break 2 interrupt flag (B2IF).
+ * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
+}
+
+/**
+ * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
+ * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+ * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
+ * (Capture/Compare 1 interrupt is pending).
+ * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+ * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
+ * (Capture/Compare 2 over-capture interrupt is pending).
+ * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+ * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
+ * (Capture/Compare 3 over-capture interrupt is pending).
+ * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+ * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
+ * (Capture/Compare 4 over-capture interrupt is pending).
+ * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the system break interrupt flag (SBIF).
+ * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
+}
+
+/**
+ * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
+ * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_IT_Management IT-Management
+ * @{
+ */
+/**
+ * @brief Enable update interrupt (UIE).
+ * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+ * @brief Disable update interrupt (UIE).
+ * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+ * @brief Indicates whether the update interrupt (UIE) is enabled.
+ * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 1 interrupt (CC1IE).
+ * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+ * @brief Disable capture/compare 1 interrupt (CC1IE).
+ * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+ * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 2 interrupt (CC2IE).
+ * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+ * @brief Disable capture/compare 2 interrupt (CC2IE).
+ * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+ * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 3 interrupt (CC3IE).
+ * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+ * @brief Disable capture/compare 3 interrupt (CC3IE).
+ * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
+ * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 4 interrupt (CC4IE).
+ * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+ * @brief Disable capture/compare 4 interrupt (CC4IE).
+ * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
+ * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable commutation interrupt (COMIE).
+ * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+ * @brief Disable commutation interrupt (COMIE).
+ * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+ * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
+ * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable trigger interrupt (TIE).
+ * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+ * @brief Disable trigger interrupt (TIE).
+ * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+ * @brief Indicates whether the trigger interrupt (TIE) is enabled.
+ * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable break interrupt (BIE).
+ * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+ * @brief Disable break interrupt (BIE).
+ * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+ * @brief Indicates whether the break interrupt (BIE) is enabled.
+ * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA Management
+ * @{
+ */
+/**
+ * @brief Enable update DMA request (UDE).
+ * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+ * @brief Disable update DMA request (UDE).
+ * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+ * @brief Indicates whether the update DMA request (UDE) is enabled.
+ * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 1 DMA request (CC1DE).
+ * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+ * @brief Disable capture/compare 1 DMA request (CC1DE).
+ * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+ * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 2 DMA request (CC2DE).
+ * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+ * @brief Disable capture/compare 2 DMA request (CC2DE).
+ * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+ * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 3 DMA request (CC3DE).
+ * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+ * @brief Disable capture/compare 3 DMA request (CC3DE).
+ * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
+ * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture/compare 4 DMA request (CC4DE).
+ * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+ * @brief Disable capture/compare 4 DMA request (CC4DE).
+ * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
+ * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable commutation DMA request (COMDE).
+ * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+ * @brief Disable commutation DMA request (COMDE).
+ * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+ * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
+ * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable trigger interrupt (TDE).
+ * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+ * @brief Disable trigger interrupt (TDE).
+ * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+ * @brief Indicates whether the trigger interrupt (TDE) is enabled.
+ * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
+ * @{
+ */
+/**
+ * @brief Generate an update event.
+ * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_UG);
+}
+
+/**
+ * @brief Generate Capture/Compare 1 event.
+ * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
+}
+
+/**
+ * @brief Generate Capture/Compare 2 event.
+ * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
+}
+
+/**
+ * @brief Generate Capture/Compare 3 event.
+ * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
+}
+
+/**
+ * @brief Generate Capture/Compare 4 event.
+ * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
+}
+
+/**
+ * @brief Generate commutation event.
+ * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_COMG);
+}
+
+/**
+ * @brief Generate trigger event.
+ * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_TG);
+}
+
+/**
+ * @brief Generate break event.
+ * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_BG);
+}
+
+/**
+ * @brief Generate break 2 event.
+ * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_B2G);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
+ * @{
+ */
+
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_TIM_H */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h
new file mode 100644
index 0000000..05aa926
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h
@@ -0,0 +1,4701 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_usart.h
+ * @author MCD Application Team
+ * @brief Header file of USART LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L4xx_LL_USART_H
+#define STM32L4xx_LL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
+
+/** @defgroup USART_LL USART
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+#if defined(USART_PRESC_PRESCALER)
+/** @defgroup USART_LL_Private_Variables USART Private Variables
+ * @{
+ */
+/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
+static const uint32_t USART_PRESCALER_TAB[] =
+{
+ 1UL,
+ 2UL,
+ 4UL,
+ 6UL,
+ 8UL,
+ 10UL,
+ 12UL,
+ 16UL,
+ 32UL,
+ 64UL,
+ 128UL,
+ 256UL
+};
+/**
+ * @}
+ */
+#endif /* USART_PRESC_PRESCALER */
+
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_Private_Macros USART Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_ES_INIT USART Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL USART Init Structure definition
+ */
+typedef struct
+{
+#if defined(USART_PRESC_PRESCALER)
+ uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
+ This parameter can be a value of @ref USART_LL_EC_PRESCALER.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetPrescaler().*/
+#endif /* USART_PRESC_PRESCALER */
+
+ uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetBaudRate().*/
+
+ uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetDataWidth().*/
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_LL_EC_STOPBITS.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetStopBitsLength().*/
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_LL_EC_PARITY.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetParity().*/
+
+ uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_LL_EC_DIRECTION.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetTransferDirection().*/
+
+ uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+ This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetHWFlowCtrl().*/
+
+ uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8.
+ This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
+
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetOverSampling().*/
+
+} LL_USART_InitTypeDef;
+
+/**
+ * @brief LL USART Clock Init Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled.
+ This parameter can be a value of @ref USART_LL_EC_CLOCK.
+
+ USART HW configuration can be modified afterwards using unitary functions
+ @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
+ For more details, refer to description of this function. */
+
+ uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref USART_LL_EC_POLARITY.
+
+ USART HW configuration can be modified afterwards using unitary
+ functions @ref LL_USART_SetClockPolarity().
+ For more details, refer to description of this function. */
+
+ uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_LL_EC_PHASE.
+
+ USART HW configuration can be modified afterwards using unitary
+ functions @ref LL_USART_SetClockPhase().
+ For more details, refer to description of this function. */
+
+ uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
+
+ USART HW configuration can be modified afterwards using unitary
+ functions @ref LL_USART_SetLastClkPulseOutput().
+ For more details, refer to description of this function. */
+
+} LL_USART_ClockInitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Constants USART Exported Constants
+ * @{
+ */
+
+/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_USART_WriteReg function
+ * @{
+ */
+#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
+#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
+#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */
+#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
+#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
+#if defined(USART_CR1_FIFOEN)
+#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */
+#endif /* USART_CR1_FIFOEN */
+#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
+#if defined(USART_TCBGT_SUPPORT)
+#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */
+#endif /* USART_TCBGT_SUPPORT */
+#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */
+#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
+#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */
+#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */
+#if defined(USART_CR2_SLVEN)
+#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */
+#endif /* USART_CR2_SLVEN */
+#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
+#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_USART_ReadReg function
+ * @{
+ */
+#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */
+#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */
+#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
+#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
+#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
+#if defined(USART_CR1_FIFOEN)
+#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
+#else
+#define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */
+#endif /* USART_CR1_FIFOEN */
+#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
+#if defined(USART_CR1_FIFOEN)
+#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
+#else
+#define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */
+#endif /* USART_CR1_FIFOEN */
+#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */
+#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
+#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
+#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */
+#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */
+#if defined(USART_CR2_SLVEN)
+#define LL_USART_ISR_UDR USART_ISR_UDR /*!< SPI Slave underrun error flag */
+#endif /* USART_CR2_SLVEN */
+#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */
+#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */
+#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
+#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
+#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
+#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
+#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
+#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
+#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
+#if defined(USART_CR1_FIFOEN)
+#define LL_USART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
+#define LL_USART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
+#endif /* USART_CR1_FIFOEN */
+#if defined(USART_TCBGT_SUPPORT)
+#define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */
+#endif /* USART_TCBGT_SUPPORT */
+#if defined(USART_CR1_FIFOEN)
+#define LL_USART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
+#define LL_USART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
+#endif /* USART_CR1_FIFOEN */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions
+ * @{
+ */
+#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
+#if defined(USART_CR1_FIFOEN)
+#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */
+#else
+#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */
+#endif /* USART_CR1_FIFOEN */
+#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
+#if defined(USART_CR1_FIFOEN)
+#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */
+#else
+#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */
+#endif /* USART_CR1_FIFOEN */
+#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
+#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
+#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */
+#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */
+#if defined(USART_CR1_FIFOEN)
+#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
+#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
+#endif /* USART_CR1_FIFOEN */
+#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */
+#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
+#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
+#define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
+#if defined(USART_CR1_FIFOEN)
+#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
+#endif /* USART_CR1_FIFOEN */
+#if defined(USART_TCBGT_SUPPORT)
+#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */
+#endif /* USART_TCBGT_SUPPORT */
+#if defined(USART_CR1_FIFOEN)
+#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
+#endif /* USART_CR1_FIFOEN */
+/**
+ * @}
+ */
+
+#if defined(USART_CR1_FIFOEN)
+/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
+ * @{
+ */
+#define LL_USART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */
+#define LL_USART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
+/**
+ * @}
+ */
+
+#endif /* USART_CR1_FIFOEN */
+/** @defgroup USART_LL_EC_DIRECTION Communication Direction
+ * @{
+ */
+#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_PARITY Parity Control
+ * @{
+ */
+#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
+#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
+#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_WAKEUP Wakeup
+ * @{
+ */
+#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+ * @{
+ */
+#define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+ * @{
+ */
+#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EC_CLOCK Clock Signal
+ * @{
+ */
+
+#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */
+#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+ * @{
+ */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_PHASE Clock Phase
+ * @{
+ */
+#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */
+/**
+ * @}
+ */
+
+#if defined(USART_PRESC_PRESCALER)
+/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
+ * @{
+ */
+#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
+#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
+#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
+#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
+#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
+#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
+#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
+#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
+#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
+#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
+#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
+#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
+/**
+ * @}
+ */
+
+#endif /* USART_PRESC_PRESCALER */
+/** @defgroup USART_LL_EC_STOPBITS Stop Bits
+ * @{
+ */
+#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */
+#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */
+#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
+ * @{
+ */
+#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+ * @{
+ */
+#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
+#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+ * @{
+ */
+#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
+#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
+ * @{
+ */
+#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
+#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_BITORDER Bit Order
+ * @{
+ */
+#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */
+#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
+ * @{
+ */
+#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */
+#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
+#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */
+#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
+ * @{
+ */
+#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
+#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+ * @{
+ */
+#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
+ * @{
+ */
+#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
+#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
+#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+ * @{
+ */
+#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+ * @{
+ */
+#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
+ * @{
+ */
+#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
+#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
+ * @{
+ */
+#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
+#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Macros USART Exported Macros
+ * @{
+ */
+
+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in USART register
+ * @param __INSTANCE__ USART Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in USART register
+ * @param __INSTANCE__ USART Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+ * @{
+ */
+
+/**
+ * @brief Compute USARTDIV value according to Peripheral Clock and
+ * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+ * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ @if USART_PRESC_PRESCALER
+ * @param __PRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_USART_PRESCALER_DIV1
+ * @arg @ref LL_USART_PRESCALER_DIV2
+ * @arg @ref LL_USART_PRESCALER_DIV4
+ * @arg @ref LL_USART_PRESCALER_DIV6
+ * @arg @ref LL_USART_PRESCALER_DIV8
+ * @arg @ref LL_USART_PRESCALER_DIV10
+ * @arg @ref LL_USART_PRESCALER_DIV12
+ * @arg @ref LL_USART_PRESCALER_DIV16
+ * @arg @ref LL_USART_PRESCALER_DIV32
+ * @arg @ref LL_USART_PRESCALER_DIV64
+ * @arg @ref LL_USART_PRESCALER_DIV128
+ * @arg @ref LL_USART_PRESCALER_DIV256
+ @endif
+ * @param __BAUDRATE__ Baud rate value to achieve
+ * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+ */
+#if defined(USART_PRESC_PRESCALER)
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+ (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
+ + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+#else
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\
+ + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+#endif /* USART_PRESC_PRESCALER */
+
+/**
+ * @brief Compute USARTDIV value according to Peripheral Clock and
+ * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+ * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ @if USART_PRESC_PRESCALER
+ * @param __PRESCALER__ This parameter can be one of the following values:
+ * @arg @ref LL_USART_PRESCALER_DIV1
+ * @arg @ref LL_USART_PRESCALER_DIV2
+ * @arg @ref LL_USART_PRESCALER_DIV4
+ * @arg @ref LL_USART_PRESCALER_DIV6
+ * @arg @ref LL_USART_PRESCALER_DIV8
+ * @arg @ref LL_USART_PRESCALER_DIV10
+ * @arg @ref LL_USART_PRESCALER_DIV12
+ * @arg @ref LL_USART_PRESCALER_DIV16
+ * @arg @ref LL_USART_PRESCALER_DIV32
+ * @arg @ref LL_USART_PRESCALER_DIV64
+ * @arg @ref LL_USART_PRESCALER_DIV128
+ * @arg @ref LL_USART_PRESCALER_DIV256
+ @endif
+ * @param __BAUDRATE__ Baud rate value to achieve
+ * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+ */
+#if defined(USART_PRESC_PRESCALER)
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+ ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
+ + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+#else
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+#endif /* USART_PRESC_PRESCALER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_LL_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @defgroup USART_LL_EF_Configuration Configuration functions
+ * @{
+ */
+
+/**
+ * @brief USART Enable
+ * @rmtoll CR1 UE LL_USART_Enable
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+ * @brief USART Disable (all USART prescalers and outputs are disabled)
+ * @note When USART is disabled, USART prescalers and outputs are stopped immediately,
+ * and current operations are discarded. The configuration of the USART is kept, but all the status
+ * flags, in the USARTx_ISR are set to their default values.
+ * @rmtoll CR1 UE LL_USART_Disable
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+ * @brief Indicate if USART is enabled
+ * @rmtoll CR1 UE LL_USART_IsEnabled
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+}
+
+#if defined(USART_CR1_FIFOEN)
+/**
+ * @brief FIFO Mode Enable
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 FIFOEN LL_USART_EnableFIFO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+ * @brief FIFO Mode Disable
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 FIFOEN LL_USART_DisableFIFO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+ * @brief Indicate if FIFO Mode is enabled
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure TX FIFO Threshold
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold
+ * @param USARTx USART Instance
+ * @param Threshold This parameter can be one of the following values:
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
+{
+ ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+ * @brief Return TX FIFO Threshold Configuration
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+ * @brief Configure RX FIFO Threshold
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold
+ * @param USARTx USART Instance
+ * @param Threshold This parameter can be one of the following values:
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
+{
+ ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+ * @brief Return RX FIFO Threshold Configuration
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+ */
+__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+ * @brief Configure TX and RX FIFOs Threshold
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n
+ * CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold
+ * @param USARTx USART Instance
+ * @param TXThreshold This parameter can be one of the following values:
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+ * @param RXThreshold This parameter can be one of the following values:
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+ * @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+ * @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+ * @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
+{
+ ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
+ (RXThreshold << USART_CR3_RXFTCFG_Pos));
+}
+
+#endif /* USART_CR1_FIFOEN */
+/**
+ * @brief USART enabled in STOP Mode.
+ * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
+ * USART clock selection is HSI or LSE in RCC.
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 UESM LL_USART_EnableInStopMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+ * @brief USART disabled in STOP Mode.
+ * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 UESM LL_USART_DisableInStopMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+ * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+}
+
+#if defined(USART_CR3_UCESM)
+/**
+ * @brief USART Clock enabled in STOP Mode
+ * @note When this function is called, USART Clock is enabled while in STOP mode
+ * @rmtoll CR3 UCESM LL_USART_EnableClockInStopMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_UCESM);
+}
+
+/**
+ * @brief USART clock disabled in STOP Mode
+ * @note When this function is called, USART Clock is disabled while in STOP mode
+ * @rmtoll CR3 UCESM LL_USART_DisableClockInStopMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM);
+}
+
+/**
+ * @brief Indicate if USART clock is enabled in STOP Mode
+ * @rmtoll CR3 UCESM LL_USART_IsClockEnabledInStopMode
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM));
+}
+
+#endif /* USART_CR3_UCESM */
+/**
+ * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
+ * @rmtoll CR1 RE LL_USART_EnableDirectionRx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+ * @brief Receiver Disable
+ * @rmtoll CR1 RE LL_USART_DisableDirectionRx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+ * @brief Transmitter Enable
+ * @rmtoll CR1 TE LL_USART_EnableDirectionTx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+ * @brief Transmitter Disable
+ * @rmtoll CR1 TE LL_USART_DisableDirectionTx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+ * @brief Configure simultaneously enabled/disabled states
+ * of Transmitter and Receiver
+ * @rmtoll CR1 RE LL_USART_SetTransferDirection\n
+ * CR1 TE LL_USART_SetTransferDirection
+ * @param USARTx USART Instance
+ * @param TransferDirection This parameter can be one of the following values:
+ * @arg @ref LL_USART_DIRECTION_NONE
+ * @arg @ref LL_USART_DIRECTION_RX
+ * @arg @ref LL_USART_DIRECTION_TX
+ * @arg @ref LL_USART_DIRECTION_TX_RX
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
+{
+ ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+ * @brief Return enabled/disabled states of Transmitter and Receiver
+ * @rmtoll CR1 RE LL_USART_GetTransferDirection\n
+ * CR1 TE LL_USART_GetTransferDirection
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_DIRECTION_NONE
+ * @arg @ref LL_USART_DIRECTION_RX
+ * @arg @ref LL_USART_DIRECTION_TX
+ * @arg @ref LL_USART_DIRECTION_TX_RX
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+ * @brief Configure Parity (enabled/disabled and parity mode if enabled).
+ * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
+ * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+ * (9th or 8th bit depending on data width) and parity is checked on the received data.
+ * @rmtoll CR1 PS LL_USART_SetParity\n
+ * CR1 PCE LL_USART_SetParity
+ * @param USARTx USART Instance
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+ * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
+ * @rmtoll CR1 PS LL_USART_GetParity\n
+ * CR1 PCE LL_USART_GetParity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ */
+__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+ * @brief Set Receiver Wake Up method from Mute mode.
+ * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod
+ * @param USARTx USART Instance
+ * @param Method This parameter can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_IDLELINE
+ * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+ * @brief Return Receiver Wake Up method from Mute mode
+ * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_IDLELINE
+ * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ */
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+ * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits)
+ * @rmtoll CR1 M0 LL_USART_SetDataWidth\n
+ * CR1 M1 LL_USART_SetDataWidth
+ * @param USARTx USART Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_7B
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+ * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
+ * @rmtoll CR1 M0 LL_USART_GetDataWidth\n
+ * CR1 M1 LL_USART_GetDataWidth
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_7B
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ */
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+}
+
+/**
+ * @brief Allow switch between Mute Mode and Active mode
+ * @rmtoll CR1 MME LL_USART_EnableMuteMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+ * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
+ * @rmtoll CR1 MME LL_USART_DisableMuteMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+ * @brief Indicate if switch between Mute Mode and Active mode is allowed
+ * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set Oversampling to 8-bit or 16-bit mode
+ * @rmtoll CR1 OVER8 LL_USART_SetOverSampling
+ * @param USARTx USART Instance
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+}
+
+/**
+ * @brief Return Oversampling mode
+ * @rmtoll CR1 OVER8 LL_USART_GetOverSampling
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ */
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+}
+
+/**
+ * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
+ * @param USARTx USART Instance
+ * @param LastBitClockPulse This parameter can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+}
+
+/**
+ * @brief Retrieve Clock pulse of the last data bit output configuration
+ * (Last bit Clock pulse output to the SCLK pin or not)
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ */
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+}
+
+/**
+ * @brief Select the phase of the clock output on the SCLK pin in synchronous mode
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPHA LL_USART_SetClockPhase
+ * @param USARTx USART Instance
+ * @param ClockPhase This parameter can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+}
+
+/**
+ * @brief Return phase of the clock output on the SCLK pin in synchronous mode
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPHA LL_USART_GetClockPhase
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+}
+
+/**
+ * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPOL LL_USART_SetClockPolarity
+ * @param USARTx USART Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+}
+
+/**
+ * @brief Return polarity of the clock output on the SCLK pin in synchronous mode
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPOL LL_USART_GetClockPolarity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+}
+
+/**
+ * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+ * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+ * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
+ * @rmtoll CR2 CPHA LL_USART_ConfigClock\n
+ * CR2 CPOL LL_USART_ConfigClock\n
+ * CR2 LBCL LL_USART_ConfigClock
+ * @param USARTx USART Instance
+ * @param Phase This parameter can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ * @param LBCPOutput This parameter can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
+}
+
+#if defined(USART_PRESC_PRESCALER)
+/**
+ * @brief Configure Clock source prescaler for baudrate generator and oversampling
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll PRESC PRESCALER LL_USART_SetPrescaler
+ * @param USARTx USART Instance
+ * @param PrescalerValue This parameter can be one of the following values:
+ * @arg @ref LL_USART_PRESCALER_DIV1
+ * @arg @ref LL_USART_PRESCALER_DIV2
+ * @arg @ref LL_USART_PRESCALER_DIV4
+ * @arg @ref LL_USART_PRESCALER_DIV6
+ * @arg @ref LL_USART_PRESCALER_DIV8
+ * @arg @ref LL_USART_PRESCALER_DIV10
+ * @arg @ref LL_USART_PRESCALER_DIV12
+ * @arg @ref LL_USART_PRESCALER_DIV16
+ * @arg @ref LL_USART_PRESCALER_DIV32
+ * @arg @ref LL_USART_PRESCALER_DIV64
+ * @arg @ref LL_USART_PRESCALER_DIV128
+ * @arg @ref LL_USART_PRESCALER_DIV256
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+ MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
+}
+
+/**
+ * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll PRESC PRESCALER LL_USART_GetPrescaler
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_PRESCALER_DIV1
+ * @arg @ref LL_USART_PRESCALER_DIV2
+ * @arg @ref LL_USART_PRESCALER_DIV4
+ * @arg @ref LL_USART_PRESCALER_DIV6
+ * @arg @ref LL_USART_PRESCALER_DIV8
+ * @arg @ref LL_USART_PRESCALER_DIV10
+ * @arg @ref LL_USART_PRESCALER_DIV12
+ * @arg @ref LL_USART_PRESCALER_DIV16
+ * @arg @ref LL_USART_PRESCALER_DIV32
+ * @arg @ref LL_USART_PRESCALER_DIV64
+ * @arg @ref LL_USART_PRESCALER_DIV128
+ * @arg @ref LL_USART_PRESCALER_DIV256
+ */
+__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
+}
+
+#endif /* USART_PRESC_PRESCALER */
+/**
+ * @brief Enable Clock output on SCLK pin
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Disable Clock output on SCLK pin
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Indicate if Clock output on SCLK pin is enabled
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the length of the stop bits
+ * @rmtoll CR2 STOP LL_USART_SetStopBitsLength
+ * @param USARTx USART Instance
+ * @param StopBits This parameter can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+ * @brief Retrieve the length of the stop bits
+ * @rmtoll CR2 STOP LL_USART_GetStopBitsLength
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ */
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+ * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Data Width configuration using @ref LL_USART_SetDataWidth() function
+ * - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+ * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+ * @rmtoll CR1 PS LL_USART_ConfigCharacter\n
+ * CR1 PCE LL_USART_ConfigCharacter\n
+ * CR1 M0 LL_USART_ConfigCharacter\n
+ * CR1 M1 LL_USART_ConfigCharacter\n
+ * CR2 STOP LL_USART_ConfigCharacter
+ * @param USARTx USART Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_7B
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ * @param StopBits This parameter can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
+ uint32_t StopBits)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+ MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+ * @brief Configure TX/RX pins swapping setting.
+ * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap
+ * @param USARTx USART Instance
+ * @param SwapConfig This parameter can be one of the following values:
+ * @arg @ref LL_USART_TXRX_STANDARD
+ * @arg @ref LL_USART_TXRX_SWAPPED
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+ * @brief Retrieve TX/RX pins swapping configuration.
+ * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_TXRX_STANDARD
+ * @arg @ref LL_USART_TXRX_SWAPPED
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+ * @brief Configure RX pin active level logic
+ * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel
+ * @param USARTx USART Instance
+ * @param PinInvMethod This parameter can be one of the following values:
+ * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+ * @brief Retrieve RX pin active level logic configuration
+ * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+ * @brief Configure TX pin active level logic
+ * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel
+ * @param USARTx USART Instance
+ * @param PinInvMethod This parameter can be one of the following values:
+ * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+ * @brief Retrieve TX pin active level logic configuration
+ * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+ * @brief Configure Binary data logic.
+ * @note Allow to define how Logical data from the data register are send/received :
+ * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+ * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic
+ * @param USARTx USART Instance
+ * @param DataLogic This parameter can be one of the following values:
+ * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+ * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+ * @brief Retrieve Binary data configuration
+ * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+ * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+ * @brief Configure transfer bit order (either Less or Most Significant Bit First)
+ * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
+ * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+ * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder
+ * @param USARTx USART Instance
+ * @param BitOrder This parameter can be one of the following values:
+ * @arg @ref LL_USART_BITORDER_LSBFIRST
+ * @arg @ref LL_USART_BITORDER_MSBFIRST
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+ * @brief Return transfer bit order (either Less or Most Significant Bit First)
+ * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
+ * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+ * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_BITORDER_LSBFIRST
+ * @arg @ref LL_USART_BITORDER_MSBFIRST
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+ * @brief Enable Auto Baud-Rate Detection
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+ * @brief Disable Auto Baud-Rate Detection
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+ * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set Auto Baud-Rate mode bits
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode
+ * @param USARTx USART Instance
+ * @param AutoBaudRateMode This parameter can be one of the following values:
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
+}
+
+/**
+ * @brief Return Auto Baud-Rate mode
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+ */
+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
+}
+
+/**
+ * @brief Enable Receiver Timeout
+ * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+ * @brief Disable Receiver Timeout
+ * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+ * @brief Indicate if Receiver Timeout feature is enabled
+ * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set Address of the USART node.
+ * @note This is used in multiprocessor communication during Mute mode or Stop mode,
+ * for wake up with address mark detection.
+ * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+ * (b7-b4 should be set to 0)
+ * 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+ * (This is used in multiprocessor communication during Mute mode or Stop mode,
+ * for wake up with 7-bit address mark detection.
+ * The MSB of the character sent by the transmitter should be equal to 1.
+ * It may also be used for character detection during normal reception,
+ * Mute mode inactive (for example, end of block detection in ModBus protocol).
+ * In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+ * value and CMF flag is set on match)
+ * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n
+ * CR2 ADDM7 LL_USART_ConfigNodeAddress
+ * @param USARTx USART Instance
+ * @param AddressLen This parameter can be one of the following values:
+ * @arg @ref LL_USART_ADDRESS_DETECT_4B
+ * @arg @ref LL_USART_ADDRESS_DETECT_7B
+ * @param NodeAddress 4 or 7 bit Address of the USART node.
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+ (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+ * @brief Return 8 bit Address of the USART node as set in ADD field of CR2.
+ * @note If 4-bit Address Detection is selected in ADDM7,
+ * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+ * If 7-bit Address Detection is selected in ADDM7,
+ * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+ * @rmtoll CR2 ADD LL_USART_GetNodeAddress
+ * @param USARTx USART Instance
+ * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+ * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+ * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_ADDRESS_DETECT_4B
+ * @arg @ref LL_USART_ADDRESS_DETECT_7B
+ */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+ * @brief Enable RTS HW Flow Control
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+ * @brief Disable RTS HW Flow Control
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+ * @brief Enable CTS HW Flow Control
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+ * @brief Disable CTS HW Flow Control
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+ * @brief Configure HW Flow Control mode (both CTS and RTS)
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
+ * CR3 CTSE LL_USART_SetHWFlowCtrl
+ * @param USARTx USART Instance
+ * @param HardwareFlowControl This parameter can be one of the following values:
+ * @arg @ref LL_USART_HWCONTROL_NONE
+ * @arg @ref LL_USART_HWCONTROL_RTS
+ * @arg @ref LL_USART_HWCONTROL_CTS
+ * @arg @ref LL_USART_HWCONTROL_RTS_CTS
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+ * @brief Return HW Flow Control configuration (both CTS and RTS)
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
+ * CR3 CTSE LL_USART_GetHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_HWCONTROL_NONE
+ * @arg @ref LL_USART_HWCONTROL_RTS
+ * @arg @ref LL_USART_HWCONTROL_CTS
+ * @arg @ref LL_USART_HWCONTROL_RTS_CTS
+ */
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+ * @brief Enable One bit sampling method
+ * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+ * @brief Disable One bit sampling method
+ * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+ * @brief Indicate if One bit sampling method is enabled
+ * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Overrun detection
+ * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+ * @brief Disable Overrun detection
+ * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+ * @brief Indicate if Overrun detection is enabled
+ * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUS LL_USART_SetWKUPType
+ * @param USARTx USART Instance
+ * @param Type This parameter can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+ * @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+ * @arg @ref LL_USART_WAKEUP_ON_RXNE
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+ * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUS LL_USART_GetWKUPType
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+ * @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+ * @arg @ref LL_USART_WAKEUP_ON_RXNE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+ * @brief Configure USART BRR register for achieving expected Baud Rate value.
+ * @note Compute and set USARTDIV value in BRR Register (full BRR content)
+ * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+ * @note Peripheral clock and Baud rate values provided as function parameters should be valid
+ * (Baud rate value != 0)
+ * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+ * @rmtoll BRR BRR LL_USART_SetBaudRate
+ * @param USARTx USART Instance
+ * @param PeriphClk Peripheral Clock
+ @if USART_PRESC_PRESCALER
+ * @param PrescalerValue This parameter can be one of the following values:
+ * @arg @ref LL_USART_PRESCALER_DIV1
+ * @arg @ref LL_USART_PRESCALER_DIV2
+ * @arg @ref LL_USART_PRESCALER_DIV4
+ * @arg @ref LL_USART_PRESCALER_DIV6
+ * @arg @ref LL_USART_PRESCALER_DIV8
+ * @arg @ref LL_USART_PRESCALER_DIV10
+ * @arg @ref LL_USART_PRESCALER_DIV12
+ * @arg @ref LL_USART_PRESCALER_DIV16
+ * @arg @ref LL_USART_PRESCALER_DIV32
+ * @arg @ref LL_USART_PRESCALER_DIV64
+ * @arg @ref LL_USART_PRESCALER_DIV128
+ * @arg @ref LL_USART_PRESCALER_DIV256
+ @endif
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @param BaudRate Baud Rate
+ * @retval None
+ */
+#if defined(USART_PRESC_PRESCALER)
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+ uint32_t OverSampling,
+ uint32_t BaudRate)
+#else
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
+ uint32_t BaudRate)
+#endif /* USART_PRESC_PRESCALER */
+{
+ uint32_t usartdiv;
+ uint32_t brrtemp;
+
+#if defined(USART_PRESC_PRESCALER)
+ if (PrescalerValue > LL_USART_PRESCALER_DIV256)
+ {
+ /* Do not overstep the size of USART_PRESCALER_TAB */
+ }
+ else if (BaudRate == 0U)
+ {
+ /* Can Not divide per 0 */
+ }
+ else if (OverSampling == LL_USART_OVERSAMPLING_8)
+#else
+ if (OverSampling == LL_USART_OVERSAMPLING_8)
+#endif /* USART_PRESC_PRESCALER */
+ {
+#if defined(USART_PRESC_PRESCALER)
+ usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+#else
+ usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
+#endif /* USART_PRESC_PRESCALER */
+ brrtemp = usartdiv & 0xFFF0U;
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ USARTx->BRR = brrtemp;
+ }
+ else
+ {
+#if defined(USART_PRESC_PRESCALER)
+ USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+#else
+ USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
+#endif /* USART_PRESC_PRESCALER */
+ }
+}
+
+/**
+ * @brief Return current Baud Rate value, according to USARTDIV present in BRR register
+ * (full BRR content), and to used Peripheral Clock and Oversampling mode values
+ * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+ * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+ * @rmtoll BRR BRR LL_USART_GetBaudRate
+ * @param USARTx USART Instance
+ * @param PeriphClk Peripheral Clock
+ @if USART_PRESC_PRESCALER
+ * @param PrescalerValue This parameter can be one of the following values:
+ * @arg @ref LL_USART_PRESCALER_DIV1
+ * @arg @ref LL_USART_PRESCALER_DIV2
+ * @arg @ref LL_USART_PRESCALER_DIV4
+ * @arg @ref LL_USART_PRESCALER_DIV6
+ * @arg @ref LL_USART_PRESCALER_DIV8
+ * @arg @ref LL_USART_PRESCALER_DIV10
+ * @arg @ref LL_USART_PRESCALER_DIV12
+ * @arg @ref LL_USART_PRESCALER_DIV16
+ * @arg @ref LL_USART_PRESCALER_DIV32
+ * @arg @ref LL_USART_PRESCALER_DIV64
+ * @arg @ref LL_USART_PRESCALER_DIV128
+ * @arg @ref LL_USART_PRESCALER_DIV256
+ @endif
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @retval Baud Rate
+ */
+#if defined(USART_PRESC_PRESCALER)
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+ uint32_t OverSampling)
+#else
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
+#endif /* USART_PRESC_PRESCALER */
+{
+ uint32_t usartdiv;
+ uint32_t brrresult = 0x0U;
+#if defined(USART_PRESC_PRESCALER)
+ uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
+#endif /* USART_PRESC_PRESCALER */
+
+ usartdiv = USARTx->BRR;
+
+ if (usartdiv == 0U)
+ {
+ /* Do not perform a division by 0 */
+ }
+ else if (OverSampling == LL_USART_OVERSAMPLING_8)
+ {
+ usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+ if (usartdiv != 0U)
+ {
+#if defined(USART_PRESC_PRESCALER)
+ brrresult = (periphclkpresc * 2U) / usartdiv;
+#else
+ brrresult = (PeriphClk * 2U) / usartdiv;
+#endif /* USART_PRESC_PRESCALER */
+ }
+ }
+ else
+ {
+ if ((usartdiv & 0xFFFFU) != 0U)
+ {
+#if defined(USART_PRESC_PRESCALER)
+ brrresult = periphclkpresc / usartdiv;
+#else
+ brrresult = PeriphClk / usartdiv;
+#endif /* USART_PRESC_PRESCALER */
+ }
+ }
+ return (brrresult);
+}
+
+/**
+ * @brief Set Receiver Time Out Value (expressed in nb of bits duration)
+ * @rmtoll RTOR RTO LL_USART_SetRxTimeout
+ * @param USARTx USART Instance
+ * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
+{
+ MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
+}
+
+/**
+ * @brief Get Receiver Time Out Value (expressed in nb of bits duration)
+ * @rmtoll RTOR RTO LL_USART_GetRxTimeout
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+ */
+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
+}
+
+/**
+ * @brief Set Block Length value in reception
+ * @rmtoll RTOR BLEN LL_USART_SetBlockLength
+ * @param USARTx USART Instance
+ * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
+{
+ MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
+}
+
+/**
+ * @brief Get Block Length value in reception
+ * @rmtoll RTOR BLEN LL_USART_GetBlockLength
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+ * @{
+ */
+
+/**
+ * @brief Enable IrDA mode
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_EnableIrda
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Disable IrDA mode
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_DisableIrda
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Indicate if IrDA mode is enabled
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_IsEnabledIrda
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure IrDA Power Mode (Normal or Low Power)
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
+ * @param USARTx USART Instance
+ * @param PowerMode This parameter can be one of the following values:
+ * @arg @ref LL_USART_IRDA_POWER_NORMAL
+ * @arg @ref LL_USART_IRDA_POWER_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+}
+
+/**
+ * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_IRDA_POWER_NORMAL
+ * @arg @ref LL_USART_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+}
+
+/**
+ * @brief Set Irda prescaler value, used for dividing the USART clock source
+ * to achieve the Irda Low Power frequency (8 bits value)
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
+ * @param USARTx USART Instance
+ * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+ * @brief Return Irda prescaler value, used for dividing the USART clock source
+ * to achieve the Irda Low Power frequency (8 bits value)
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
+ * @param USARTx USART Instance
+ * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
+ * @{
+ */
+
+/**
+ * @brief Enable Smartcard NACK transmission
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+ * @brief Disable Smartcard NACK transmission
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+ * @brief Indicate if Smartcard NACK transmission is enabled
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Smartcard mode
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_EnableSmartcard
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Disable Smartcard mode
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_DisableSmartcard
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Indicate if Smartcard mode is enabled
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
+ * In transmission mode, it specifies the number of automatic retransmission retries, before
+ * generating a transmission error (FE bit set).
+ * In reception mode, it specifies the number or erroneous reception trials, before generating a
+ * reception error (RXNE and PE bits set)
+ * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount
+ * @param USARTx USART Instance
+ * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
+}
+
+/**
+ * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
+ * @param USARTx USART Instance
+ * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
+}
+
+/**
+ * @brief Set Smartcard prescaler value, used for dividing the USART clock
+ * source to provide the SMARTCARD Clock (5 bits value)
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
+ * @param USARTx USART Instance
+ * @param PrescalerValue Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+ * @brief Return Smartcard prescaler value, used for dividing the USART clock
+ * source to provide the SMARTCARD Clock (5 bits value)
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
+ * @param USARTx USART Instance
+ * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+ * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods
+ * (GT[7:0] bits : Guard time value)
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
+ * @param USARTx USART Instance
+ * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+{
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
+}
+
+/**
+ * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods
+ * (GT[7:0] bits : Guard time value)
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
+ * @param USARTx USART Instance
+ * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+ * @{
+ */
+
+/**
+ * @brief Enable Single Wire Half-Duplex mode
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Disable Single Wire Half-Duplex mode
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Indicate if Single Wire Half-Duplex mode is enabled
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USART_CR2_SLVEN)
+/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature
+ * @{
+ */
+/**
+ * @brief Enable SPI Synchronous Slave mode
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * SPI Slave mode feature is supported by the USARTx instance.
+ * @rmtoll CR2 SLVEN LL_USART_EnableSPISlave
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+ * @brief Disable SPI Synchronous Slave mode
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * SPI Slave mode feature is supported by the USARTx instance.
+ * @rmtoll CR2 SLVEN LL_USART_DisableSPISlave
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+ * @brief Indicate if SPI Synchronous Slave mode is enabled
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * SPI Slave mode feature is supported by the USARTx instance.
+ * @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable SPI Slave Selection using NSS input pin
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * SPI Slave mode feature is supported by the USARTx instance.
+ * @note SPI Slave Selection depends on NSS input pin
+ * (The slave is selected when NSS is low and deselected when NSS is high).
+ * @rmtoll CR2 DIS_NSS LL_USART_EnableSPISlaveSelect
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+ * @brief Disable SPI Slave Selection using NSS input pin
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * SPI Slave mode feature is supported by the USARTx instance.
+ * @note SPI Slave will be always selected and NSS input pin will be ignored.
+ * @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+ * @brief Indicate if SPI Slave Selection depends on NSS input pin
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * SPI Slave mode feature is supported by the USARTx instance.
+ * @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+#endif /* USART_CR2_SLVEN */
+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+ * @{
+ */
+
+/**
+ * @brief Set LIN Break Detection Length
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
+ * @param USARTx USART Instance
+ * @param LINBDLength This parameter can be one of the following values:
+ * @arg @ref LL_USART_LINBREAK_DETECT_10B
+ * @arg @ref LL_USART_LINBREAK_DETECT_11B
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+}
+
+/**
+ * @brief Return LIN Break Detection Length
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_LINBREAK_DETECT_10B
+ * @arg @ref LL_USART_LINBREAK_DETECT_11B
+ */
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+}
+
+/**
+ * @brief Enable LIN mode
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_EnableLIN
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Disable LIN mode
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_DisableLIN
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Indicate if LIN mode is enabled
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+ * @{
+ */
+
+/**
+ * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime
+ * @param USARTx USART Instance
+ * @param Time Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+ * @brief Return DEDT (Driver Enable De-Assertion Time)
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime
+ * @param USARTx USART Instance
+ * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+ */
+__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+ * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime
+ * @param USARTx USART Instance
+ * @param Time Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+ * @brief Return DEAT (Driver Enable Assertion Time)
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime
+ * @param USARTx USART Instance
+ * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+ */
+__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+ * @brief Enable Driver Enable (DE) Mode
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEM LL_USART_EnableDEMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+ * @brief Disable Driver Enable (DE) Mode
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEM LL_USART_DisableDEMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+ * @brief Indicate if Driver Enable (DE) Mode is enabled
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Select Driver Enable Polarity
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity
+ * @param USARTx USART Instance
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_DE_POLARITY_HIGH
+ * @arg @ref LL_USART_DE_POLARITY_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+ * @brief Return Driver Enable Polarity
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_DE_POLARITY_HIGH
+ * @arg @ref LL_USART_DE_POLARITY_LOW
+ */
+__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+ * @{
+ */
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+ * @note In UART mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * @note Other remaining configurations items related to Asynchronous Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n
+ * CR2 CLKEN LL_USART_ConfigAsyncMode\n
+ * CR3 SCEN LL_USART_ConfigAsyncMode\n
+ * CR3 IREN LL_USART_ConfigAsyncMode\n
+ * CR3 HDSEL LL_USART_ConfigAsyncMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+{
+ /* In Asynchronous mode, the following bits must be kept cleared:
+ - LINEN, CLKEN bits in the USART_CR2 register,
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Synchronous Mode
+ * @note In Synchronous mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also sets the USART in Synchronous mode.
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+ * @note Other remaining configurations items related to Synchronous Mode
+ * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n
+ * CR2 CLKEN LL_USART_ConfigSyncMode\n
+ * CR3 SCEN LL_USART_ConfigSyncMode\n
+ * CR3 IREN LL_USART_ConfigSyncMode\n
+ * CR3 HDSEL LL_USART_ConfigSyncMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+{
+ /* In Synchronous mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register,
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+ /* set the UART/USART in Synchronous mode */
+ SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in LIN Mode
+ * @note In LIN mode, the following bits must be kept cleared:
+ * - STOP and CLKEN bits in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also set the UART/USART in LIN mode.
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+ * @note Other remaining configurations items related to LIN Mode
+ * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n
+ * CR2 STOP LL_USART_ConfigLINMode\n
+ * CR2 LINEN LL_USART_ConfigLINMode\n
+ * CR3 IREN LL_USART_ConfigLINMode\n
+ * CR3 SCEN LL_USART_ConfigLINMode\n
+ * CR3 HDSEL LL_USART_ConfigLINMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+{
+ /* In LIN mode, the following bits must be kept cleared:
+ - STOP and CLKEN bits in the USART_CR2 register,
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+ /* Set the UART/USART in LIN mode */
+ SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode
+ * @note In Half Duplex mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * This function also sets the UART/USART in Half Duplex mode.
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+ * @note Other remaining configurations items related to Half Duplex Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n
+ * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n
+ * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n
+ * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n
+ * CR3 IREN LL_USART_ConfigHalfDuplexMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+{
+ /* In Half Duplex mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+ /* set the UART/USART in Half Duplex mode */
+ SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Smartcard Mode
+ * @note In Smartcard mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also configures Stop bits to 1.5 bits and
+ * sets the USART in Smartcard mode (SCEN bit).
+ * Clock Output is also enabled (CLKEN).
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+ * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+ * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+ * @note Other remaining configurations items related to Smartcard Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n
+ * CR2 STOP LL_USART_ConfigSmartcardMode\n
+ * CR2 CLKEN LL_USART_ConfigSmartcardMode\n
+ * CR3 HDSEL LL_USART_ConfigSmartcardMode\n
+ * CR3 SCEN LL_USART_ConfigSmartcardMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+{
+ /* In Smartcard mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register,
+ - IREN and HDSEL bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+ /* Configure Stop bits to 1.5 bits */
+ /* Synchronous mode is activated by default */
+ SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+ /* set the UART/USART in Smartcard mode */
+ SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Irda Mode
+ * @note In IRDA mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - STOP and CLKEN bits in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also sets the UART/USART in IRDA mode (IREN bit).
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+ * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+ * @note Other remaining configurations items related to Irda Mode
+ * (as Baud Rate, Word length, Power mode, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n
+ * CR2 CLKEN LL_USART_ConfigIrdaMode\n
+ * CR2 STOP LL_USART_ConfigIrdaMode\n
+ * CR3 SCEN LL_USART_ConfigIrdaMode\n
+ * CR3 HDSEL LL_USART_ConfigIrdaMode\n
+ * CR3 IREN LL_USART_ConfigIrdaMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+{
+ /* In IRDA mode, the following bits must be kept cleared:
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+ - SCEN and HDSEL bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+ /* set the UART/USART in IRDA mode */
+ SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Multi processor Mode
+ * (several USARTs connected in a network, one of the USARTs can be the master,
+ * its TX output connected to the RX inputs of the other slaves USARTs).
+ * @note In MultiProcessor mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * @note Other remaining configurations items related to Multi processor Mode
+ * (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n
+ * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n
+ * CR3 SCEN LL_USART_ConfigMultiProcessMode\n
+ * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n
+ * CR3 IREN LL_USART_ConfigMultiProcessMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+{
+ /* In Multi Processor mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+ */
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check if the USART Parity Error Flag is set or not
+ * @rmtoll ISR PE LL_USART_IsActiveFlag_PE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Framing Error Flag is set or not
+ * @rmtoll ISR FE LL_USART_IsActiveFlag_FE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Noise error detected Flag is set or not
+ * @rmtoll ISR NE LL_USART_IsActiveFlag_NE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART OverRun Error Flag is set or not
+ * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART IDLE line detected Flag is set or not
+ * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
+}
+
+#if defined(USART_CR1_FIFOEN)
+/* Legacy define */
+#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE
+
+/**
+ * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
+}
+
+#else
+/**
+ * @brief Check if the USART Read Data Register Not Empty Flag is set or not
+ * @rmtoll ISR RXNE LL_USART_IsActiveFlag_RXNE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL);
+}
+
+#endif /* USART_CR1_FIFOEN */
+/**
+ * @brief Check if the USART Transmission Complete Flag is set or not
+ * @rmtoll ISR TC LL_USART_IsActiveFlag_TC
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+}
+
+#if defined(USART_CR1_FIFOEN)
+/* Legacy define */
+#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF
+
+/**
+ * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
+}
+
+#else
+/**
+ * @brief Check if the USART Transmit Data Register Empty Flag is set or not
+ * @rmtoll ISR TXE LL_USART_IsActiveFlag_TXE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL);
+}
+
+#endif /* USART_CR1_FIFOEN */
+/**
+ * @brief Check if the USART LIN Break Detection Flag is set or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART CTS interrupt Flag is set or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART CTS Flag is set or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Receiver Time Out Flag is set or not
+ * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART End Of Block Flag is set or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
+}
+
+#if defined(USART_CR2_SLVEN)
+/**
+ * @brief Check if the SPI Slave Underrun error flag is set or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * SPI Slave mode feature is supported by the USARTx instance.
+ * @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
+}
+
+#endif /* USART_CR2_SLVEN */
+/**
+ * @brief Check if the USART Auto-Baud Rate Error Flag is set or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Auto-Baud Rate Flag is set or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Busy Flag is set or not
+ * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Character Match Flag is set or not
+ * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Send Break Flag is set or not
+ * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not
+ * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Wake Up from stop mode Flag is set or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not
+ * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Receive Enable Acknowledge Flag is set or not
+ * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
+}
+
+#if defined(USART_CR1_FIFOEN)
+/**
+ * @brief Check if the USART TX FIFO Empty Flag is set or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART RX FIFO Full Flag is set or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
+}
+
+#endif /* USART_CR1_FIFOEN */
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+ * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
+ * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
+}
+
+#endif /* USART_TCBGT_SUPPORT */
+#if defined(USART_CR1_FIFOEN)
+/**
+ * @brief Check if the USART TX FIFO Threshold Flag is set or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART RX FIFO Threshold Flag is set or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
+}
+
+#endif /* USART_CR1_FIFOEN */
+/**
+ * @brief Clear Parity Error Flag
+ * @rmtoll ICR PECF LL_USART_ClearFlag_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+ * @brief Clear Framing Error Flag
+ * @rmtoll ICR FECF LL_USART_ClearFlag_FE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+ * @brief Clear Noise Error detected Flag
+ * @rmtoll ICR NECF LL_USART_ClearFlag_NE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_NECF);
+}
+
+/**
+ * @brief Clear OverRun Error Flag
+ * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+ * @brief Clear IDLE line detected Flag
+ * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
+}
+
+#if defined(USART_CR1_FIFOEN)
+/**
+ * @brief Clear TX FIFO Empty Flag
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
+}
+
+#endif /* USART_CR1_FIFOEN */
+/**
+ * @brief Clear Transmission Complete Flag
+ * @rmtoll ICR TCCF LL_USART_ClearFlag_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
+}
+
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+ * @brief Clear Smartcard Transmission Complete Before Guard Time Flag
+ * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
+}
+#endif /* USART_TCBGT_SUPPORT */
+
+/**
+ * @brief Clear LIN Break Detection Flag
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
+}
+
+/**
+ * @brief Clear CTS Interrupt Flag
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+ * @brief Clear Receiver Time Out Flag
+ * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
+}
+
+/**
+ * @brief Clear End Of Block Flag
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
+}
+
+#if defined(USART_CR2_SLVEN)
+/**
+ * @brief Clear SPI Slave Underrun Flag
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * SPI Slave mode feature is supported by the USARTx instance.
+ * @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
+}
+
+#endif /* USART_CR2_SLVEN */
+/**
+ * @brief Clear Character Match Flag
+ * @rmtoll ICR CMCF LL_USART_ClearFlag_CM
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+ * @brief Clear Wake Up from stop mode Flag
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable IDLE Interrupt
+ * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+#if defined(USART_CR1_FIFOEN)
+/* Legacy define */
+#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE
+
+/**
+ * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+#else
+/**
+ * @brief Enable RX Not Empty Interrupt
+ * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+#endif /* USART_CR1_FIFOEN */
+/**
+ * @brief Enable Transmission Complete Interrupt
+ * @rmtoll CR1 TCIE LL_USART_EnableIT_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+#if defined(USART_CR1_FIFOEN)
+/* Legacy define */
+#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF
+
+/**
+ * @brief Enable TX Empty and TX FIFO Not Full Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+#else
+/**
+ * @brief Enable TX Empty Interrupt
+ * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+#endif /* USART_CR1_FIFOEN */
+/**
+ * @brief Enable Parity Error Interrupt
+ * @rmtoll CR1 PEIE LL_USART_EnableIT_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+ * @brief Enable Character Match Interrupt
+ * @rmtoll CR1 CMIE LL_USART_EnableIT_CM
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+ * @brief Enable Receiver Timeout Interrupt
+ * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+ * @brief Enable End Of Block Interrupt
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+#if defined(USART_CR1_FIFOEN)
+/**
+ * @brief Enable TX FIFO Empty Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+ * @brief Enable RX FIFO Full Interrupt
+ * @rmtoll CR1 RXFFIE LL_USART_EnableIT_RXFF
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+#endif /* USART_CR1_FIFOEN */
+/**
+ * @brief Enable LIN Break Detection Interrupt
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+ * @brief Enable Error Interrupt
+ * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+ * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+ * 0: Interrupt is inhibited
+ * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+ * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+ * @brief Enable CTS Interrupt
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+ * @brief Enable Wake Up from Stop Mode Interrupt
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+#if defined(USART_CR1_FIFOEN)
+/**
+ * @brief Enable TX FIFO Threshold Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+#endif /* USART_CR1_FIFOEN */
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+ * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+#endif /* USART_TCBGT_SUPPORT */
+
+#if defined(USART_CR1_FIFOEN)
+/**
+ * @brief Enable RX FIFO Threshold Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+#endif /* USART_CR1_FIFOEN */
+/**
+ * @brief Disable IDLE Interrupt
+ * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+#if defined(USART_CR1_FIFOEN)
+/* Legacy define */
+#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE
+
+/**
+ * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+#else
+/**
+ * @brief Disable RX Not Empty Interrupt
+ * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+#endif /* USART_CR1_FIFOEN */
+/**
+ * @brief Disable Transmission Complete Interrupt
+ * @rmtoll CR1 TCIE LL_USART_DisableIT_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+#if defined(USART_CR1_FIFOEN)
+/* Legacy define */
+#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF
+
+/**
+ * @brief Disable TX Empty and TX FIFO Not Full Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+#else
+/**
+ * @brief Disable TX Empty Interrupt
+ * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+#endif /* USART_CR1_FIFOEN */
+/**
+ * @brief Disable Parity Error Interrupt
+ * @rmtoll CR1 PEIE LL_USART_DisableIT_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+ * @brief Disable Character Match Interrupt
+ * @rmtoll CR1 CMIE LL_USART_DisableIT_CM
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+ * @brief Disable Receiver Timeout Interrupt
+ * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+ * @brief Disable End Of Block Interrupt
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+#if defined(USART_CR1_FIFOEN)
+/**
+ * @brief Disable TX FIFO Empty Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+ * @brief Disable RX FIFO Full Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+#endif /* USART_CR1_FIFOEN */
+/**
+ * @brief Disable LIN Break Detection Interrupt
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+ * @brief Disable Error Interrupt
+ * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+ * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+ * 0: Interrupt is inhibited
+ * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+ * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+ * @brief Disable CTS Interrupt
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+ * @brief Disable Wake Up from Stop Mode Interrupt
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+#if defined(USART_CR1_FIFOEN)
+/**
+ * @brief Disable TX FIFO Threshold Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+#endif /* USART_CR1_FIFOEN */
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+ * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+#endif /* USART_TCBGT_SUPPORT */
+
+#if defined(USART_CR1_FIFOEN)
+/**
+ * @brief Disable RX FIFO Threshold Interrupt
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+#endif /* USART_CR1_FIFOEN */
+/**
+ * @brief Check if the USART IDLE Interrupt source is enabled or disabled.
+ * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
+}
+
+#if defined(USART_CR1_FIFOEN)
+/* Legacy define */
+#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE
+
+/**
+ * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
+}
+
+#else
+/**
+ * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled.
+ * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1U : 0U);
+}
+
+#endif /* USART_CR1_FIFOEN */
+/**
+ * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled.
+ * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+#if defined(USART_CR1_FIFOEN)
+/* Legacy define */
+#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF
+
+/**
+ * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
+}
+
+#else
+/**
+ * @brief Check if the USART TX Empty Interrupt is enabled or disabled.
+ * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1U : 0U);
+}
+
+#endif /* USART_CR1_FIFOEN */
+/**
+ * @brief Check if the USART Parity Error Interrupt is enabled or disabled.
+ * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Character Match Interrupt is enabled or disabled.
+ * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled.
+ * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART End Of Block Interrupt is enabled or disabled.
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
+}
+
+#if defined(USART_CR1_FIFOEN)
+/**
+ * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
+}
+
+#endif /* USART_CR1_FIFOEN */
+/**
+ * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Error Interrupt is enabled or disabled.
+ * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART CTS Interrupt is enabled or disabled.
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
+}
+
+#if defined(USART_CR1_FIFOEN)
+/**
+ * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
+}
+
+#endif /* USART_CR1_FIFOEN */
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+ * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
+}
+#endif /* USART_TCBGT_SUPPORT */
+
+#if defined(USART_CR1_FIFOEN)
+/**
+ * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
+}
+
+#endif /* USART_CR1_FIFOEN */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_DMA_Management DMA_Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Mode for reception
+ * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+ * @brief Disable DMA Mode for reception
+ * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+ * @brief Check if DMA Mode is enabled for reception
+ * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable DMA Mode for transmission
+ * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+{
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+ * @brief Disable DMA Mode for transmission
+ * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+{
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+ * @brief Check if DMA Mode is enabled for transmission
+ * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable DMA Disabling on Reception Error
+ * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+ * @brief Disable DMA Disabling on Reception Error
+ * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+ * @brief Indicate if DMA Disabling on Reception Error is disabled
+ * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n
+ * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr
+ * @param USARTx USART Instance
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
+ * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
+{
+ uint32_t data_reg_addr;
+
+ if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
+ {
+ /* return address of TDR register */
+ data_reg_addr = (uint32_t) &(USARTx->TDR);
+ }
+ else
+ {
+ /* return address of RDR register */
+ data_reg_addr = (uint32_t) &(USARTx->RDR);
+ }
+
+ return data_reg_addr;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Read Receiver Data register (Receive Data value, 8 bits)
+ * @rmtoll RDR RDR LL_USART_ReceiveData8
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
+{
+ return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
+}
+
+/**
+ * @brief Read Receiver Data register (Receive Data value, 9 bits)
+ * @rmtoll RDR RDR LL_USART_ReceiveData9
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+ */
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
+{
+ return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+ * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
+ * @rmtoll TDR TDR LL_USART_TransmitData8
+ * @param USARTx USART Instance
+ * @param Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
+{
+ USARTx->TDR = Value;
+}
+
+/**
+ * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
+ * @rmtoll TDR TDR LL_USART_TransmitData9
+ * @param USARTx USART Instance
+ * @param Value between Min_Data=0x00 and Max_Data=0x1FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
+{
+ USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Execution Execution
+ * @{
+ */
+
+/**
+ * @brief Request an Automatic Baud Rate measurement on next received data frame
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
+}
+
+/**
+ * @brief Request Break sending
+ * @rmtoll RQR SBKRQ LL_USART_RequestBreakSending
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
+}
+
+/**
+ * @brief Put USART in mute mode and set the RWU flag
+ * @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
+}
+
+/**
+ @if USART_CR1_FIFOEN
+ * @brief Request a Receive Data and FIFO flush
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @note Allows to discard the received data without reading them, and avoid an overrun
+ * condition.
+ @else
+ * @brief Request a Receive Data flush
+ @endif
+ * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
+}
+
+/**
+ @if USART_CR1_FIFOEN
+ * @brief Request a Transmit data and FIFO flush
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ @else
+ * @brief Request a Transmit data flush
+ @endif
+ * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L4xx_LL_USART_H */
+
diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h
new file mode 100644
index 0000000..d465c0d
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h
@@ -0,0 +1,329 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_utils.h
+ * @author MCD Application Team
+ * @brief Header file of UTILS LL module.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL UTILS driver contains a set of generic APIs that can be
+ used by user:
+ (+) Device electronic signature
+ (+) Timing functions
+ (+) PLL configuration functions
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L4xx_LL_UTILS_H
+#define STM32L4xx_LL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup UTILS_LL UTILS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
+ * @{
+ */
+
+/* Max delay can be used in LL_mDelay */
+#define LL_MAX_DELAY 0xFFFFFFFFU
+
+/**
+ * @brief Unique device ID register base address
+ */
+#define UID_BASE_ADDRESS UID_BASE
+
+/**
+ * @brief Flash size data register base address
+ */
+#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
+
+/**
+ * @brief Package data register base address
+ */
+#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
+ * @{
+ */
+/**
+ * @brief UTILS PLL structure definition
+ */
+typedef struct
+{
+ uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
+ This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+ uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
+ This parameter must be a number between Min_Data = 8 and Max_Data = 86
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+ uint32_t PLLR; /*!< Division for the main system clock.
+ This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+} LL_UTILS_PLLInitTypeDef;
+
+/**
+ * @brief UTILS System, AHB and APB buses clock configuration structure definition
+ */
+typedef struct
+{
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+ This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAHBPrescaler(). */
+
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAPB1Prescaler(). */
+
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAPB2Prescaler(). */
+
+} LL_UTILS_ClkInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
+ * @{
+ */
+
+/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
+ * @{
+ */
+#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
+#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
+ * @{
+ */
+#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */
+#define LL_UTILS_PACKAGETYPE_WLCSP64 0x00000001U /*!< WLCSP64 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */
+#define LL_UTILS_PACKAGETYPE_BGA132 0x00000003U /*!< BGA132 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP144_CSP72 0x00000004U /*!< LQFP144, WLCSP81 or WLCSP72 package type */
+#define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000008U /*!< UFQFPN32 package type */
+#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x0000000AU /*!< UFQFPN48 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP48 0x0000000BU /*!< LQFP48 package type */
+#define LL_UTILS_PACKAGETYPE_WLCSP49 0x0000000CU /*!< WLCSP49 package type */
+#define LL_UTILS_PACKAGETYPE_UFBGA64 0x0000000DU /*!< UFBGA64 package type */
+#define LL_UTILS_PACKAGETYPE_UFBGA100 0x0000000EU /*!< UFBGA100 package type */
+#define LL_UTILS_PACKAGETYPE_UFBGA169_CSP115 0x00000010U /*!< UFBGA169 or WLCSP115 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP100_DSI 0x00000012U /*!< LQFP100 with DSI package type */
+#define LL_UTILS_PACKAGETYPE_WLCSP144_DSI 0x00000013U /*!< WLCSP144 with DSI package type */
+#define LL_UTILS_PACKAGETYPE_UFBGA144_DSI 0x00000013U /*!< UFBGA144 with DSI package type */
+#define LL_UTILS_PACKAGETYPE_UFBGA169_DSI 0x00000014U /*!< UFBGA169 with DSI package type */
+#define LL_UTILS_PACKAGETYPE_LQFP144_DSI 0x00000015U /*!< LQFP144 with DSI package type */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
+ * @{
+ */
+
+/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
+ * @{
+ */
+
+/**
+ * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
+}
+
+/**
+ * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
+}
+
+/**
+ * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
+}
+
+/**
+ * @brief Get Flash memory size
+ * @note This bitfield indicates the size of the device Flash memory expressed in
+ * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
+ * @retval FLASH_SIZE[15:0]: Flash memory size
+ */
+__STATIC_INLINE uint32_t LL_GetFlashSize(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU);
+}
+
+/**
+ * @brief Get Package type
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100 (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_BGA132 (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_CSP72 (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32 (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48 (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48 (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP49 (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64 (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100 (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169 (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_DSI (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP144_DSI (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_DSI (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_DSI (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_DSI (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_GetPackageType(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_LL_EF_DELAY DELAY
+ * @{
+ */
+
+/**
+ * @brief This function configures the Cortex-M SysTick source of the time base.
+ * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+ * @note When a RTOS is used, it is recommended to avoid changing the SysTick
+ * configuration by calling this function, for a delay use rather osDelay RTOS service.
+ * @param Ticks Number of ticks
+ * @retval None
+ */
+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
+{
+ /* Configure the SysTick to have interrupt in 1ms time base */
+ SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
+}
+
+void LL_Init1msTick(uint32_t HCLKFrequency);
+void LL_mDelay(uint32_t Delay);
+
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_EF_SYSTEM SYSTEM
+ * @{
+ */
+
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
+ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
+ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L4xx_LL_UTILS_H */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c
deleted file mode 100644
index 9b5cb1d..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c
+++ /dev/null
@@ -1,764 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal.c
- * @author MCD Application Team
- * @brief HAL module driver.
- * This is the common part of the HAL initialization
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The common HAL driver contains a set of generic and common APIs that can be
- used by the PPP peripheral drivers and the user to start using the HAL.
- [..]
- The HAL contains two APIs' categories:
- (+) Common HAL APIs
- (+) Services HAL APIs
-
- @endverbatim
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup HAL HAL
- * @brief HAL module driver
- * @{
- */
-
-#ifdef HAL_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/**
- * @brief STM32L4xx HAL Driver version number
- */
-#define STM32L4XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
-#define STM32L4XX_HAL_VERSION_SUB1 (0x0DU) /*!< [23:16] sub1 version */
-#define STM32L4XX_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
-#define STM32L4XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
-#define STM32L4XX_HAL_VERSION ((STM32L4XX_HAL_VERSION_MAIN << 24U)\
- |(STM32L4XX_HAL_VERSION_SUB1 << 16U)\
- |(STM32L4XX_HAL_VERSION_SUB2 << 8U)\
- |(STM32L4XX_HAL_VERSION_RC))
-
-#if defined(VREFBUF)
-#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms (to be confirmed) */
-#endif /* VREFBUF */
-
-/* ------------ SYSCFG registers bit address in the alias region ------------ */
-#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
-/* --- MEMRMP Register ---*/
-/* Alias word address of FB_MODE bit */
-#define MEMRMP_OFFSET SYSCFG_OFFSET
-#define FB_MODE_BitNumber 8U
-#define FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (FB_MODE_BitNumber * 4U))
-
-/* --- SCSR Register ---*/
-/* Alias word address of SRAM2ER bit */
-#define SCSR_OFFSET (SYSCFG_OFFSET + 0x18U)
-#define BRER_BitNumber 0U
-#define SCSR_SRAM2ER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32U) + (BRER_BitNumber * 4U))
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported variables --------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Variables HAL Exported Variables
- * @{
- */
-__IO uint32_t uwTick;
-uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid priority */
-HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Functions HAL Exported Functions
- * @{
- */
-
-/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the Flash interface, the NVIC allocation and initial time base
- clock configuration.
- (+) De-initialize common part of the HAL.
- (+) Configure the time base source to have 1ms time base with a dedicated
- Tick interrupt priority.
- (++) SysTick timer is used by default as source of time base, but user
- can eventually implement his proper time base source (a general purpose
- timer for example or other time source), keeping in mind that Time base
- duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
- handled in milliseconds basis.
- (++) Time base configuration function (HAL_InitTick ()) is called automatically
- at the beginning of the program after reset by HAL_Init() or at any time
- when clock is configured, by HAL_RCC_ClockConfig().
- (++) Source of time base is configured to generate interrupts at regular
- time intervals. Care must be taken if HAL_Delay() is called from a
- peripheral ISR process, the Tick interrupt line must have higher priority
- (numerically lower) than the peripheral interrupt. Otherwise the caller
- ISR process will be blocked.
- (++) functions affecting time base configurations are declared as __weak
- to make override possible in case of other implementations in user file.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure the Flash prefetch, the Instruction and Data caches,
- * the time base source, NVIC and any required global low level hardware
- * by calling the HAL_MspInit() callback function to be optionally defined in user file
- * stm32l4xx_hal_msp.c.
- *
- * @note HAL_Init() function is called at the beginning of program after reset and before
- * the clock configuration.
- *
- * @note In the default implementation the System Timer (Systick) is used as source of time base.
- * The Systick configuration is based on MSI clock, as MSI is the clock
- * used after a system Reset and the NVIC configuration is set to Priority group 4.
- * Once done, time base tick starts incrementing: the tick variable counter is incremented
- * each 1ms in the SysTick_Handler() interrupt handler.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_Init(void)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Configure Flash prefetch, Instruction cache, Data cache */
- /* Default configuration at reset is: */
- /* - Prefetch disabled */
- /* - Instruction cache enabled */
- /* - Data cache enabled */
-#if (INSTRUCTION_CACHE_ENABLE == 0)
- __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
-#endif /* INSTRUCTION_CACHE_ENABLE */
-
-#if (DATA_CACHE_ENABLE == 0)
- __HAL_FLASH_DATA_CACHE_DISABLE();
-#endif /* DATA_CACHE_ENABLE */
-
-#if (PREFETCH_ENABLE != 0)
- __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
-#endif /* PREFETCH_ENABLE */
-
- /* Set Interrupt Group Priority */
- HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
-
- /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
- if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Init the low level hardware */
- HAL_MspInit();
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief De-initialize common part of the HAL and stop the source of time base.
- * @note This function is optional.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DeInit(void)
-{
- /* Reset of all peripherals */
- __HAL_RCC_APB1_FORCE_RESET();
- __HAL_RCC_APB1_RELEASE_RESET();
-
- __HAL_RCC_APB2_FORCE_RESET();
- __HAL_RCC_APB2_RELEASE_RESET();
-
- __HAL_RCC_AHB1_FORCE_RESET();
- __HAL_RCC_AHB1_RELEASE_RESET();
-
- __HAL_RCC_AHB2_FORCE_RESET();
- __HAL_RCC_AHB2_RELEASE_RESET();
-
- __HAL_RCC_AHB3_FORCE_RESET();
- __HAL_RCC_AHB3_RELEASE_RESET();
-
- /* De-Init the low level hardware */
- HAL_MspDeInit();
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the MSP.
- * @retval None
- */
-__weak void HAL_MspInit(void)
-{
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the MSP.
- * @retval None
- */
-__weak void HAL_MspDeInit(void)
-{
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief This function configures the source of the time base:
- * The time source is configured to have 1ms time base with a dedicated
- * Tick interrupt priority.
- * @note This function is called automatically at the beginning of program after
- * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
- * @note In the default implementation, SysTick timer is the source of time base.
- * It is used to generate interrupts at regular time intervals.
- * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
- * The SysTick interrupt must have higher priority (numerically lower)
- * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
- * The function is declared as __weak to be overwritten in case of other
- * implementation in user file.
- * @param TickPriority Tick interrupt priority.
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
- if ((uint32_t)uwTickFreq != 0U)
- {
- /*Configure the SysTick to have interrupt in 1ms time basis*/
- if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
- {
- /* Configure the SysTick IRQ priority */
- if (TickPriority < (1UL << __NVIC_PRIO_BITS))
- {
- HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
- uwTickPrio = TickPriority;
- }
- else
- {
- status = HAL_ERROR;
- }
- }
- else
- {
- status = HAL_ERROR;
- }
- }
- else
- {
- status = HAL_ERROR;
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
- * @brief HAL Control functions
- *
-@verbatim
- ===============================================================================
- ##### HAL Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Provide a tick value in millisecond
- (+) Provide a blocking delay in millisecond
- (+) Suspend the time base source interrupt
- (+) Resume the time base source interrupt
- (+) Get the HAL API driver version
- (+) Get the device identifier
- (+) Get the device revision identifier
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function is called to increment a global variable "uwTick"
- * used as application time base.
- * @note In the default implementation, this variable is incremented each 1ms
- * in SysTick ISR.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_IncTick(void)
-{
- uwTick += (uint32_t)uwTickFreq;
-}
-
-/**
- * @brief Provide a tick value in millisecond.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval tick value
- */
-__weak uint32_t HAL_GetTick(void)
-{
- return uwTick;
-}
-
-/**
- * @brief This function returns a tick priority.
- * @retval tick priority
- */
-uint32_t HAL_GetTickPrio(void)
-{
- return uwTickPrio;
-}
-
-/**
- * @brief Set new tick Freq.
- * @param Freq tick frequency
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
-{
- HAL_StatusTypeDef status = HAL_OK;
- HAL_TickFreqTypeDef prevTickFreq;
-
- if (uwTickFreq != Freq)
- {
- /* Back up uwTickFreq frequency */
- prevTickFreq = uwTickFreq;
-
- /* Update uwTickFreq global variable used by HAL_InitTick() */
- uwTickFreq = Freq;
-
- /* Apply the new tick Freq */
- status = HAL_InitTick(uwTickPrio);
- if (status != HAL_OK)
- {
- /* Restore previous tick frequency */
- uwTickFreq = prevTickFreq;
- }
- }
-
- return status;
-}
-
-/**
- * @brief Return tick frequency.
- * @retval tick period in Hz
- */
-HAL_TickFreqTypeDef HAL_GetTickFreq(void)
-{
- return uwTickFreq;
-}
-
-/**
- * @brief This function provides minimum delay (in milliseconds) based
- * on variable incremented.
- * @note In the default implementation , SysTick timer is the source of time base.
- * It is used to generate interrupts at regular time intervals where uwTick
- * is incremented.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @param Delay specifies the delay time length, in milliseconds.
- * @retval None
- */
-__weak void HAL_Delay(uint32_t Delay)
-{
- uint32_t tickstart = HAL_GetTick();
- uint32_t wait = Delay;
-
- /* Add a period to guaranty minimum wait */
- if (wait < HAL_MAX_DELAY)
- {
- wait += (uint32_t)uwTickFreq;
- }
-
- while ((HAL_GetTick() - tickstart) < wait)
- {
- }
-}
-
-/**
- * @brief Suspend Tick increment.
- * @note In the default implementation , SysTick timer is the source of time base. It is
- * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
- * is called, the SysTick interrupt will be disabled and so Tick increment
- * is suspended.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_SuspendTick(void)
-{
- /* Disable SysTick Interrupt */
- SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
-}
-
-/**
- * @brief Resume Tick increment.
- * @note In the default implementation , SysTick timer is the source of time base. It is
- * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
- * is called, the SysTick interrupt will be enabled and so Tick increment
- * is resumed.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_ResumeTick(void)
-{
- /* Enable SysTick Interrupt */
- SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
-}
-
-/**
- * @brief Return the HAL revision.
- * @retval version : 0xXYZR (8bits for each decimal, R for RC)
- */
-uint32_t HAL_GetHalVersion(void)
-{
- return STM32L4XX_HAL_VERSION;
-}
-
-/**
- * @brief Return the device revision identifier.
- * @retval Device revision identifier
- */
-uint32_t HAL_GetREVID(void)
-{
- return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16);
-}
-
-/**
- * @brief Return the device identifier.
- * @retval Device identifier
- */
-uint32_t HAL_GetDEVID(void)
-{
- return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
-}
-
-/**
- * @brief Return the first word of the unique device identifier (UID based on 96 bits)
- * @retval Device identifier
- */
-uint32_t HAL_GetUIDw0(void)
-{
- return(READ_REG(*((uint32_t *)UID_BASE)));
-}
-
-/**
- * @brief Return the second word of the unique device identifier (UID based on 96 bits)
- * @retval Device identifier
- */
-uint32_t HAL_GetUIDw1(void)
-{
- return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
-}
-
-/**
- * @brief Return the third word of the unique device identifier (UID based on 96 bits)
- * @retval Device identifier
- */
-uint32_t HAL_GetUIDw2(void)
-{
- return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
-}
-
-/**
- * @}
- */
-
-/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
- * @brief HAL Debug functions
- *
-@verbatim
- ===============================================================================
- ##### HAL Debug functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Enable/Disable Debug module during SLEEP mode
- (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes
- (+) Enable/Disable Debug module during STANDBY mode
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enable the Debug Module during SLEEP mode.
- * @retval None
- */
-void HAL_DBGMCU_EnableDBGSleepMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Disable the Debug Module during SLEEP mode.
- * @retval None
- */
-void HAL_DBGMCU_DisableDBGSleepMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Enable the Debug Module during STOP0/STOP1/STOP2 modes.
- * @retval None
- */
-void HAL_DBGMCU_EnableDBGStopMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Disable the Debug Module during STOP0/STOP1/STOP2 modes.
- * @retval None
- */
-void HAL_DBGMCU_DisableDBGStopMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Enable the Debug Module during STANDBY mode.
- * @retval None
- */
-void HAL_DBGMCU_EnableDBGStandbyMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @brief Disable the Debug Module during STANDBY mode.
- * @retval None
- */
-void HAL_DBGMCU_DisableDBGStandbyMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @}
- */
-
-/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions
- * @brief HAL SYSCFG configuration functions
- *
-@verbatim
- ===============================================================================
- ##### HAL SYSCFG configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Start a hardware SRAM2 erase operation
- (+) Enable/Disable the Internal FLASH Bank Swapping
- (+) Configure the Voltage reference buffer
- (+) Enable/Disable the Voltage reference buffer
- (+) Enable/Disable the I/O analog switch voltage booster
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start a hardware SRAM2 erase operation.
- * @note As long as SRAM2 is not erased the SRAM2ER bit will be set.
- * This bit is automatically reset at the end of the SRAM2 erase operation.
- * @retval None
- */
-void HAL_SYSCFG_SRAM2Erase(void)
-{
- /* unlock the write protection of the SRAM2ER bit */
- SYSCFG->SKR = 0xCA;
- SYSCFG->SKR = 0x53;
- /* Starts a hardware SRAM2 erase operation*/
- *(__IO uint32_t *) SCSR_SRAM2ER_BB = 0x00000001UL;
-}
-
-/**
- * @brief Enable the Internal FLASH Bank Swapping.
- *
- * @note This function can be used only for STM32L4xx devices.
- *
- * @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
- * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)
- *
- * @retval None
- */
-void HAL_SYSCFG_EnableMemorySwappingBank(void)
-{
- *(__IO uint32_t *)FB_MODE_BB = 0x00000001UL;
-}
-
-/**
- * @brief Disable the Internal FLASH Bank Swapping.
- *
- * @note This function can be used only for STM32L4xx devices.
- *
- * @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000)
- * and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)
- *
- * @retval None
- */
-void HAL_SYSCFG_DisableMemorySwappingBank(void)
-{
-
- *(__IO uint32_t *)FB_MODE_BB = 0x00000000UL;
-}
-
-#if defined(VREFBUF)
-/**
- * @brief Configure the internal voltage reference buffer voltage scale.
- * @param VoltageScaling specifies the output voltage to achieve
- * This parameter can be one of the following values:
- * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V.
- * This requires VDDA equal to or higher than 2.4 V.
- * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V.
- * This requires VDDA equal to or higher than 2.8 V.
- * @retval None
- */
-void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
-{
- /* Check the parameters */
- assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
-
- MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
-}
-
-/**
- * @brief Configure the internal voltage reference buffer high impedance mode.
- * @param Mode specifies the high impedance mode
- * This parameter can be one of the following values:
- * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
- * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
- * @retval None
- */
-void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
-{
- /* Check the parameters */
- assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
-
- MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
-}
-
-/**
- * @brief Tune the Internal Voltage Reference buffer (VREFBUF).
- * @retval None
- */
-void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
-{
- /* Check the parameters */
- assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
-
- MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
-}
-
-/**
- * @brief Enable the Internal Voltage Reference buffer (VREFBUF).
- * @retval HAL_OK/HAL_TIMEOUT
- */
-HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
-{
- uint32_t tickstart;
-
- SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait for VRR bit */
- while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0U)
- {
- if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable the Internal Voltage Reference buffer (VREFBUF).
- *
- * @retval None
- */
-void HAL_SYSCFG_DisableVREFBUF(void)
-{
- CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
-}
-#endif /* VREFBUF */
-
-/**
- * @brief Enable the I/O analog switch voltage booster
- *
- * @retval None
- */
-void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void)
-{
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
-}
-
-/**
- * @brief Disable the I/O analog switch voltage booster
- *
- * @retval None
- */
-void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void)
-{
- CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c
deleted file mode 100644
index f95efa9..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c
+++ /dev/null
@@ -1,517 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_cortex.c
- * @author MCD Application Team
- * @brief CORTEX HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the CORTEX:
- * + Initialization and Configuration functions
- * + Peripheral Control functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
-
- [..]
- *** How to configure Interrupts using CORTEX HAL driver ***
- ===========================================================
- [..]
- This section provides functions allowing to configure the NVIC interrupts (IRQ).
- The Cortex-M4 exceptions are managed by CMSIS functions.
-
- (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
- (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
- (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
-
- -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
- The pending IRQ priority will be managed only by the sub priority.
-
- -@- IRQ priority order (sorted by highest to lowest priority):
- (+@) Lowest pre-emption priority
- (+@) Lowest sub priority
- (+@) Lowest hardware priority (IRQ number)
-
- [..]
- *** How to configure SysTick using CORTEX HAL driver ***
- ========================================================
- [..]
- Setup SysTick Timer for time base.
-
- (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
- is a CMSIS function that:
- (++) Configures the SysTick Reload register with value passed as function parameter.
- (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
- (++) Resets the SysTick Counter register.
- (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
- (++) Enables the SysTick Interrupt.
- (++) Starts the SysTick Counter.
-
- (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
- __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
- HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
- inside the stm32l4xx_hal_cortex.h file.
-
- (+) You can change the SysTick IRQ priority by calling the
- HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
- call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
-
- (+) To adjust the SysTick time base, use the following formula:
-
- Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
- (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
- (++) Reload Value should not exceed 0xFFFFFF
-
- @endverbatim
- ******************************************************************************
-
- The table below gives the allowed values of the pre-emption priority and subpriority according
- to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
-
- ==========================================================================================================================
- NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
- ==========================================================================================================================
- NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority
- | | | 4 bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority
- | | | 3 bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
- | | | 2 bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
- | | | 1 bit for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
- | | | 0 bit for subpriority
- ==========================================================================================================================
-
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file in
- * the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CORTEX
- * @{
- */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup CORTEX_Exported_Functions
- * @{
- */
-
-
-/** @addtogroup CORTEX_Exported_Functions_Group1
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and Configuration functions #####
- ==============================================================================
- [..]
- This section provides the CORTEX HAL driver functions allowing to configure Interrupts
- SysTick functionalities
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Set the priority grouping field (pre-emption priority and subpriority)
- * using the required unlock sequence.
- * @param PriorityGroup: The priority grouping bits length.
- * This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
- * 4 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
- * 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
- * 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
- * 1 bit for subpriority
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
- * 0 bit for subpriority
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
- * The pending IRQ priority will be managed only by the subpriority.
- * @retval None
- */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-
- /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
- NVIC_SetPriorityGrouping(PriorityGroup);
-}
-
-/**
- * @brief Set the priority of an interrupt.
- * @param IRQn: External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
- * @param PreemptPriority: The pre-emption priority for the IRQn channel.
- * This parameter can be a value between 0 and 15
- * A lower priority value indicates a higher priority
- * @param SubPriority: the subpriority level for the IRQ channel.
- * This parameter can be a value between 0 and 15
- * A lower priority value indicates a higher priority.
- * @retval None
- */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t prioritygroup = 0x00;
-
- /* Check the parameters */
- assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-
- prioritygroup = NVIC_GetPriorityGrouping();
-
- NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
-}
-
-/**
- * @brief Enable a device specific interrupt in the NVIC interrupt controller.
- * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
- * function should be called before.
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
- * @retval None
- */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Enable interrupt */
- NVIC_EnableIRQ(IRQn);
-}
-
-/**
- * @brief Disable a device specific interrupt in the NVIC interrupt controller.
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
- * @retval None
- */
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Disable interrupt */
- NVIC_DisableIRQ(IRQn);
-}
-
-/**
- * @brief Initiate a system reset request to reset the MCU.
- * @retval None
- */
-void HAL_NVIC_SystemReset(void)
-{
- /* System Reset */
- NVIC_SystemReset();
-}
-
-/**
- * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
- * Counter is in free running mode to generate periodic interrupts.
- * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
- * @retval status: - 0 Function succeeded.
- * - 1 Function failed.
- */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
- return SysTick_Config(TicksNumb);
-}
-/**
- * @}
- */
-
-/** @addtogroup CORTEX_Exported_Functions_Group2
- * @brief Cortex control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control the CORTEX
- (NVIC, SYSTICK, MPU) functionalities.
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Get the priority grouping field from the NVIC Interrupt Controller.
- * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
- */
-uint32_t HAL_NVIC_GetPriorityGrouping(void)
-{
- /* Get the PRIGROUP[10:8] field value */
- return NVIC_GetPriorityGrouping();
-}
-
-/**
- * @brief Get the priority of an interrupt.
- * @param IRQn: External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
- * @param PriorityGroup: the priority grouping bits length.
- * This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
- * 4 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
- * 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
- * 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
- * 1 bit for subpriority
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
- * 0 bit for subpriority
- * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
- * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
- * @retval None
- */
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
- /* Get priority for Cortex-M system or device specific interrupts */
- NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
-}
-
-/**
- * @brief Set Pending bit of an external interrupt.
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
- * @retval None
- */
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Set interrupt pending */
- NVIC_SetPendingIRQ(IRQn);
-}
-
-/**
- * @brief Get Pending Interrupt (read the pending register in the NVIC
- * and return the pending bit for the specified interrupt).
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
- * @retval status: - 0 Interrupt status is not pending.
- * - 1 Interrupt status is pending.
- */
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Return 1 if pending else 0 */
- return NVIC_GetPendingIRQ(IRQn);
-}
-
-/**
- * @brief Clear the pending bit of an external interrupt.
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
- * @retval None
- */
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Clear pending interrupt */
- NVIC_ClearPendingIRQ(IRQn);
-}
-
-/**
- * @brief Get active interrupt (read the active register in NVIC and return the active bit).
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
- * @retval status: - 0 Interrupt status is not pending.
- * - 1 Interrupt status is pending.
- */
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
-{
- /* Return 1 if active else 0 */
- return NVIC_GetActive(IRQn);
-}
-
-/**
- * @brief Configure the SysTick clock source.
- * @param CLKSource: specifies the SysTick clock source.
- * This parameter can be one of the following values:
- * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
- * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
- * @retval None
- */
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
-{
- /* Check the parameters */
- assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
- if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
- {
- SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
- }
- else
- {
- SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
- }
-}
-
-/**
- * @brief Handle SYSTICK interrupt request.
- * @retval None
- */
-void HAL_SYSTICK_IRQHandler(void)
-{
- HAL_SYSTICK_Callback();
-}
-
-/**
- * @brief SYSTICK callback.
- * @retval None
- */
-__weak void HAL_SYSTICK_Callback(void)
-{
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SYSTICK_Callback could be implemented in the user file
- */
-}
-
-#if (__MPU_PRESENT == 1)
-/**
- * @brief Enable the MPU.
- * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
- * NMI, FAULTMASK and privileged accessto the default memory
- * This parameter can be one of the following values:
- * @arg MPU_HFNMI_PRIVDEF_NONE
- * @arg MPU_HARDFAULT_NMI
- * @arg MPU_PRIVILEGED_DEFAULT
- * @arg MPU_HFNMI_PRIVDEF
- * @retval None
- */
-void HAL_MPU_Enable(uint32_t MPU_Control)
-{
- /* Enable the MPU */
- MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
-
- /* Ensure MPU setting take effects */
- __DSB();
- __ISB();
-}
-
-
-/**
- * @brief Disable the MPU.
- * @retval None
- */
-void HAL_MPU_Disable(void)
-{
- /* Make sure outstanding transfers are done */
- __DMB();
-
- /* Disable the MPU and clear the control register*/
- MPU->CTRL = 0;
-}
-
-
-/**
- * @brief Initialize and configure the Region and the memory to be protected.
- * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
- * the initialization and configuration information.
- * @retval None
- */
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
-{
- /* Check the parameters */
- assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
- assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
-
- /* Set the Region number */
- MPU->RNR = MPU_Init->Number;
-
- if ((MPU_Init->Enable) != RESET)
- {
- /* Check the parameters */
- assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
- assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
- assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
- assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
- assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
- assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
- assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
- assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-
- MPU->RBAR = MPU_Init->BaseAddress;
- MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
- ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
- ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
- ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
- ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
- ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
- ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
- ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
- ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
- }
- else
- {
- MPU->RBAR = 0x00;
- MPU->RASR = 0x00;
- }
-}
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c
deleted file mode 100644
index c0f1fab..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c
+++ /dev/null
@@ -1,1174 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_dma.c
- * @author MCD Application Team
- * @brief DMA HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Direct Memory Access (DMA) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State and errors functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable and configure the peripheral to be connected to the DMA Channel
- (except for internal SRAM / FLASH memories: no initialization is
- necessary). Please refer to the Reference manual for connection between peripherals
- and DMA requests.
-
- (#) For a given Channel, program the required configuration through the following parameters:
- Channel request, Transfer Direction, Source and Destination data formats,
- Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
- using HAL_DMA_Init() function.
-
- Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX
- thanks to:
- (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() ;
- (##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE();
-
- (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
- detection.
-
- (#) Use HAL_DMA_Abort() function to abort the current transfer
-
- -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
- address and destination address and the Length of data to be transferred
- (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
- case a fixed Timeout can be configured by User depending from his application.
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
- (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
- (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
- Source address and destination address and the Length of data to be transferred.
- In this case the DMA interrupt is configured
- (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
- (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
- add his own function to register callbacks with HAL_DMA_RegisterCallback().
-
- *** DMA HAL driver macros list ***
- =============================================
- [..]
- Below the list of macros in DMA HAL driver.
-
- (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
- (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
- (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
- (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
- (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
- (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
- (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not.
-
- [..]
- (@) You can refer to the DMA HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DMA DMA
- * @brief DMA HAL module driver
- * @{
- */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup DMA_Private_Functions DMA Private Functions
- * @{
- */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-#if defined(DMAMUX1)
-static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
-static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
-#endif /* DMAMUX1 */
-
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Functions DMA Exported Functions
- * @{
- */
-
-/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to initialize the DMA Channel source
- and destination addresses, incrementation and data sizes, transfer direction,
- circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
- [..]
- The HAL_DMA_Init() function follows the DMA configuration procedures as described in
- reference manual.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the DMA according to the specified
- * parameters in the DMA_InitTypeDef and initialize the associated handle.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
-{
- uint32_t tmp;
-
- /* Check the DMA handle allocation */
- if(hdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
- assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
- assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
- assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
- assert_param(IS_DMA_MODE(hdma->Init.Mode));
- assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
-
- assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
-
- /* Compute the channel index */
- if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
- {
- /* DMA1 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
- hdma->DmaBaseAddress = DMA1;
- }
- else
- {
- /* DMA2 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
- hdma->DmaBaseAddress = DMA2;
- }
-
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- /* Get the CR register value */
- tmp = hdma->Instance->CCR;
-
- /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
- tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE |
- DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |
- DMA_CCR_DIR | DMA_CCR_MEM2MEM));
-
- /* Prepare the DMA Channel configuration */
- tmp |= hdma->Init.Direction |
- hdma->Init.PeriphInc | hdma->Init.MemInc |
- hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
- hdma->Init.Mode | hdma->Init.Priority;
-
- /* Write to DMA Channel CR register */
- hdma->Instance->CCR = tmp;
-
-#if defined(DMAMUX1)
- /* Initialize parameters for DMAMUX channel :
- DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
- */
- DMA_CalcDMAMUXChannelBaseAndMask(hdma);
-
- if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
- {
- /* if memory to memory force the request to 0*/
- hdma->Init.Request = DMA_REQUEST_MEM2MEM;
- }
-
- /* Set peripheral request to DMAMUX channel */
- hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
-
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- if(((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
- {
- /* Initialize parameters for DMAMUX request generator :
- DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
- */
- DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
-
- /* Reset the DMAMUX request generator register*/
- hdma->DMAmuxRequestGen->RGCR = 0U;
-
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
- }
- else
- {
- hdma->DMAmuxRequestGen = 0U;
- hdma->DMAmuxRequestGenStatus = 0U;
- hdma->DMAmuxRequestGenStatusMask = 0U;
- }
-#endif /* DMAMUX1 */
-
-#if !defined (DMAMUX1)
-
- /* Set request selection */
- if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
- {
- /* Write to DMA channel selection register */
- if (DMA1 == hdma->DmaBaseAddress)
- {
- /* Reset request selection for DMA1 Channelx */
- DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
-
- /* Configure request selection for DMA1 Channelx */
- DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
- }
- else /* DMA2 */
- {
- /* Reset request selection for DMA2 Channelx */
- DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
-
- /* Configure request selection for DMA2 Channelx */
- DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
- }
- }
-
-#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
- /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
- /* STM32L496xx || STM32L4A6xx */
-
- /* Initialise the error code */
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Initialize the DMA state*/
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Allocate lock resource and initialize it */
- hdma->Lock = HAL_UNLOCKED;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the DMA peripheral.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
-{
-
- /* Check the DMA handle allocation */
- if (NULL == hdma )
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-
- /* Disable the selected DMA Channelx */
- __HAL_DMA_DISABLE(hdma);
-
- /* Compute the channel index */
- if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
- {
- /* DMA1 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
- hdma->DmaBaseAddress = DMA1;
- }
- else
- {
- /* DMA2 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
- hdma->DmaBaseAddress = DMA2;
- }
-
- /* Reset DMA Channel control register */
- hdma->Instance->CCR = 0U;
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
-
-#if !defined (DMAMUX1)
-
- /* Reset DMA channel selection register */
- if (DMA1 == hdma->DmaBaseAddress)
- {
- /* DMA1 */
- DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
- }
- else
- {
- /* DMA2 */
- DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
- }
-#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
- /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
- /* STM32L496xx || STM32L4A6xx */
-
-#if defined(DMAMUX1)
-
- /* Initialize parameters for DMAMUX channel :
- DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
-
- DMA_CalcDMAMUXChannelBaseAndMask(hdma);
-
- /* Reset the DMAMUX channel that corresponds to the DMA channel */
- hdma->DMAmuxChannel->CCR = 0U;
-
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- /* Reset Request generator parameters if any */
- if(((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
- {
- /* Initialize parameters for DMAMUX request generator :
- DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
- */
- DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
-
- /* Reset the DMAMUX request generator register*/
- hdma->DMAmuxRequestGen->RGCR = 0U;
-
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
- }
-
- hdma->DMAmuxRequestGen = 0U;
- hdma->DMAmuxRequestGenStatus = 0U;
- hdma->DMAmuxRequestGenStatusMask = 0U;
-
-#endif /* DMAMUX1 */
-
- /* Clean callbacks */
- hdma->XferCpltCallback = NULL;
- hdma->XferHalfCpltCallback = NULL;
- hdma->XferErrorCallback = NULL;
- hdma->XferAbortCallback = NULL;
-
- /* Initialise the error code */
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Initialize the DMA state */
- hdma->State = HAL_DMA_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
- * @brief Input and Output operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure the source, destination address and data length and Start DMA transfer
- (+) Configure the source, destination address and data length and
- Start DMA transfer with interrupt
- (+) Abort DMA transfer
- (+) Poll for transfer complete
- (+) Handle DMA interrupt request
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start the DMA Transfer.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param SrcAddress The source memory Buffer address
- * @param DstAddress The destination memory Buffer address
- * @param DataLength The length of data to be transferred from source to destination
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Disable the peripheral */
- __HAL_DMA_DISABLE(hdma);
-
- /* Configure the source, destination address and the data length & clear flags*/
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- /* Enable the Peripheral */
- __HAL_DMA_ENABLE(hdma);
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
- status = HAL_BUSY;
- }
- return status;
-}
-
-/**
- * @brief Start the DMA Transfer with interrupt enabled.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param SrcAddress The source memory Buffer address
- * @param DstAddress The destination memory Buffer address
- * @param DataLength The length of data to be transferred from source to destination
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Disable the peripheral */
- __HAL_DMA_DISABLE(hdma);
-
- /* Configure the source, destination address and the data length & clear flags*/
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- /* Enable the transfer complete interrupt */
- /* Enable the transfer Error interrupt */
- if(NULL != hdma->XferHalfCpltCallback )
- {
- /* Enable the Half transfer complete interrupt as well */
- __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
- }
- else
- {
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
- __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
- }
-
-#ifdef DMAMUX1
-
- /* Check if DMAMUX Synchronization is enabled*/
- if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
- {
- /* Enable DMAMUX sync overrun IT*/
- hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
- }
-
- if(hdma->DMAmuxRequestGen != 0U)
- {
- /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
- /* enable the request gen overrun IT*/
- hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
- }
-
-#endif /* DMAMUX1 */
-
- /* Enable the Peripheral */
- __HAL_DMA_ENABLE(hdma);
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Remain BUSY */
- status = HAL_BUSY;
- }
- return status;
-}
-
-/**
- * @brief Abort the DMA Transfer.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the DMA peripheral state */
- if(hdma->State != HAL_DMA_STATE_BUSY)
- {
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_ERROR;
- }
- else
- {
- /* Disable DMA IT */
- __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-
-#if defined(DMAMUX1)
- /* disable the DMAMUX sync overrun IT*/
- hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
-#endif /* DMAMUX1 */
-
- /* Disable the channel */
- __HAL_DMA_DISABLE(hdma);
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
-
-#if defined(DMAMUX1)
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- if(hdma->DMAmuxRequestGen != 0U)
- {
- /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
- /* disable the request gen overrun IT*/
- hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
-
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
- }
-
-#endif /* DMAMUX1 */
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return status;
- }
-}
-
-/**
- * @brief Aborts the DMA Transfer in Interrupt mode.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if(HAL_DMA_STATE_BUSY != hdma->State)
- {
- /* no transfer ongoing */
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-
- status = HAL_ERROR;
- }
- else
- {
- /* Disable DMA IT */
- __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-
- /* Disable the channel */
- __HAL_DMA_DISABLE(hdma);
-
-#if defined(DMAMUX1)
- /* disable the DMAMUX sync overrun IT*/
- hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
-
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- if(hdma->DMAmuxRequestGen != 0U)
- {
- /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
- /* disable the request gen overrun IT*/
- hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
-
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
- }
-
-#else
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
-#endif /* DMAMUX1 */
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Call User Abort callback */
- if(hdma->XferAbortCallback != NULL)
- {
- hdma->XferAbortCallback(hdma);
- }
- }
- return status;
-}
-
-/**
- * @brief Polling for transfer complete.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param CompleteLevel Specifies the DMA level complete.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
-{
- uint32_t temp;
- uint32_t tickstart;
-
- if(HAL_DMA_STATE_BUSY != hdma->State)
- {
- /* no transfer ongoing */
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
- __HAL_UNLOCK(hdma);
- return HAL_ERROR;
- }
-
- /* Polling mode not supported in circular mode */
- if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U)
- {
- hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
- }
-
- /* Get the level transfer complete flag */
- if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
- {
- /* Transfer Complete flag */
- temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU);
- }
- else
- {
- /* Half Transfer Complete flag */
- temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU);
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((hdma->DmaBaseAddress->ISR & temp) == 0U)
- {
- if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U)
- {
- /* When a DMA transfer error occurs */
- /* A hardware clear of its EN bits is performed */
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
-
- /* Update error code */
- hdma->ErrorCode = HAL_DMA_ERROR_TE;
-
- /* Change the DMA state */
- hdma->State= HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_ERROR;
- }
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
- {
- /* Update error code */
- hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_ERROR;
- }
- }
- }
-
-#if defined(DMAMUX1)
- /*Check for DMAMUX Request generator (if used) overrun status */
- if(hdma->DMAmuxRequestGen != 0U)
- {
- /* if using DMAMUX request generator Check for DMAMUX request generator overrun */
- if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
- {
- /* Disable the request gen overrun interrupt */
- hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
-
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
-
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
- }
- }
-
- /* Check for DMAMUX Synchronization overrun */
- if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
- {
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
- }
-#endif /* DMAMUX1 */
-
- if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
- {
- /* Clear the transfer complete flag */
- hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1CU));
-
- /* Process unlocked */
- __HAL_UNLOCK(hdma);
-
- /* The selected Channelx EN bit is cleared (DMA is disabled and
- all transfers are complete) */
- hdma->State = HAL_DMA_STATE_READY;
- }
- else
- {
- /* Clear the half transfer complete flag */
- hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU));
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle DMA interrupt request.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval None
- */
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
-{
- uint32_t flag_it = hdma->DmaBaseAddress->ISR;
- uint32_t source_it = hdma->Instance->CCR;
-
- /* Half Transfer Complete Interrupt management ******************************/
- if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
- {
- /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- {
- /* Disable the half transfer interrupt */
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
- }
- /* Clear the half transfer complete flag */
- hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
-
- /* DMA peripheral state is not updated in Half Transfer */
- /* but in Transfer Complete case */
-
- if(hdma->XferHalfCpltCallback != NULL)
- {
- /* Half transfer callback */
- hdma->XferHalfCpltCallback(hdma);
- }
- }
-
- /* Transfer Complete Interrupt management ***********************************/
- else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U))
- {
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- {
- /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
- /* Disable the transfer complete and error interrupt */
- /* if the DMA mode is not CIRCULAR */
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
- }
- /* Clear the transfer complete flag */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1CU));
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if(hdma->XferCpltCallback != NULL)
- {
- /* Transfer complete callback */
- hdma->XferCpltCallback(hdma);
- }
- }
-
- /* Transfer Error Interrupt management **************************************/
- else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U))
- {
- /* When a DMA transfer error occurs */
- /* A hardware clear of its EN bits is performed */
- /* Disable ALL DMA IT */
- __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
-
- /* Update error code */
- hdma->ErrorCode = HAL_DMA_ERROR_TE;
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if (hdma->XferErrorCallback != NULL)
- {
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
- }
- }
- else
- {
- /* Nothing To Do */
- }
- return;
-}
-
-/**
- * @brief Register callbacks
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param CallbackID User Callback identifier
- * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
- * @param pCallback pointer to private callbacsk function which has pointer to
- * a DMA_HandleTypeDef structure as parameter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- switch (CallbackID)
- {
- case HAL_DMA_XFER_CPLT_CB_ID:
- hdma->XferCpltCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_HALFCPLT_CB_ID:
- hdma->XferHalfCpltCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_ERROR_CB_ID:
- hdma->XferErrorCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_ABORT_CB_ID:
- hdma->XferAbortCallback = pCallback;
- break;
-
- default:
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
- return status;
-}
-
-/**
- * @brief UnRegister callbacks
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param CallbackID User Callback identifier
- * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- switch (CallbackID)
- {
- case HAL_DMA_XFER_CPLT_CB_ID:
- hdma->XferCpltCallback = NULL;
- break;
-
- case HAL_DMA_XFER_HALFCPLT_CB_ID:
- hdma->XferHalfCpltCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ERROR_CB_ID:
- hdma->XferErrorCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ABORT_CB_ID:
- hdma->XferAbortCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ALL_CB_ID:
- hdma->XferCpltCallback = NULL;
- hdma->XferHalfCpltCallback = NULL;
- hdma->XferErrorCallback = NULL;
- hdma->XferAbortCallback = NULL;
- break;
-
- default:
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
- return status;
-}
-
-/**
- * @}
- */
-
-
-
-/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Check the DMA state
- (+) Get error code
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the DMA handle state.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL state
- */
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
-{
- /* Return DMA handle state */
- return hdma->State;
-}
-
-/**
- * @brief Return the DMA error code.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval DMA Error Code
- */
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
-{
- return hdma->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup DMA_Private_Functions
- * @{
- */
-
-/**
- * @brief Sets the DMA Transfer parameter.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param SrcAddress The source memory Buffer address
- * @param DstAddress The destination memory Buffer address
- * @param DataLength The length of data to be transferred from source to destination
- * @retval HAL status
- */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-#if defined(DMAMUX1)
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- if(hdma->DMAmuxRequestGen != 0U)
- {
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
- }
-#endif
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
-
- /* Configure DMA Channel data length */
- hdma->Instance->CNDTR = DataLength;
-
- /* Memory to Peripheral */
- if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
- {
- /* Configure DMA Channel destination address */
- hdma->Instance->CPAR = DstAddress;
-
- /* Configure DMA Channel source address */
- hdma->Instance->CMAR = SrcAddress;
- }
- /* Peripheral to Memory */
- else
- {
- /* Configure DMA Channel source address */
- hdma->Instance->CPAR = SrcAddress;
-
- /* Configure DMA Channel destination address */
- hdma->Instance->CMAR = DstAddress;
- }
-}
-
-#if defined(DMAMUX1)
-
-/**
- * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on channel number
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval None
- */
-static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
-{
- uint32_t channel_number;
-
- /* check if instance is not outside the DMA channel range */
- if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)
- {
- /* DMA1 */
- hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U));
- }
- else
- {
- /* DMA2 */
- hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U));
- }
-
- channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
- hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
- hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU);
-}
-
-/**
- * @brief Updates the DMA handle with the DMAMUX request generator params
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval None
- */
-
-static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
-{
- uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
-
- /* DMA Channels are connected to DMAMUX1 request generator blocks*/
- hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
-
- hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
-
- /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/
- hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);
-}
-
-#endif /* DMAMUX1 */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_DMA_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c
deleted file mode 100644
index e6684a2..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_dma_ex.c
- * @author MCD Application Team
- * @brief DMA Extension HAL module driver
- * This file provides firmware functions to manage the following
- * functionalities of the DMA Extension peripheral:
- * + Extended features functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The DMA Extension HAL driver can be used as follows:
-
- (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
- (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
- Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
- to respectively enable/disable the request generator.
-
- (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from
- the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler.
- As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be
- called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
- (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
-
- -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
- -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
- -@- In Multi (Double) buffer mode, it is possible to update the base address for
- the AHB memory port on the fly (DMA_CM0ARx or DMA_CM1ARx) when the channel is enabled.
-
-
- @endverbatim
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-#if defined(DMAMUX1)
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DMAEx DMAEx
- * @brief DMA Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private Constants ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-
-/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
- * @{
- */
-
-/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions
- * @brief Extended features functions
- *
-@verbatim
- ===============================================================================
- ##### Extended features functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
-
- (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
- (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
- Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
- to respectively enable/disable the request generator.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA channel.
- * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-
- assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
-
- assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity));
- assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
- assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
- assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
-
- /*Check if the DMA state is ready */
- if(hdma->State == HAL_DMA_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hdma);
-
- /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
- MODIFY_REG( hdma->DMAmuxChannel->CCR, \
- (~DMAMUX_CxCR_DMAREQ_ID) , \
- ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
- pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \
- ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
-
- /* Process UnLocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_OK;
- }
- else
- {
- /*DMA State not Ready*/
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance).
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA channel.
- * @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
- * contains the request generator parameters.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-
- assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
-
- assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
- assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
-
- /* check if the DMA state is ready
- and DMA is using a DMAMUX request generator block
- */
- if((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))
- {
- /* Process Locked */
- __HAL_LOCK(hdma);
-
- /* Set the request generator new parameters */
- hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
- ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \
- pRequestGeneratorConfig->Polarity;
- /* Process UnLocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable the DMAMUX request generator block used by the given DMA channel (instance).
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-
- /* check if the DMA state is ready
- and DMA is using a DMAMUX request generator block
- */
- if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
- {
-
- /* Enable the request generator*/
- hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable the DMAMUX request generator block used by the given DMA channel (instance).
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-
- /* check if the DMA state is ready
- and DMA is using a DMAMUX request generator block
- */
- if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
- {
-
- /* Disable the request generator*/
- hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Handles DMAMUX interrupt request.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA channel.
- * @retval None
- */
-void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
-{
- /* Check for DMAMUX Synchronization overrun */
- if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
- {
- /* Disable the synchro overrun interrupt */
- hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
-
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
-
- if(hdma->XferErrorCallback != NULL)
- {
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
- }
- }
-
- if(hdma->DMAmuxRequestGen != 0)
- {
- /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
- if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
- {
- /* Disable the request gen overrun interrupt */
- hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
-
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
-
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
-
- if(hdma->XferErrorCallback != NULL)
- {
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
- }
- }
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DMAMUX1 */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c
deleted file mode 100644
index 662203c..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c
+++ /dev/null
@@ -1,632 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_exti.c
- * @author MCD Application Team
- * @brief EXTI HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### EXTI Peripheral features #####
- ==============================================================================
- [..]
- (+) Each Exti line can be configured within this driver.
-
- (+) Exti line can be configured in 3 different modes
- (++) Interrupt
- (++) Event
- (++) Both of them
-
- (+) Configurable Exti lines can be configured with 3 different triggers
- (++) Rising
- (++) Falling
- (++) Both of them
-
- (+) When set in interrupt mode, configurable Exti lines have two different
- interrupts pending registers which allow to distinguish which transition
- occurs:
- (++) Rising edge pending interrupt
- (++) Falling
-
- (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
- be selected through multiplexer.
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
-
- (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
- (++) Choose the interrupt line number by setting "Line" member from
- EXTI_ConfigTypeDef structure.
- (++) Configure the interrupt and/or event mode using "Mode" member from
- EXTI_ConfigTypeDef structure.
- (++) For configurable lines, configure rising and/or falling trigger
- "Trigger" member from EXTI_ConfigTypeDef structure.
- (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
- member from GPIO_InitTypeDef structure.
-
- (#) Get current Exti configuration of a dedicated line using
- HAL_EXTI_GetConfigLine().
- (++) Provide exiting handle as parameter.
- (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
-
- (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
- (++) Provide exiting handle as parameter.
-
- (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
- (++) Provide exiting handle as first parameter.
- (++) Provide which callback will be registered using one value from
- EXTI_CallbackIDTypeDef.
- (++) Provide callback function pointer.
-
- (#) Get interrupt pending bit using HAL_EXTI_GetPending().
-
- (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
-
- (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
-
- @endverbatim
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup EXTI
- * @{
- */
-/** MISRA C:2012 deviation rule has been granted for following rule:
- * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
- * of bounds [0,3] in following API :
- * HAL_EXTI_SetConfigLine
- * HAL_EXTI_GetConfigLine
- * HAL_EXTI_ClearConfigLine
- */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines ------------------------------------------------------------*/
-/** @defgroup EXTI_Private_Constants EXTI Private Constants
- * @{
- */
-#define EXTI_MODE_OFFSET 0x08u /* 0x20: offset between MCU IMR/EMR registers */
-#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between MCU Rising/Falling configuration registers */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup EXTI_Exported_Functions
- * @{
- */
-
-/** @addtogroup EXTI_Exported_Functions_Group1
- * @brief Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set configuration of a dedicated Exti line.
- * @param hexti Exti handle.
- * @param pExtiConfig Pointer on EXTI configuration to be set.
- * @retval HAL Status.
- */
-HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
-{
- __IO uint32_t *regaddr;
- uint32_t regval;
- uint32_t linepos;
- uint32_t maskline;
- uint32_t offset;
-
- /* Check null pointer */
- if ((hexti == NULL) || (pExtiConfig == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Check parameters */
- assert_param(IS_EXTI_LINE(pExtiConfig->Line));
- assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
-
- /* Assign line number to handle */
- hexti->Line = pExtiConfig->Line;
-
- /* Compute line register offset and line mask */
- offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
- linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
- maskline = (1uL << linepos);
-
- /* Configure triggers for configurable lines */
- if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
- {
- assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
-
- /* Configure rising trigger */
- regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
- regval = *regaddr;
-
- /* Mask or set line */
- if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
- {
- regval |= maskline;
- }
- else
- {
- regval &= ~maskline;
- }
-
- /* Store rising trigger mode */
- *regaddr = regval;
-
- /* Configure falling trigger */
- regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
- regval = *regaddr;
-
- /* Mask or set line */
- if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
- {
- regval |= maskline;
- }
- else
- {
- regval &= ~maskline;
- }
-
- /* Store falling trigger mode */
- *regaddr = regval;
-
- /* Configure gpio port selection in case of gpio exti line */
- if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
- {
- assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
- assert_param(IS_EXTI_GPIO_PIN(linepos));
-
- regval = SYSCFG->EXTICR[linepos >> 2u];
- regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
- regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
- SYSCFG->EXTICR[linepos >> 2u] = regval;
- }
- }
-
- /* Configure interrupt mode : read current mode */
- regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
- regval = *regaddr;
-
- /* Mask or set line */
- if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
- {
- regval |= maskline;
- }
- else
- {
- regval &= ~maskline;
- }
-
- /* Store interrupt mode */
- *regaddr = regval;
-
- /* The event mode cannot be configured if the line does not support it */
- assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT));
-
- /* Configure event mode : read current mode */
- regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
- regval = *regaddr;
-
- /* Mask or set line */
- if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
- {
- regval |= maskline;
- }
- else
- {
- regval &= ~maskline;
- }
-
- /* Store event mode */
- *regaddr = regval;
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Get configuration of a dedicated Exti line.
- * @param hexti Exti handle.
- * @param pExtiConfig Pointer on structure to store Exti configuration.
- * @retval HAL Status.
- */
-HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
-{
- __IO uint32_t *regaddr;
- uint32_t regval;
- uint32_t linepos;
- uint32_t maskline;
- uint32_t offset;
-
- /* Check null pointer */
- if ((hexti == NULL) || (pExtiConfig == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Check the parameter */
- assert_param(IS_EXTI_LINE(hexti->Line));
-
- /* Store handle line number to configuration structure */
- pExtiConfig->Line = hexti->Line;
-
- /* Compute line register offset and line mask */
- offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
- linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
- maskline = (1uL << linepos);
-
- /* 1] Get core mode : interrupt */
- regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
- regval = *regaddr;
-
- /* Check if selected line is enable */
- if ((regval & maskline) != 0x00u)
- {
- pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
- }
- else
- {
- pExtiConfig->Mode = EXTI_MODE_NONE;
- }
-
- /* Get event mode */
- regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
- regval = *regaddr;
-
- /* Check if selected line is enable */
- if ((regval & maskline) != 0x00u)
- {
- pExtiConfig->Mode |= EXTI_MODE_EVENT;
- }
-
- /* Get default Trigger and GPIOSel configuration */
- pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
- pExtiConfig->GPIOSel = 0x00u;
-
- /* 2] Get trigger for configurable lines : rising */
- if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
- {
- regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
- regval = *regaddr;
-
- /* Check if configuration of selected line is enable */
- if ((regval & maskline) != 0x00u)
- {
- pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
- }
-
- /* Get falling configuration */
- regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
- regval = *regaddr;
-
- /* Check if configuration of selected line is enable */
- if ((regval & maskline) != 0x00u)
- {
- pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
- }
-
- /* Get Gpio port selection for gpio lines */
- if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
- {
- assert_param(IS_EXTI_GPIO_PIN(linepos));
-
- regval = SYSCFG->EXTICR[linepos >> 2u];
- pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
- }
- }
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Clear whole configuration of a dedicated Exti line.
- * @param hexti Exti handle.
- * @retval HAL Status.
- */
-HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
-{
- __IO uint32_t *regaddr;
- uint32_t regval;
- uint32_t linepos;
- uint32_t maskline;
- uint32_t offset;
-
- /* Check null pointer */
- if (hexti == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameter */
- assert_param(IS_EXTI_LINE(hexti->Line));
-
- /* compute line register offset and line mask */
- offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
- linepos = (hexti->Line & EXTI_PIN_MASK);
- maskline = (1uL << linepos);
-
- /* 1] Clear interrupt mode */
- regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
- regval = (*regaddr & ~maskline);
- *regaddr = regval;
-
- /* 2] Clear event mode */
- regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
- regval = (*regaddr & ~maskline);
- *regaddr = regval;
-
- /* 3] Clear triggers in case of configurable lines */
- if ((hexti->Line & EXTI_CONFIG) != 0x00u)
- {
- regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
- regval = (*regaddr & ~maskline);
- *regaddr = regval;
-
- regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
- regval = (*regaddr & ~maskline);
- *regaddr = regval;
-
- /* Get Gpio port selection for gpio lines */
- if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
- {
- assert_param(IS_EXTI_GPIO_PIN(linepos));
-
- regval = SYSCFG->EXTICR[linepos >> 2u];
- regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
- SYSCFG->EXTICR[linepos >> 2u] = regval;
- }
- }
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Register callback for a dedicated Exti line.
- * @param hexti Exti handle.
- * @param CallbackID User callback identifier.
- * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
- * @param pPendingCbfn function pointer to be stored as callback.
- * @retval HAL Status.
- */
-HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- switch (CallbackID)
- {
- case HAL_EXTI_COMMON_CB_ID:
- hexti->PendingCallback = pPendingCbfn;
- break;
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- return status;
-}
-
-
-/**
- * @brief Store line number as handle private field.
- * @param hexti Exti handle.
- * @param ExtiLine Exti line number.
- * This parameter can be from 0 to @ref EXTI_LINE_NB.
- * @retval HAL Status.
- */
-HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(ExtiLine));
-
- /* Check null pointer */
- if (hexti == NULL)
- {
- return HAL_ERROR;
- }
- else
- {
- /* Store line number as handle private field */
- hexti->Line = ExtiLine;
-
- return HAL_OK;
- }
-}
-
-
-/**
- * @}
- */
-
-/** @addtogroup EXTI_Exported_Functions_Group2
- * @brief EXTI IO functions.
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Handle EXTI interrupt request.
- * @param hexti Exti handle.
- * @retval none.
- */
-void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
-{
- __IO uint32_t *regaddr;
- uint32_t regval;
- uint32_t maskline;
- uint32_t offset;
-
- /* Compute line register offset and line mask */
- offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
- maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
-
- /* Get pending bit */
- regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
- regval = (*regaddr & maskline);
-
- if (regval != 0x00u)
- {
- /* Clear pending bit */
- *regaddr = maskline;
-
- /* Call callback */
- if (hexti->PendingCallback != NULL)
- {
- hexti->PendingCallback();
- }
- }
-}
-
-
-/**
- * @brief Get interrupt pending bit of a dedicated line.
- * @param hexti Exti handle.
- * @param Edge Specify which pending edge as to be checked.
- * This parameter can be one of the following values:
- * @arg @ref EXTI_TRIGGER_RISING_FALLING
- * This parameter is kept for compatibility with other series.
- * @retval 1 if interrupt is pending else 0.
- */
-uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
-{
- __IO uint32_t *regaddr;
- uint32_t regval;
- uint32_t linepos;
- uint32_t maskline;
- uint32_t offset;
-
- /* Check parameters */
- assert_param(IS_EXTI_LINE(hexti->Line));
- assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
- assert_param(IS_EXTI_PENDING_EDGE(Edge));
-
- /* Compute line register offset and line mask */
- offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
- linepos = (hexti->Line & EXTI_PIN_MASK);
- maskline = (1uL << linepos);
-
- /* Get pending bit */
- regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
-
- /* return 1 if bit is set else 0 */
- regval = ((*regaddr & maskline) >> linepos);
- return regval;
-}
-
-
-/**
- * @brief Clear interrupt pending bit of a dedicated line.
- * @param hexti Exti handle.
- * @param Edge Specify which pending edge as to be clear.
- * This parameter can be one of the following values:
- * @arg @ref EXTI_TRIGGER_RISING_FALLING
- * This parameter is kept for compatibility with other series.
- * @retval None.
- */
-void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
-{
- __IO uint32_t *regaddr;
- uint32_t maskline;
- uint32_t offset;
-
- /* Check parameters */
- assert_param(IS_EXTI_LINE(hexti->Line));
- assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
- assert_param(IS_EXTI_PENDING_EDGE(Edge));
-
- /* compute line register offset and line mask */
- offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
- maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
-
- /* Get pending register address */
- regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
-
- /* Clear Pending bit */
- *regaddr = maskline;
-}
-
-
-/**
- * @brief Generate a software interrupt for a dedicated line.
- * @param hexti Exti handle.
- * @retval None.
- */
-void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
-{
- __IO uint32_t *regaddr;
- uint32_t maskline;
- uint32_t offset;
-
- /* Check parameters */
- assert_param(IS_EXTI_LINE(hexti->Line));
- assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
-
- /* compute line register offset and line mask */
- offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
- maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
-
- regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
- *regaddr = maskline;
-}
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_EXTI_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c
deleted file mode 100644
index 75fa3ea..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c
+++ /dev/null
@@ -1,764 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_flash.c
- * @author MCD Application Team
- * @brief FLASH HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the internal FLASH memory:
- * + Program operations functions
- * + Memory Control functions
- * + Peripheral Errors functions
- *
- @verbatim
- ==============================================================================
- ##### FLASH peripheral features #####
- ==============================================================================
-
- [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
- to the Flash memory. It implements the erase and program Flash memory operations
- and the read and write protection mechanisms.
-
- [..] The Flash memory interface accelerates code execution with a system of instruction
- prefetch and cache lines.
-
- [..] The FLASH main features are:
- (+) Flash memory read operations
- (+) Flash memory program/erase operations
- (+) Read / write protections
- (+) Option bytes programming
- (+) Prefetch on I-Code
- (+) 32 cache lines of 4*64 bits on I-Code
- (+) 8 cache lines of 4*64 bits on D-Code
- (+) Error code correction (ECC) : Data in flash are 72-bits word
- (8 bits added per double word)
-
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver provides functions and macros to configure and program the FLASH
- memory of all STM32L4xx devices.
-
- (#) Flash Memory IO Programming functions:
- (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
- HAL_FLASH_Lock() functions
- (++) Program functions: double word and fast program (full row programming)
- (++) There Two modes of programming :
- (+++) Polling mode using HAL_FLASH_Program() function
- (+++) Interrupt mode using HAL_FLASH_Program_IT() function
-
- (#) Interrupts and flags management functions :
- (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
- (++) Callback functions are called when the flash operations are finished :
- HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
- HAL_FLASH_OperationErrorCallback()
- (++) Get error flag status by calling HAL_GetError()
-
- (#) Option bytes management functions :
- (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
- HAL_FLASH_OB_Lock() functions
- (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.
- In this case, a reset is generated
-
- [..]
- In addition to these functions, this driver includes a set of macros allowing
- to handle the following operations:
- (+) Set the latency
- (+) Enable/Disable the prefetch buffer
- (+) Enable/Disable the Instruction cache and the Data cache
- (+) Reset the Instruction cache and the Data cache
- (+) Enable/Disable the Flash power-down during low-power run and sleep modes
- (+) Enable/Disable the Flash interrupts
- (+) Monitor the Flash flags status
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file in
- * the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup FLASH FLASH
- * @brief FLASH HAL module driver
- * @{
- */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define FLASH_NB_DOUBLE_WORDS_IN_ROW 64
-#else
-#define FLASH_NB_DOUBLE_WORDS_IN_ROW 32
-#endif
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Variables FLASH Private Variables
- * @{
- */
-/**
- * @brief Variable used for Program/Erase sectors under interruption
- */
-FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \
- .ErrorCode = HAL_FLASH_ERROR_NONE, \
- .ProcedureOnGoing = FLASH_PROC_NONE, \
- .Address = 0U, \
- .Bank = FLASH_BANK_1, \
- .Page = 0U, \
- .NbPagesToErase = 0U, \
- .CacheToReactivate = FLASH_CACHE_DISABLED};
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup FLASH_Private_Functions FLASH Private Functions
- * @{
- */
-static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
-static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
- * @{
- */
-
-/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
- * @brief Programming operation functions
- *
-@verbatim
- ===============================================================================
- ##### Programming operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the FLASH
- program operations.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Program double word or fast program of a row at a specified address.
- * @param TypeProgram Indicate the way to program at a specified address.
- * This parameter can be a value of @ref FLASH_Type_Program
- * @param Address specifies the address to be programmed.
- * @param Data specifies the data to be programmed
- * This parameter is the data for the double word program and the address where
- * are stored the data for the row fast program
- *
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
-{
- HAL_StatusTypeDef status;
- uint32_t prog_bit = 0;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* Deactivate the data cache if they are activated to avoid data misbehavior */
- if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
- {
- /* Disable data cache */
- __HAL_FLASH_DATA_CACHE_DISABLE();
- pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
- }
- else
- {
- pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
- }
-
- if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
- {
- /* Program double-word (64-bit) at a specified address */
- FLASH_Program_DoubleWord(Address, Data);
- prog_bit = FLASH_CR_PG;
- }
- else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
- {
- /* Fast program a 32 row double-word (64-bit) at a specified address */
- FLASH_Program_Fast(Address, (uint32_t)Data);
-
- /* If it is the last row, the bit will be cleared at the end of the operation */
- if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
- {
- prog_bit = FLASH_CR_FSTPG;
- }
- }
- else
- {
- /* Nothing to do */
- }
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the program operation is completed, disable the PG or FSTPG Bit */
- if (prog_bit != 0U)
- {
- CLEAR_BIT(FLASH->CR, prog_bit);
- }
-
- /* Flush the caches to be sure of the data consistency */
- FLASH_FlushCaches();
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-
-/**
- * @brief Program double word or fast program of a row at a specified address with interrupt enabled.
- * @param TypeProgram Indicate the way to program at a specified address.
- * This parameter can be a value of @ref FLASH_Type_Program
- * @param Address specifies the address to be programmed.
- * @param Data specifies the data to be programmed
- * This parameter is the data for the double word program and the address where
- * are stored the data for the row fast program
- *
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* Deactivate the data cache if they are activated to avoid data misbehavior */
- if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
- {
- /* Disable data cache */
- __HAL_FLASH_DATA_CACHE_DISABLE();
- pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
- }
- else
- {
- pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
- }
-
- /* Set internal variables used by the IRQ handler */
- if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
- {
- pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_LAST;
- }
- else
- {
- pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
- }
- pFlash.Address = Address;
-
- /* Enable End of Operation and Error interrupts */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
-
- if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
- {
- /* Program double-word (64-bit) at a specified address */
- FLASH_Program_DoubleWord(Address, Data);
- }
- else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
- {
- /* Fast program a 32 row double-word (64-bit) at a specified address */
- FLASH_Program_Fast(Address, (uint32_t)Data);
- }
- else
- {
- /* Nothing to do */
- }
-
- return status;
-}
-
-/**
- * @brief Handle FLASH interrupt request.
- * @retval None
- */
-void HAL_FLASH_IRQHandler(void)
-{
- uint32_t tmp_page;
- uint32_t error;
- FLASH_ProcedureTypeDef procedure;
-
- /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */
- CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB));
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- CLEAR_BIT(FLASH->CR, FLASH_CR_MER2);
-#endif
-
- /* Disable the FSTPG Bit only if it is the last row programmed */
- if(pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)
- {
- CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG);
- }
-
- /* Check FLASH operation error flags */
- error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
-
- if (error !=0U)
- {
- /*Save the error code*/
- pFlash.ErrorCode |= error;
-
- /* Clear error programming flags */
- __HAL_FLASH_CLEAR_FLAG(error);
-
- /* Flush the caches to be sure of the data consistency */
- FLASH_FlushCaches() ;
-
- /* FLASH error interrupt user callback */
- procedure = pFlash.ProcedureOnGoing;
- if(procedure == FLASH_PROC_PAGE_ERASE)
- {
- HAL_FLASH_OperationErrorCallback(pFlash.Page);
- }
- else if(procedure == FLASH_PROC_MASS_ERASE)
- {
- HAL_FLASH_OperationErrorCallback(pFlash.Bank);
- }
- else if((procedure == FLASH_PROC_PROGRAM) ||
- (procedure == FLASH_PROC_PROGRAM_LAST))
- {
- HAL_FLASH_OperationErrorCallback(pFlash.Address);
- }
- else
- {
- HAL_FLASH_OperationErrorCallback(0U);
- }
-
- /*Stop the procedure ongoing*/
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
-
- /* Check FLASH End of Operation flag */
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != 0U)
- {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-
- if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE)
- {
- /* Nb of pages to erased can be decreased */
- pFlash.NbPagesToErase--;
-
- /* Check if there are still pages to erase*/
- if(pFlash.NbPagesToErase != 0U)
- {
- /* Indicate user which page has been erased*/
- HAL_FLASH_EndOfOperationCallback(pFlash.Page);
-
- /* Increment page number */
- pFlash.Page++;
- tmp_page = pFlash.Page;
- FLASH_PageErase(tmp_page, pFlash.Bank);
- }
- else
- {
- /* No more pages to Erase */
- /* Reset Address and stop Erase pages procedure */
- pFlash.Page = 0xFFFFFFFFU;
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-
- /* Flush the caches to be sure of the data consistency */
- FLASH_FlushCaches() ;
-
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(pFlash.Page);
- }
- }
- else
- {
- /* Flush the caches to be sure of the data consistency */
- FLASH_FlushCaches() ;
-
- procedure = pFlash.ProcedureOnGoing;
- if(procedure == FLASH_PROC_MASS_ERASE)
- {
- /* MassErase ended. Return the selected bank */
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
- }
- else if((procedure == FLASH_PROC_PROGRAM) ||
- (procedure == FLASH_PROC_PROGRAM_LAST))
- {
- /* Program ended. Return the selected address */
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(pFlash.Address);
- }
- else
- {
- /* Nothing to do */
- }
-
- /*Clear the procedure ongoing*/
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
- }
-
- if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
- {
- /* Disable End of Operation and Error interrupts */
- __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- }
-}
-
-/**
- * @brief FLASH end of operation interrupt callback.
- * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
- * Mass Erase: Bank number which has been requested to erase
- * Page Erase: Page which has been erased
- * (if 0xFFFFFFFF, it means that all the selected pages have been erased)
- * Program: Address which was selected for data program
- * @retval None
- */
-__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(ReturnValue);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief FLASH operation error interrupt callback.
- * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
- * Mass Erase: Bank number which has been requested to erase
- * Page Erase: Page number which returned an error
- * Program: Address which was selected for data program
- * @retval None
- */
-__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(ReturnValue);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_FLASH_OperationErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
- * @brief Management functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the FLASH
- memory operations.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlock the FLASH control register access.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Unlock(void)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
- {
- /* Authorize the FLASH Registers access */
- WRITE_REG(FLASH->KEYR, FLASH_KEY1);
- WRITE_REG(FLASH->KEYR, FLASH_KEY2);
-
- /* Verify Flash is unlocked */
- if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
- {
- status = HAL_ERROR;
- }
- }
-
- return status;
-}
-
-/**
- * @brief Lock the FLASH control register access.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Lock(void)
-{
- /* Set the LOCK Bit to lock the FLASH Registers access */
- SET_BIT(FLASH->CR, FLASH_CR_LOCK);
-
- return HAL_OK;
-}
-
-/**
- * @brief Unlock the FLASH Option Bytes Registers access.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
-{
- if(READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
- {
- /* Authorizes the Option Byte register programming */
- WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
- WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
- }
- else
- {
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Lock the FLASH Option Bytes Registers access.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
-{
- /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
- SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
-
- return HAL_OK;
-}
-
-/**
- * @brief Launch the option byte loading.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
-{
- /* Set the bit to force the option byte reloading */
- SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
-
- /* Wait for last operation to be completed */
- return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral Errors functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Errors functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time Errors of the FLASH peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Get the specific FLASH error flag.
- * @retval FLASH_ErrorCode: The returned value can be:
- * @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
- * @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
- * @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
- * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
- * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
- * @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag
- * @arg HAL_FLASH_ERROR_NONE: No error set
- * @arg HAL_FLASH_ERROR_OP: FLASH Operation error
- * @arg HAL_FLASH_ERROR_PROG: FLASH Programming error
- * @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error
- * @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error
- * @arg HAL_FLASH_ERROR_SIZ: FLASH Size error
- * @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error
- * @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error
- * @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error
- * @arg HAL_FLASH_ERROR_RD: FLASH PCROP read error
- * @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error
- * @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices)
- */
-uint32_t HAL_FLASH_GetError(void)
-{
- return pFlash.ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @addtogroup FLASH_Private_Functions
- * @{
- */
-
-/**
- * @brief Wait for a FLASH operation to complete.
- * @param Timeout maximum flash operation timeout
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
-{
- /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
- Even if the FLASH operation fails, the BUSY flag will be reset and an error
- flag will be set */
-
- uint32_t tickstart = HAL_GetTick();
- uint32_t error;
-
- while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart) >= Timeout)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
-
- if(error != 0u)
- {
- /*Save the error code*/
- pFlash.ErrorCode |= error;
-
- /* Clear error programming flags */
- __HAL_FLASH_CLEAR_FLAG(error);
-
- return HAL_ERROR;
- }
-
- /* Check FLASH End of Operation flag */
- if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
- {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
- }
-
- /* If there is an error flag set */
- return HAL_OK;
-}
-
-/**
- * @brief Program double-word (64-bit) at a specified address.
- * @param Address specifies the address to be programmed.
- * @param Data specifies the data to be programmed.
- * @retval None
- */
-static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
- /* Set PG bit */
- SET_BIT(FLASH->CR, FLASH_CR_PG);
-
- /* Program first word */
- *(__IO uint32_t*)Address = (uint32_t)Data;
-
- /* Barrier to ensure programming is performed in 2 steps, in right order
- (independently of compiler optimization behavior) */
- __ISB();
-
- /* Program second word */
- *(__IO uint32_t*)(Address+4U) = (uint32_t)(Data >> 32);
-}
-
-/**
- * @brief Fast program a row double-word (64-bit) at a specified address.
- * @param Address specifies the address to be programmed.
- * @param DataAddress specifies the address where the data are stored.
- * @retval None
- */
-static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
-{
- uint32_t primask_bit;
- uint8_t row_index = (2*FLASH_NB_DOUBLE_WORDS_IN_ROW);
- __IO uint32_t *dest_addr = (__IO uint32_t*)Address;
- __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress;
-
- /* Check the parameters */
- assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
-
- /* Set FSTPG bit */
- SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
-
- /* Disable interrupts to avoid any interruption during the loop */
- primask_bit = __get_PRIMASK();
- __disable_irq();
-
- /* Program the double word of the row */
- do
- {
- *dest_addr = *src_addr;
- dest_addr++;
- src_addr++;
- row_index--;
- } while (row_index != 0U);
-
- /* Re-enable the interrupts */
- __set_PRIMASK(primask_bit);
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c
deleted file mode 100644
index d9b1205..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c
+++ /dev/null
@@ -1,1316 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_flash_ex.c
- * @author MCD Application Team
- * @brief Extended FLASH HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the FLASH extended peripheral:
- * + Extended programming operations functions
- *
- @verbatim
- ==============================================================================
- ##### Flash Extended features #####
- ==============================================================================
-
- [..] Comparing to other previous devices, the FLASH interface for STM32L4xx
- devices contains the following additional features
-
- (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
- capability (RWW)
- (+) Dual bank memory organization
- (+) PCROP protection for all banks
-
- ##### How to use this driver #####
- ==============================================================================
- [..] This driver provides functions to configure and program the FLASH memory
- of all STM32L4xx devices. It includes
- (#) Flash Memory Erase functions:
- (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
- HAL_FLASH_Lock() functions
- (++) Erase function: Erase page, erase all sectors
- (++) There are two modes of erase :
- (+++) Polling Mode using HAL_FLASHEx_Erase()
- (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
-
- (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to :
- (++) Set/Reset the write protection
- (++) Set the Read protection Level
- (++) Program the user Option Bytes
- (++) Configure the PCROP protection
-
- (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to :
- (++) Get the value of a write protection area
- (++) Know if the read protection is activated
- (++) Get the value of the user Option Bytes
- (++) Get the value of a PCROP area
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file in
- * the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup FLASHEx FLASHEx
- * @brief FLASH Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
- * @{
- */
-static void FLASH_MassErase(uint32_t Banks);
-static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);
-static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel);
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
-static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr);
-static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset);
-static uint32_t FLASH_OB_GetRDP(void);
-static uint32_t FLASH_OB_GetUser(void);
-static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr);
-/**
- * @}
- */
-
-/* Exported functions -------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
- * @{
- */
-
-/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
- * @brief Extended IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### Extended programming operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the Extended FLASH
- programming operations Operations.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Perform a mass erase or erase the specified FLASH memory pages.
- * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
- * contains the configuration information for the erasing.
- *
- * @param[out] PageError : pointer to variable that contains the configuration
- * information on faulty page in case of error (0xFFFFFFFF means that all
- * the pages have been correctly erased)
- *
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
-{
- HAL_StatusTypeDef status;
- uint32_t page_index;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if (status == HAL_OK)
- {
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* Deactivate the cache if they are activated to avoid data misbehavior */
- if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
- {
- if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
- {
- /* Disable data cache */
- __HAL_FLASH_DATA_CACHE_DISABLE();
- pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
- }
- else
- {
- pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
- }
- }
- else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
- {
- /* Disable data cache */
- __HAL_FLASH_DATA_CACHE_DISABLE();
- pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
- }
- else
- {
- pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
- }
-
- if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
- {
- /* Mass erase to be done */
- FLASH_MassErase(pEraseInit->Banks);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- /* If the erase operation is completed, disable the MER1 and MER2 Bits */
- CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
-#else
- /* If the erase operation is completed, disable the MER1 Bit */
- CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1));
-#endif
- }
- else
- {
- /*Initialization of PageError variable*/
- *PageError = 0xFFFFFFFFU;
-
- for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
- {
- FLASH_PageErase(page_index, pEraseInit->Banks);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the PER Bit */
- CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
-
- if (status != HAL_OK)
- {
- /* In case of error, stop erase procedure and return the faulty address */
- *PageError = page_index;
- break;
- }
- }
- }
-
- /* Flush the caches to be sure of the data consistency */
- FLASH_FlushCaches();
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-
-/**
- * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
- * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
- * contains the configuration information for the erasing.
- *
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* Deactivate the cache if they are activated to avoid data misbehavior */
- if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
- {
- if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
- {
- /* Disable data cache */
- __HAL_FLASH_DATA_CACHE_DISABLE();
- pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
- }
- else
- {
- pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
- }
- }
- else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
- {
- /* Disable data cache */
- __HAL_FLASH_DATA_CACHE_DISABLE();
- pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
- }
- else
- {
- pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
- }
-
- /* Enable End of Operation and Error interrupts */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
-
- pFlash.Bank = pEraseInit->Banks;
-
- if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
- {
- /* Mass erase to be done */
- pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE;
- FLASH_MassErase(pEraseInit->Banks);
- }
- else
- {
- /* Erase by page to be done */
- pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE;
- pFlash.NbPagesToErase = pEraseInit->NbPages;
- pFlash.Page = pEraseInit->Page;
-
- /*Erase 1st page and wait for IT */
- FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);
- }
-
- return status;
-}
-
-/**
- * @brief Program Option bytes.
- * @param pOBInit pointer to an FLASH_OBInitStruct structure that
- * contains the configuration information for the programming.
- *
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
-
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* Write protection configuration */
- if((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U)
- {
- /* Configure of Write protection on the selected area */
- if(FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset) != HAL_OK)
- {
- status = HAL_ERROR;
- }
-
- }
-
- /* Read protection configuration */
- if((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
- {
- /* Configure the Read protection level */
- if(FLASH_OB_RDPConfig(pOBInit->RDPLevel) != HAL_OK)
- {
- status = HAL_ERROR;
- }
- }
-
- /* User Configuration */
- if((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
- {
- /* Configure the user option bytes */
- if(FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig) != HAL_OK)
- {
- status = HAL_ERROR;
- }
- }
-
- /* PCROP Configuration */
- if((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U)
- {
- if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr)
- {
- /* Configure the Proprietary code readout protection */
- if(FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr) != HAL_OK)
- {
- status = HAL_ERROR;
- }
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-
-/**
- * @brief Get the Option bytes configuration.
- * @param pOBInit pointer to an FLASH_OBInitStruct structure that contains the
- * configuration information.
- * @note The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate
- * which area is requested for the WRP and PCROP, else no information will be returned
- *
- * @retval None
- */
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
-{
- pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);
-
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) ||
- (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB))
-#else
- if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB))
-#endif
- {
- pOBInit->OptionType |= OPTIONBYTE_WRP;
- /* Get write protection on the selected area */
- FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
- }
-
- /* Get Read protection level */
- pOBInit->RDPLevel = FLASH_OB_GetRDP();
-
- /* Get the user option bytes */
- pOBInit->USERConfig = FLASH_OB_GetUser();
-
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- if((pOBInit->PCROPConfig == FLASH_BANK_1) || (pOBInit->PCROPConfig == FLASH_BANK_2))
-#else
- if(pOBInit->PCROPConfig == FLASH_BANK_1)
-#endif
- {
- pOBInit->OptionType |= OPTIONBYTE_PCROP;
- /* Get the Proprietary code readout protection */
- FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr));
- }
-}
-
-/**
- * @}
- */
-
-#if defined (FLASH_CFGR_LVEN)
-/** @defgroup FLASHEx_Exported_Functions_Group2 Extended specific configuration functions
- * @brief Extended specific configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Extended specific configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the Extended FLASH
- specific configurations.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configuration of the LVE pin of the Flash (managed by power controller
- * or forced to low in order to use an external SMPS)
- * @param ConfigLVE Configuration of the LVE pin,
- * This parameter can be one of the following values:
- * @arg FLASH_LVE_PIN_CTRL: LVE FLASH pin controlled by power controller
- * @arg FLASH_LVE_PIN_FORCED: LVE FLASH pin enforced to low (external SMPS used)
- *
- * @note Before enforcing the LVE pin to low, the SOC should be in low voltage
- * range 2 and the voltage VDD12 should be higher than 1.08V and SMPS is ON.
- *
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE)
-{
- HAL_StatusTypeDef status;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_FLASH_LVE_PIN(ConfigLVE));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if (status == HAL_OK)
- {
- /* Check that the voltage scaling is range 2 */
- if (HAL_PWREx_GetVoltageRange() == PWR_REGULATOR_VOLTAGE_SCALE2)
- {
- /* Configure the LVEN bit */
- MODIFY_REG(FLASH->CFGR, FLASH_CFGR_LVEN, ConfigLVE);
-
- /* Check that the bit has been correctly configured */
- if (READ_BIT(FLASH->CFGR, FLASH_CFGR_LVEN) != ConfigLVE)
- {
- status = HAL_ERROR;
- }
- }
- else
- {
- /* Not allow to force Flash LVE pin if not in voltage range 2 */
- status = HAL_ERROR;
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-
-/**
- * @}
- */
-#endif /* FLASH_CFGR_LVEN */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @addtogroup FLASHEx_Private_Functions
- * @{
- */
-/**
- * @brief Mass erase of FLASH memory.
- * @param Banks Banks to be erased
- * This parameter can be one of the following values:
- * @arg FLASH_BANK_1: Bank1 to be erased
- * @arg FLASH_BANK_2: Bank2 to be erased
- * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
- * @retval None
- */
-static void FLASH_MassErase(uint32_t Banks)
-{
-#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U)
-#endif
- {
- /* Check the parameters */
- assert_param(IS_FLASH_BANK(Banks));
-
- /* Set the Mass Erase Bit for the bank 1 if requested */
- if((Banks & FLASH_BANK_1) != 0U)
- {
- SET_BIT(FLASH->CR, FLASH_CR_MER1);
- }
-
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- /* Set the Mass Erase Bit for the bank 2 if requested */
- if((Banks & FLASH_BANK_2) != 0U)
- {
- SET_BIT(FLASH->CR, FLASH_CR_MER2);
- }
-#endif
- }
-#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- else
- {
- SET_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
- }
-#endif
-
- /* Proceed to erase all sectors */
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
-}
-
-/**
- * @brief Erase the specified FLASH memory page.
- * @param Page FLASH page to erase
- * This parameter must be a value between 0 and (max number of pages in the bank - 1)
- * @param Banks Bank(s) where the page will be erased
- * This parameter can be one of the following values:
- * @arg FLASH_BANK_1: Page in bank 1 to be erased
- * @arg FLASH_BANK_2: Page in bank 2 to be erased
- * @retval None
- */
-void FLASH_PageErase(uint32_t Page, uint32_t Banks)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_PAGE(Page));
-
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- if(READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)
- {
- CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
- }
- else
-#endif
- {
- assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
-
- if((Banks & FLASH_BANK_1) != 0U)
- {
- CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
- }
- else
- {
- SET_BIT(FLASH->CR, FLASH_CR_BKER);
- }
- }
-#else
- /* Prevent unused argument(s) compilation warning */
- UNUSED(Banks);
-#endif
-
- /* Proceed to erase the page */
- MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page & 0xFFU) << FLASH_CR_PNB_Pos));
- SET_BIT(FLASH->CR, FLASH_CR_PER);
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
-}
-
-/**
- * @brief Flush the instruction and data caches.
- * @retval None
- */
-void FLASH_FlushCaches(void)
-{
- FLASH_CacheTypeDef cache = pFlash.CacheToReactivate;
-
- /* Flush instruction cache */
- if((cache == FLASH_CACHE_ICACHE_ENABLED) ||
- (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
- {
- /* Disable instruction cache */
- __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
- /* Reset instruction cache */
- __HAL_FLASH_INSTRUCTION_CACHE_RESET();
- /* Enable instruction cache */
- __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
- }
-
- /* Flush data cache */
- if((cache == FLASH_CACHE_DCACHE_ENABLED) ||
- (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
- {
- /* Reset data cache */
- __HAL_FLASH_DATA_CACHE_RESET();
- /* Enable data cache */
- __HAL_FLASH_DATA_CACHE_ENABLE();
- }
-
- /* Reset internal variable */
- pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
-}
-
-/**
- * @brief Configure the write protection of the desired pages.
- *
- * @note When the memory read protection level is selected (RDP level = 1),
- * it is not possible to program or erase Flash memory if the CPU debug
- * features are connected (JTAG or single wire) or boot code is being
- * executed from RAM or System flash, even if WRP is not activated.
- * @note To configure the WRP options, the option lock bit OPTLOCK must be
- * cleared with the call of the HAL_FLASH_OB_Unlock() function.
- * @note To validate the WRP options, the option bytes must be reloaded
- * through the call of the HAL_FLASH_OB_Launch() function.
- *
- * @param WRPArea specifies the area to be configured.
- * This parameter can be one of the following values:
- * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
- * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
- * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply for STM32L43x/STM32L44x devices)
- * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply for STM32L43x/STM32L44x devices)
- *
- * @param WRPStartOffset specifies the start page of the write protected area
- * This parameter can be page number between 0 and (max number of pages in the bank - 1)
- *
- * @param WRDPEndOffset specifies the end page of the write protected area
- * This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1)
- *
- * @retval HAL Status
- */
-static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
-{
- HAL_StatusTypeDef status;
-
- /* Check the parameters */
- assert_param(IS_OB_WRPAREA(WRPArea));
- assert_param(IS_FLASH_PAGE(WRPStartOffset));
- assert_param(IS_FLASH_PAGE(WRDPEndOffset));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Configure the write protected area */
- if(WRPArea == OB_WRPAREA_BANK1_AREAA)
- {
- MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END),
- (WRPStartOffset | (WRDPEndOffset << 16)));
- }
- else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
- {
- MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END),
- (WRPStartOffset | (WRDPEndOffset << 16)));
- }
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
- {
- MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END),
- (WRPStartOffset | (WRDPEndOffset << 16)));
- }
- else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
- {
- MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END),
- (WRPStartOffset | (WRDPEndOffset << 16)));
- }
-#endif
- else
- {
- /* Nothing to do */
- }
-
- /* Set OPTSTRT Bit */
- SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the option byte program operation is completed, disable the OPTSTRT Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
- }
-
- return status;
-}
-
-/**
- * @brief Set the read protection level.
- *
- * @note To configure the RDP level, the option lock bit OPTLOCK must be
- * cleared with the call of the HAL_FLASH_OB_Unlock() function.
- * @note To validate the RDP level, the option bytes must be reloaded
- * through the call of the HAL_FLASH_OB_Launch() function.
- * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible
- * to go back to level 1 or 0 !!!
- *
- * @param RDPLevel specifies the read protection level.
- * This parameter can be one of the following values:
- * @arg OB_RDP_LEVEL_0: No protection
- * @arg OB_RDP_LEVEL_1: Read protection of the memory
- * @arg OB_RDP_LEVEL_2: Full chip protection
- *
- * @retval HAL status
- */
-static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel)
-{
- HAL_StatusTypeDef status;
-
- /* Check the parameters */
- assert_param(IS_OB_RDP_LEVEL(RDPLevel));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Configure the RDP level in the option bytes register */
- MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);
-
- /* Set OPTSTRT Bit */
- SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the option byte program operation is completed, disable the OPTSTRT Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
- }
-
- return status;
-}
-
-/**
- * @brief Program the FLASH User Option Byte.
- *
- * @note To configure the user option bytes, the option lock bit OPTLOCK must
- * be cleared with the call of the HAL_FLASH_OB_Unlock() function.
- * @note To validate the user option bytes, the option bytes must be reloaded
- * through the call of the HAL_FLASH_OB_Launch() function.
- *
- * @param UserType The FLASH User Option Bytes to be modified
- * @param UserConfig The FLASH User Option Bytes values:
- * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), IWDG_SW(Bit16),
- * IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), BFB2(Bit20),
- * DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25).
- *
- * @retval HAL status
- */
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
-{
- uint32_t optr_reg_val = 0;
- uint32_t optr_reg_mask = 0;
- HAL_StatusTypeDef status;
-
- /* Check the parameters */
- assert_param(IS_OB_USER_TYPE(UserType));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- if((UserType & OB_USER_BOR_LEV) != 0U)
- {
- /* BOR level option byte should be modified */
- assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));
-
- /* Set value and mask for BOR level option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);
- optr_reg_mask |= FLASH_OPTR_BOR_LEV;
- }
-
- if((UserType & OB_USER_nRST_STOP) != 0U)
- {
- /* nRST_STOP option byte should be modified */
- assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));
-
- /* Set value and mask for nRST_STOP option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);
- optr_reg_mask |= FLASH_OPTR_nRST_STOP;
- }
-
- if((UserType & OB_USER_nRST_STDBY) != 0U)
- {
- /* nRST_STDBY option byte should be modified */
- assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));
-
- /* Set value and mask for nRST_STDBY option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);
- optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
- }
-
- if((UserType & OB_USER_nRST_SHDW) != 0U)
- {
- /* nRST_SHDW option byte should be modified */
- assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));
-
- /* Set value and mask for nRST_SHDW option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);
- optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
- }
-
- if((UserType & OB_USER_IWDG_SW) != 0U)
- {
- /* IWDG_SW option byte should be modified */
- assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));
-
- /* Set value and mask for IWDG_SW option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);
- optr_reg_mask |= FLASH_OPTR_IWDG_SW;
- }
-
- if((UserType & OB_USER_IWDG_STOP) != 0U)
- {
- /* IWDG_STOP option byte should be modified */
- assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));
-
- /* Set value and mask for IWDG_STOP option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);
- optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
- }
-
- if((UserType & OB_USER_IWDG_STDBY) != 0U)
- {
- /* IWDG_STDBY option byte should be modified */
- assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));
-
- /* Set value and mask for IWDG_STDBY option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);
- optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
- }
-
- if((UserType & OB_USER_WWDG_SW) != 0U)
- {
- /* WWDG_SW option byte should be modified */
- assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));
-
- /* Set value and mask for WWDG_SW option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);
- optr_reg_mask |= FLASH_OPTR_WWDG_SW;
- }
-
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- if((UserType & OB_USER_BFB2) != 0U)
- {
- /* BFB2 option byte should be modified */
- assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2));
-
- /* Set value and mask for BFB2 option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2);
- optr_reg_mask |= FLASH_OPTR_BFB2;
- }
-
- if((UserType & OB_USER_DUALBANK) != 0U)
- {
-#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- /* DUALBANK option byte should be modified */
- assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DB1M));
-
- /* Set value and mask for DUALBANK option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_DB1M);
- optr_reg_mask |= FLASH_OPTR_DB1M;
-#else
- /* DUALBANK option byte should be modified */
- assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK));
-
- /* Set value and mask for DUALBANK option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK);
- optr_reg_mask |= FLASH_OPTR_DUALBANK;
-#endif
- }
-#endif
-
- if((UserType & OB_USER_nBOOT1) != 0U)
- {
- /* nBOOT1 option byte should be modified */
- assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1));
-
- /* Set value and mask for nBOOT1 option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1);
- optr_reg_mask |= FLASH_OPTR_nBOOT1;
- }
-
- if((UserType & OB_USER_SRAM2_PE) != 0U)
- {
- /* SRAM2_PE option byte should be modified */
- assert_param(IS_OB_USER_SRAM2_PARITY(UserConfig & FLASH_OPTR_SRAM2_PE));
-
- /* Set value and mask for SRAM2_PE option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_PE);
- optr_reg_mask |= FLASH_OPTR_SRAM2_PE;
- }
-
- if((UserType & OB_USER_SRAM2_RST) != 0U)
- {
- /* SRAM2_RST option byte should be modified */
- assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST));
-
- /* Set value and mask for SRAM2_RST option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST);
- optr_reg_mask |= FLASH_OPTR_SRAM2_RST;
- }
-
-#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \
- defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- if((UserType & OB_USER_nSWBOOT0) != 0U)
- {
- /* nSWBOOT0 option byte should be modified */
- assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0));
-
- /* Set value and mask for nSWBOOT0 option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0);
- optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
- }
-
- if((UserType & OB_USER_nBOOT0) != 0U)
- {
- /* nBOOT0 option byte should be modified */
- assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0));
-
- /* Set value and mask for nBOOT0 option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0);
- optr_reg_mask |= FLASH_OPTR_nBOOT0;
- }
-#endif
-
- /* Configure the option bytes register */
- MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);
-
- /* Set OPTSTRT Bit */
- SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the option byte program operation is completed, disable the OPTSTRT Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
- }
-
- return status;
-}
-
-/**
- * @brief Configure the Proprietary code readout protection of the desired addresses.
- *
- * @note To configure the PCROP options, the option lock bit OPTLOCK must be
- * cleared with the call of the HAL_FLASH_OB_Unlock() function.
- * @note To validate the PCROP options, the option bytes must be reloaded
- * through the call of the HAL_FLASH_OB_Launch() function.
- *
- * @param PCROPConfig specifies the configuration (Bank to be configured and PCROP_RDP option).
- * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2
- * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
- *
- * @param PCROPStartAddr specifies the start address of the Proprietary code readout protection
- * This parameter can be an address between begin and end of the bank
- *
- * @param PCROPEndAddr specifies the end address of the Proprietary code readout protection
- * This parameter can be an address between PCROPStartAddr and end of the bank
- *
- * @retval HAL Status
- */
-static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr)
-{
- HAL_StatusTypeDef status;
- uint32_t reg_value;
- uint32_t bank1_addr;
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- uint32_t bank2_addr;
-#endif
-
- /* Check the parameters */
- assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH));
- assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
- assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr));
- assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- /* Get the information about the bank swapping */
- if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U)
- {
- bank1_addr = FLASH_BASE;
- bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
- }
- else
- {
- bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
- bank2_addr = FLASH_BASE;
- }
-#else
- bank1_addr = FLASH_BASE;
-#endif
-
-#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)
- {
- /* Configure the Proprietary code readout protection */
- if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)
- {
- reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4);
- MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
-
- reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4);
- MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
- }
- else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)
- {
- reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4);
- MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
-
- reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4);
- MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
- }
- else
- {
- /* Nothing to do */
- }
- }
- else
-#endif
- {
- /* Configure the Proprietary code readout protection */
- if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)
- {
- reg_value = ((PCROPStartAddr - bank1_addr) >> 3);
- MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
-
- reg_value = ((PCROPEndAddr - bank1_addr) >> 3);
- MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
- }
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)
- {
- reg_value = ((PCROPStartAddr - bank2_addr) >> 3);
- MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
-
- reg_value = ((PCROPEndAddr - bank2_addr) >> 3);
- MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
- }
-#endif
- else
- {
- /* Nothing to do */
- }
- }
-
- MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
-
- /* Set OPTSTRT Bit */
- SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the option byte program operation is completed, disable the OPTSTRT Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
- }
-
- return status;
-}
-
-/**
- * @brief Return the FLASH Write Protection Option Bytes value.
- *
- * @param[in] WRPArea: specifies the area to be returned.
- * This parameter can be one of the following values:
- * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
- * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
- * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32L43x/STM32L44x devices)
- * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32L43x/STM32L44x devices)
- *
- * @param[out] WRPStartOffset: specifies the address where to copied the start page
- * of the write protected area
- *
- * @param[out] WRDPEndOffset: specifies the address where to copied the end page of
- * the write protected area
- *
- * @retval None
- */
-static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset)
-{
- /* Get the configuration of the write protected area */
- if(WRPArea == OB_WRPAREA_BANK1_AREAA)
- {
- *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);
- *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> 16);
- }
- else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
- {
- *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
- *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> 16);
- }
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
- {
- *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT);
- *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> 16);
- }
- else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
- {
- *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT);
- *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> 16);
- }
-#endif
- else
- {
- /* Nothing to do */
- }
-}
-
-/**
- * @brief Return the FLASH Read Protection level.
- * @retval FLASH ReadOut Protection Status:
- * This return value can be one of the following values:
- * @arg OB_RDP_LEVEL_0: No protection
- * @arg OB_RDP_LEVEL_1: Read protection of the memory
- * @arg OB_RDP_LEVEL_2: Full chip protection
- */
-static uint32_t FLASH_OB_GetRDP(void)
-{
- uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP);
-
- if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2))
- {
- return (OB_RDP_LEVEL_1);
- }
- else
- {
- return (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP));
- }
-}
-
-/**
- * @brief Return the FLASH User Option Byte value.
- * @retval The FLASH User Option Bytes values:
- * For STM32L47x/STM32L48x devices :
- * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14),
- * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),
- * BFB2(Bit20), DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25).
- * For STM32L43x/STM32L44x devices :
- * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14),
- * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),
- * nBOOT1(Bit23), SRAM2_PE(Bit24), SRAM2_RST(Bit25), nSWBOOT0(Bit26) and nBOOT0(Bit27).
- */
-static uint32_t FLASH_OB_GetUser(void)
-{
- uint32_t user_config = READ_REG(FLASH->OPTR);
- CLEAR_BIT(user_config, FLASH_OPTR_RDP);
-
- return user_config;
-}
-
-/**
- * @brief Return the FLASH Write Protection Option Bytes value.
- *
- * @param PCROPConfig [inout]: specifies the configuration (Bank to be configured and PCROP_RDP option).
- * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2
- * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
- *
- * @param PCROPStartAddr [out]: specifies the address where to copied the start address
- * of the Proprietary code readout protection
- *
- * @param PCROPEndAddr [out]: specifies the address where to copied the end address of
- * the Proprietary code readout protection
- *
- * @retval None
- */
-static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr)
-{
- uint32_t reg_value;
- uint32_t bank1_addr;
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- uint32_t bank2_addr;
-#endif
-
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- /* Get the information about the bank swapping */
- if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U)
- {
- bank1_addr = FLASH_BASE;
- bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
- }
- else
- {
- bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
- bank2_addr = FLASH_BASE;
- }
-#else
- bank1_addr = FLASH_BASE;
-#endif
-
-#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)
- {
- if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)
- {
- reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
- *PCROPStartAddr = (reg_value << 4) + FLASH_BASE;
-
- reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
- *PCROPEndAddr = (reg_value << 4) + FLASH_BASE + 0xFU;
- }
- else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)
- {
- reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
- *PCROPStartAddr = (reg_value << 4) + FLASH_BASE;
-
- reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
- *PCROPEndAddr = (reg_value << 4) + FLASH_BASE + 0xFU;;
- }
- else
- {
- /* Nothing to do */
- }
- }
- else
-#endif
- {
- if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)
- {
- reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
- *PCROPStartAddr = (reg_value << 3) + bank1_addr;
-
- reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
- *PCROPEndAddr = (reg_value << 3) + bank1_addr + 0x7U;
- }
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
- defined (STM32L496xx) || defined (STM32L4A6xx) || \
- defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
- else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)
- {
- reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
- *PCROPStartAddr = (reg_value << 3) + bank2_addr;
-
- reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
- *PCROPEndAddr = (reg_value << 3) + bank2_addr + 0x7U;
- }
-#endif
- else
- {
- /* Nothing to do */
- }
- }
-
- *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP);
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c
deleted file mode 100644
index 82599f9..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_flash_ramfunc.c
- * @author MCD Application Team
- * @brief FLASH RAMFUNC driver.
- * This file provides a Flash firmware functions which should be
- * executed from internal SRAM
- * + FLASH HalfPage Programming
- * + FLASH Power Down in Run mode
- *
- * @verbatim
- ==============================================================================
- ##### Flash RAM functions #####
- ==============================================================================
-
- *** ARM Compiler ***
- --------------------
- [..] RAM functions are defined using the toolchain options.
- Functions that are executed in RAM should reside in a separate
- source module. Using the 'Options for File' dialog you can simply change
- the 'Code / Const' area of a module to a memory space in physical RAM.
- Available memory areas are declared in the 'Target' tab of the
- Options for Target' dialog.
-
- *** ICCARM Compiler ***
- -----------------------
- [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
-
- *** GNU Compiler ***
- --------------------
- [..] RAM functions are defined using a specific toolchain attribute
- "__attribute__((section(".RamFunc")))".
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file in
- * the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
- * @brief FLASH functions executed from RAM
- * @{
- */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions -------------------------------------------------------*/
-
-/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH in RAM function Exported Functions
- * @{
- */
-
-/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### ramfunc functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions that should be executed from RAM.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enable the Power down in Run Mode
- * @note This function should be called and executed from SRAM memory
- * @retval HAL status
- */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void)
-{
- /* Enable the Power Down in Run mode*/
- __HAL_FLASH_POWER_DOWN_ENABLE();
-
- return HAL_OK;
-
-}
-
-/**
- * @brief Disable the Power down in Run Mode
- * @note This function should be called and executed from SRAM memory
- * @retval HAL status
- */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void)
-{
- /* Disable the Power Down in Run mode*/
- __HAL_FLASH_POWER_DOWN_DISABLE();
-
- return HAL_OK;
-}
-
-#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-/**
- * @brief Program the FLASH DBANK User Option Byte.
- *
- * @note To configure the user option bytes, the option lock bit OPTLOCK must
- * be cleared with the call of the HAL_FLASH_OB_Unlock() function.
- * @note To modify the DBANK option byte, no PCROP region should be defined.
- * To deactivate PCROP, user should perform RDP changing
- *
- * @param DBankConfig The FLASH DBANK User Option Byte value.
- * This parameter can be one of the following values:
- * @arg OB_DBANK_128_BITS: Single-bank with 128-bits data
- * @arg OB_DBANK_64_BITS: Dual-bank with 64-bits data
- *
- * @retval HAL status
- */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig)
-{
- uint32_t count, reg;
- HAL_StatusTypeDef status = HAL_ERROR;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check if the PCROP is disabled */
- reg = FLASH->PCROP1SR;
- if (reg > FLASH->PCROP1ER)
- {
- reg = FLASH->PCROP2SR;
- if (reg > FLASH->PCROP2ER)
- {
- /* Disable Flash prefetch */
- __HAL_FLASH_PREFETCH_BUFFER_DISABLE();
-
- if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
- {
- /* Disable Flash instruction cache */
- __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
-
- /* Flush Flash instruction cache */
- __HAL_FLASH_INSTRUCTION_CACHE_RESET();
- }
-
- if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
- {
- /* Disable Flash data cache */
- __HAL_FLASH_DATA_CACHE_DISABLE();
-
- /* Flush Flash data cache */
- __HAL_FLASH_DATA_CACHE_RESET();
- }
-
- /* Disable WRP zone 1 of 1st bank if needed */
- reg = FLASH->WRP1AR;
- if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> FLASH_WRP1AR_WRP1A_STRT_Pos) <=
- ((reg & FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos))
- {
- MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_STRT);
- }
-
- /* Disable WRP zone 2 of 1st bank if needed */
- reg = FLASH->WRP1BR;
- if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> FLASH_WRP1BR_WRP1B_STRT_Pos) <=
- ((reg & FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos))
- {
- MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_STRT);
- }
-
- /* Disable WRP zone 1 of 2nd bank if needed */
- reg = FLASH->WRP2AR;
- if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> FLASH_WRP2AR_WRP2A_STRT_Pos) <=
- ((reg & FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos))
- {
- MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_STRT);
- }
-
- /* Disable WRP zone 2 of 2nd bank if needed */
- reg = FLASH->WRP2BR;
- if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> FLASH_WRP2BR_WRP2B_STRT_Pos) <=
- ((reg & FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos))
- {
- MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_STRT);
- }
-
- /* Modify the DBANK user option byte */
- MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig);
-
- /* Set OPTSTRT Bit */
- SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-
- /* Wait for last operation to be completed */
- /* 8 is the number of required instruction cycles for the below loop statement (timeout expressed in ms) */
- count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8U / 1000U);
- do
- {
- if (count == 0U)
- {
- break;
- }
- count--;
- } while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET);
-
- /* If the option byte program operation is completed, disable the OPTSTRT Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
-
- /* Set the bit to force the option byte reloading */
- SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-
-
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c
deleted file mode 100644
index 6ba7d60..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c
+++ /dev/null
@@ -1,551 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_gpio.c
- * @author MCD Application Team
- * @brief GPIO HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the General Purpose Input/Output (GPIO) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### GPIO Peripheral features #####
- ==============================================================================
- [..]
- (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
- configured by software in several modes:
- (++) Input mode
- (++) Analog mode
- (++) Output mode
- (++) Alternate function mode
- (++) External interrupt/event lines
-
- (+) During and just after reset, the alternate functions and external interrupt
- lines are not active and the I/O ports are configured in input floating mode.
-
- (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
- activated or not.
-
- (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
- type and the IO speed can be selected depending on the VDD value.
-
- (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
- multiplexer that allows only one peripheral alternate function (AF) connected
- to an IO pin at a time. In this way, there can be no conflict between peripherals
- sharing the same IO pin.
-
- (+) All ports have external interrupt/event capability. To use external interrupt
- lines, the port must be configured in input mode. All available GPIO pins are
- connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
-
- (+) The external interrupt/event controller consists of up to 39 edge detectors
- (16 lines are connected to GPIO) for generating event/interrupt requests (each
- input line can be independently configured to select the type (interrupt or event)
- and the corresponding trigger event (rising or falling or both). Each line can
- also be masked independently.
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
-
- (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
- (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
- (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
- structure.
- (++) In case of Output or alternate function mode selection: the speed is
- configured through "Speed" member from GPIO_InitTypeDef structure.
- (++) In alternate mode is selection, the alternate function connected to the IO
- is configured through "Alternate" member from GPIO_InitTypeDef structure.
- (++) Analog mode is required when a pin is to be used as ADC channel
- or DAC output.
- (++) In case of external interrupt/event selection the "Mode" member from
- GPIO_InitTypeDef structure select the type (interrupt or event) and
- the corresponding trigger event (rising or falling or both).
-
- (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
- mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
- HAL_NVIC_EnableIRQ().
-
- (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
-
- (#) To set/reset the level of a pin configured in output mode use
- HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
-
- (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
-
- (#) During and just after reset, the alternate functions are not
- active and the GPIO pins are configured in input floating mode (except JTAG
- pins).
-
- (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
- (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
- priority over the GPIO function.
-
- (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
- general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
- The HSE has priority over the GPIO function.
-
- @endverbatim
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup GPIO GPIO
- * @brief GPIO HAL module driver
- * @{
- */
-/** MISRA C:2012 deviation rule has been granted for following rules:
- * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
- * range of the shift operator in following API :
- * HAL_GPIO_Init
- * HAL_GPIO_DeInit
- */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @addtogroup GPIO_Private_Defines GPIO Private Defines
- * @{
- */
-#define GPIO_NUMBER (16u)
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
- * @{
- */
-
-/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
- * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
- * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
- * the configuration information for the specified GPIO peripheral.
- * @retval None
- */
-void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
- uint32_t position = 0x00u;
- uint32_t iocurrent;
- uint32_t temp;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
- assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
-
- /* Configure the port pins */
- while (((GPIO_Init->Pin) >> position) != 0x00u)
- {
- /* Get current io position */
- iocurrent = (GPIO_Init->Pin) & (1uL << position);
-
- if (iocurrent != 0x00u)
- {
- /*--------------------- GPIO Mode Configuration ------------------------*/
- /* In case of Output or Alternate function mode selection */
- if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
- {
- /* Check the Speed parameter */
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
-
- /* Configure the IO Speed */
- temp = GPIOx->OSPEEDR;
- temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
- temp |= (GPIO_Init->Speed << (position * 2u));
- GPIOx->OSPEEDR = temp;
-
- /* Configure the IO Output Type */
- temp = GPIOx->OTYPER;
- temp &= ~(GPIO_OTYPER_OT0 << position) ;
- temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
- GPIOx->OTYPER = temp;
- }
-
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
-
- /* In case of Analog mode, check if ADC control mode is selected */
- if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
- {
- /* Configure the IO Output Type */
- temp = GPIOx->ASCR;
- temp &= ~(GPIO_ASCR_ASC0 << position) ;
- temp |= (((GPIO_Init->Mode & GPIO_MODE_ANALOG_ADC_CONTROL) >> 3) << position);
- GPIOx->ASCR = temp;
- }
-
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
-
- /* Activate the Pull-up or Pull down resistor for the current IO */
- if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
- {
- /* Check the Pull parameter */
- assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
-
- temp = GPIOx->PUPDR;
- temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
- temp |= ((GPIO_Init->Pull) << (position * 2U));
- GPIOx->PUPDR = temp;
- }
-
- /* In case of Alternate function mode selection */
- if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
- {
- /* Check the Alternate function parameters */
- assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
- assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
- /* Configure Alternate function mapped with the current IO */
- temp = GPIOx->AFR[position >> 3u];
- temp &= ~(0xFu << ((position & 0x07u) * 4u));
- temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
- GPIOx->AFR[position >> 3u] = temp;
- }
-
- /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
- temp = GPIOx->MODER;
- temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
- temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
- GPIOx->MODER = temp;
-
- /*--------------------- EXTI Mode Configuration ------------------------*/
- /* Configure the External Interrupt or event for the current IO */
- if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
- {
- /* Enable SYSCFG Clock */
- __HAL_RCC_SYSCFG_CLK_ENABLE();
-
- temp = SYSCFG->EXTICR[position >> 2u];
- temp &= ~(0x0FuL << (4u * (position & 0x03u)));
- temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
- SYSCFG->EXTICR[position >> 2u] = temp;
-
- /* Clear Rising Falling edge configuration */
- temp = EXTI->RTSR1;
- temp &= ~(iocurrent);
- if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
- {
- temp |= iocurrent;
- }
- EXTI->RTSR1 = temp;
-
- temp = EXTI->FTSR1;
- temp &= ~(iocurrent);
- if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
- {
- temp |= iocurrent;
- }
- EXTI->FTSR1 = temp;
-
- /* Clear EXTI line configuration */
- temp = EXTI->EMR1;
- temp &= ~(iocurrent);
- if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
- {
- temp |= iocurrent;
- }
- EXTI->EMR1 = temp;
-
- temp = EXTI->IMR1;
- temp &= ~(iocurrent);
- if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
- {
- temp |= iocurrent;
- }
- EXTI->IMR1 = temp;
- }
- }
-
- position++;
- }
-}
-
-/**
- * @brief De-initialize the GPIOx peripheral registers to their default reset values.
- * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
- * @param GPIO_Pin specifies the port bit to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
-{
- uint32_t position = 0x00u;
- uint32_t iocurrent;
- uint32_t tmp;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- /* Configure the port pins */
- while ((GPIO_Pin >> position) != 0x00u)
- {
- /* Get current io position */
- iocurrent = (GPIO_Pin) & (1uL << position);
-
- if (iocurrent != 0x00u)
- {
- /*------------------------- EXTI Mode Configuration --------------------*/
- /* Clear the External Interrupt or Event for the current IO */
-
- tmp = SYSCFG->EXTICR[position >> 2u];
- tmp &= (0x0FuL << (4u * (position & 0x03u)));
- if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
- {
- /* Clear EXTI line configuration */
- EXTI->IMR1 &= ~(iocurrent);
- EXTI->EMR1 &= ~(iocurrent);
-
- /* Clear Rising Falling edge configuration */
- EXTI->FTSR1 &= ~(iocurrent);
- EXTI->RTSR1 &= ~(iocurrent);
-
- tmp = 0x0FuL << (4u * (position & 0x03u));
- SYSCFG->EXTICR[position >> 2u] &= ~tmp;
- }
-
- /*------------------------- GPIO Mode Configuration --------------------*/
- /* Configure IO in Analog Mode */
- GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));
-
- /* Configure the default Alternate Function in current IO */
- GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ;
-
- /* Configure the default value for IO Speed */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
-
- /* Configure the default value IO Output Type */
- GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
-
- /* Deactivate the Pull-up and Pull-down resistor for the current IO */
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
-
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
- /* Deactivate the Control bit of Analog mode for the current IO */
- GPIOx->ASCR &= ~(GPIO_ASCR_ASC0<< position);
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
- }
-
- position++;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
- * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Read the specified input port pin.
- * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
- * @param GPIO_Pin specifies the port bit to read.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval The input port pin value.
- */
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- GPIO_PinState bitstatus;
-
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->IDR & GPIO_Pin) != 0x00u)
- {
- bitstatus = GPIO_PIN_SET;
- }
- else
- {
- bitstatus = GPIO_PIN_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Set or clear the selected data port bit.
- *
- * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
- * accesses. In this way, there is no risk of an IRQ occurring between
- * the read and the modify access.
- *
- * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
- * @param GPIO_Pin specifies the port bit to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @param PinState specifies the value to be written to the selected bit.
- * This parameter can be one of the GPIO_PinState enum values:
- * @arg GPIO_PIN_RESET: to clear the port pin
- * @arg GPIO_PIN_SET: to set the port pin
- * @retval None
- */
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_PIN_ACTION(PinState));
-
- if(PinState != GPIO_PIN_RESET)
- {
- GPIOx->BSRR = (uint32_t)GPIO_Pin;
- }
- else
- {
- GPIOx->BRR = (uint32_t)GPIO_Pin;
- }
-}
-
-/**
- * @brief Toggle the specified GPIO pin.
- * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
- * @param GPIO_Pin specifies the pin to be toggled.
- * @retval None
- */
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint32_t odr;
-
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- /* get current Output Data Register value */
- odr = GPIOx->ODR;
-
- /* Set selected pins that were at low level, and reset ones that were high */
- GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
-}
-
-/**
-* @brief Lock GPIO Pins configuration registers.
- * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
- * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
- * @note The configuration of the locked GPIO pins can no longer be modified
- * until the next reset.
- * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
- * @param GPIO_Pin specifies the port bits to be locked.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- __IO uint32_t tmp = GPIO_LCKR_LCKK;
-
- /* Check the parameters */
- assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- /* Apply lock key write sequence */
- tmp |= GPIO_Pin;
- /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
- GPIOx->LCKR = tmp;
- /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
- GPIOx->LCKR = GPIO_Pin;
- /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
- GPIOx->LCKR = tmp;
- /* Read LCKK register. This read is mandatory to complete key lock sequence */
- tmp = GPIOx->LCKR;
-
- /* Read again in order to confirm lock is active */
- if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
- {
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Handle EXTI interrupt request.
- * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
- * @retval None
- */
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
-{
- /* EXTI line interrupt detected */
- if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
- {
- __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
- HAL_GPIO_EXTI_Callback(GPIO_Pin);
- }
-}
-
-/**
- * @brief EXTI line detection callback.
- * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
- * @retval None
- */
-__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(GPIO_Pin);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_GPIO_EXTI_Callback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-#endif /* HAL_GPIO_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c
deleted file mode 100644
index 4fa5c10..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c
+++ /dev/null
@@ -1,6884 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_i2c.c
- * @author MCD Application Team
- * @brief I2C HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Inter Integrated Circuit (I2C) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State and Errors functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The I2C HAL driver can be used as follows:
-
- (#) Declare a I2C_HandleTypeDef handle structure, for example:
- I2C_HandleTypeDef hi2c;
-
- (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
- (##) Enable the I2Cx interface clock
- (##) I2C pins configuration
- (+++) Enable the clock for the I2C GPIOs
- (+++) Configure I2C pins as alternate function open-drain
- (##) NVIC configuration if you need to use interrupt process
- (+++) Configure the I2Cx interrupt priority
- (+++) Enable the NVIC I2C IRQ Channel
- (##) DMA Configuration if you need to use DMA process
- (+++) Declare a DMA_HandleTypeDef handle structure for
- the transmit or receive channel
- (+++) Enable the DMAx interface clock using
- (+++) Configure the DMA handle parameters
- (+++) Configure the DMA Tx or Rx channel
- (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
- the DMA Tx or Rx channel
-
- (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
- Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
-
- (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
- (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
-
- (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
-
- (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
- (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
- (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
- (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
-
- *** Polling mode IO MEM operation ***
- =====================================
- [..]
- (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
- (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
-
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
- (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
- add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
- (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
- (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
- add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
- (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
- add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
- (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
- (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
- add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
- add their own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
- add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
- This action will inform Master to generate a Stop condition to discard the communication.
-
-
- *** Interrupt mode or DMA mode IO sequential operation ***
- ==========================================================
- [..]
- (@) These interfaces allow to manage a sequential transfer with a repeated start condition
- when a direction change during transfer
- [..]
- (+) A specific option field manage the different steps of a sequential transfer
- (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
- (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
- no sequential mode
- (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
- and data to transfer without a final stop condition
- (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
- start condition, address and data to transfer without a final stop condition,
- an then permit a call the same master sequential interface several times
- (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
- or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
- (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
- and with new data to transfer if the direction change or manage only the new data to
- transfer
- if no direction change and without a final stop condition in both cases
- (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
- and with new data to transfer if the direction change or manage only the new data to
- transfer
- if no direction change and with a final stop condition in both cases
- (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
- after several call of the same master sequential interface several times
- (link with option I2C_FIRST_AND_NEXT_FRAME).
- Usage can, transfer several bytes one by one using
- HAL_I2C_Master_Seq_Transmit_IT
- or HAL_I2C_Master_Seq_Receive_IT
- or HAL_I2C_Master_Seq_Transmit_DMA
- or HAL_I2C_Master_Seq_Receive_DMA
- with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
- Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
- Receive sequence permit to call the opposite interface Receive or Transmit
- without stopping the communication and so generate a restart condition.
- (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
- each call of the same master sequential
- interface.
- Usage can, transfer several bytes one by one with a restart with slave address between
- each bytes using
- HAL_I2C_Master_Seq_Transmit_IT
- or HAL_I2C_Master_Seq_Receive_IT
- or HAL_I2C_Master_Seq_Transmit_DMA
- or HAL_I2C_Master_Seq_Receive_DMA
- with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
- Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
- generation of STOP condition.
-
- (+) Different sequential I2C interfaces are listed below:
- (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
- HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
- (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
- users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
- (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
- HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
- (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
- add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
- add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
- HAL_I2C_DisableListen_IT()
- (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
- add their own code to check the Address Match Code and the transmission direction request by master
- (Write/Read).
- (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
- add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
- (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
- HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
- (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
- users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
- (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
- HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
- (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
- add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
- (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
- add their own code by customization of function pointer HAL_I2C_ErrorCallback()
- (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
- This action will inform Master to generate a Stop condition to discard the communication.
-
- *** Interrupt mode IO MEM operation ***
- =======================================
- [..]
- (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
- HAL_I2C_Mem_Write_IT()
- (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
- add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
- (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
- HAL_I2C_Mem_Read_IT()
- (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
- add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
- add their own code by customization of function pointer HAL_I2C_ErrorCallback()
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Master_Transmit_DMA()
- (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
- add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
- (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Master_Receive_DMA()
- (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
- add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Slave_Transmit_DMA()
- (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
- add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
- (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Slave_Receive_DMA()
- (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
- add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
- add their own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
- add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
- This action will inform Master to generate a Stop condition to discard the communication.
-
- *** DMA mode IO MEM operation ***
- =================================
- [..]
- (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
- HAL_I2C_Mem_Write_DMA()
- (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
- add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
- (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
- HAL_I2C_Mem_Read_DMA()
- (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
- add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
- add their own code by customization of function pointer HAL_I2C_ErrorCallback()
-
-
- *** I2C HAL driver macros list ***
- ==================================
- [..]
- Below the list of most used macros in I2C HAL driver.
-
- (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
- (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
- (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
- (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
- (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
- (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
- (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
-
- *** Callback registration ***
- =============================================
- [..]
- The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
- allows the user to configure dynamically the driver callbacks.
- Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
- to register an interrupt callback.
- [..]
- Function HAL_I2C_RegisterCallback() allows to register following callbacks:
- (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
- (+) MasterRxCpltCallback : callback for Master reception end of transfer.
- (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
- (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
- (+) ListenCpltCallback : callback for end of listen mode.
- (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
- (+) MemRxCpltCallback : callback for Memory reception end of transfer.
- (+) ErrorCallback : callback for error detection.
- (+) AbortCpltCallback : callback for abort completion process.
- (+) MspInitCallback : callback for Msp Init.
- (+) MspDeInitCallback : callback for Msp DeInit.
- This function takes as parameters the HAL peripheral handle, the Callback ID
- and a pointer to the user callback function.
- [..]
- For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
- [..]
- Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
- weak function.
- HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
- and the Callback ID.
- This function allows to reset following callbacks:
- (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
- (+) MasterRxCpltCallback : callback for Master reception end of transfer.
- (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
- (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
- (+) ListenCpltCallback : callback for end of listen mode.
- (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
- (+) MemRxCpltCallback : callback for Memory reception end of transfer.
- (+) ErrorCallback : callback for error detection.
- (+) AbortCpltCallback : callback for abort completion process.
- (+) MspInitCallback : callback for Msp Init.
- (+) MspDeInitCallback : callback for Msp DeInit.
- [..]
- For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
- [..]
- By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
- all callbacks are set to the corresponding weak functions:
- examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
- Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
- these callbacks are null (not registered beforehand).
- If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
- keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
- [..]
- Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
- Exception done MspInit/MspDeInit functions that can be registered/unregistered
- in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
- thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
- Then, the user first registers the MspInit/MspDeInit user callbacks
- using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
- or HAL_I2C_Init() function.
- [..]
- When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registration feature is not available and all callbacks
- are set to the corresponding weak functions.
-
- [..]
- (@) You can refer to the I2C HAL driver header file for more useful macros
-
- @endverbatim
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup I2C I2C
- * @brief I2C HAL module driver
- * @{
- */
-
-#ifdef HAL_I2C_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup I2C_Private_Define I2C Private Define
- * @{
- */
-#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
-#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
-#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
-#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
-#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
-#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
-#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
-#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
-#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
-#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
-
-#define MAX_NBYTE_SIZE 255U
-#define SLAVE_ADDR_SHIFT 7U
-#define SLAVE_ADDR_MSK 0x06U
-
-/* Private define for @ref PreviousState usage */
-#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
- (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
- (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
-/*!< Mask State define, keep only RX and TX bits */
-#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
-/*!< Default Value */
-#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
- (uint32_t)HAL_I2C_MODE_MASTER))
-/*!< Master Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
- (uint32_t)HAL_I2C_MODE_MASTER))
-/*!< Master Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
- (uint32_t)HAL_I2C_MODE_SLAVE))
-/*!< Slave Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
- (uint32_t)HAL_I2C_MODE_SLAVE))
-/*!< Slave Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
- (uint32_t)HAL_I2C_MODE_MEM))
-/*!< Memory Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
- (uint32_t)HAL_I2C_MODE_MEM))
-/*!< Memory Busy RX, combinaison of State LSB and Mode enum */
-
-
-/* Private define to centralize the enable/disable of Interrupts */
-#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with
- @ref I2C_XFER_LISTEN_IT */
-#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with
- @ref I2C_XFER_LISTEN_IT */
-#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
- and @ref I2C_XFER_RX_IT */
-
-#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error
- and NACK treatment */
-#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */
-#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */
-
-/* Private define Sequential Transfer Options default/reset value */
-#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Macro to get remaining data to transfer on DMA side */
-#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/** @defgroup I2C_Private_Functions I2C Private Functions
- * @{
- */
-/* Private functions to handle DMA transfer */
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAError(DMA_HandleTypeDef *hdma);
-static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
-
-/* Private functions to handle IT transfer */
-static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
-static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
-static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
-
-/* Private functions to handle IT transfer */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
- uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
- uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
- uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
- uint32_t Tickstart);
-
-/* Private functions for I2C transfer IRQ handler */
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
- uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
- uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
- uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
- uint32_t ITSources);
-
-/* Private functions to handle flags during polling transfer */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
- uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
- uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
- uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
- uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
- uint32_t Tickstart);
-
-/* Private functions to centralize the enable/disable of Interrupts */
-static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
-static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
-
-/* Private function to treat different error callback */
-static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
-
-/* Private function to flush TXDR register */
-static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
-
-/* Private function to handle start, restart or stop a transfer */
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
- uint32_t Request);
-
-/* Private function to Convert Specific options */
-static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Functions I2C Exported Functions
- * @{
- */
-
-/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- deinitialize the I2Cx peripheral:
-
- (+) User must Implement HAL_I2C_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
- (+) Call the function HAL_I2C_Init() to configure the selected device with
- the selected configuration:
- (++) Clock Timing
- (++) Own Address 1
- (++) Addressing mode (Master, Slave)
- (++) Dual Addressing mode
- (++) Own Address 2
- (++) Own Address 2 Mask
- (++) General call mode
- (++) Nostretch mode
-
- (+) Call the function HAL_I2C_DeInit() to restore the default configuration
- of the selected I2Cx peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the I2C according to the specified parameters
- * in the I2C_InitTypeDef and initialize the associated handle.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
-{
- /* Check the I2C handle allocation */
- if (hi2c == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
- assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
- assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
- assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
- assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
- assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
- assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
- assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
-
- if (hi2c->State == HAL_I2C_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hi2c->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- /* Init the I2C Callback settings */
- hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
- hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
- hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
- hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
- hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
- hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
- hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
- hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
- hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
- hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
-
- if (hi2c->MspInitCallback == NULL)
- {
- hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
- }
-
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
- hi2c->MspInitCallback(hi2c);
-#else
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
- HAL_I2C_MspInit(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
- /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
- /* Configure I2Cx: Frequency range */
- hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
-
- /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
- /* Disable Own Address1 before set the Own Address1 configuration */
- hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
-
- /* Configure I2Cx: Own Address1 and ack own address1 mode */
- if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
- {
- hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
- }
- else /* I2C_ADDRESSINGMODE_10BIT */
- {
- hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
- }
-
- /*---------------------------- I2Cx CR2 Configuration ----------------------*/
- /* Configure I2Cx: Addressing Master mode */
- if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
- {
- hi2c->Instance->CR2 = (I2C_CR2_ADD10);
- }
- /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
- hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
-
- /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
- /* Disable Own Address2 before set the Own Address2 configuration */
- hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
-
- /* Configure I2Cx: Dual mode and Own Address2 */
- hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
- (hi2c->Init.OwnAddress2Masks << 8));
-
- /*---------------------------- I2Cx CR1 Configuration ----------------------*/
- /* Configure I2Cx: Generalcall and NoStretch mode */
- hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
-
- /* Enable the selected I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
-
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the I2C peripheral.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
-{
- /* Check the I2C handle allocation */
- if (hi2c == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the I2C Peripheral Clock */
- __HAL_I2C_DISABLE(hi2c);
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- if (hi2c->MspDeInitCallback == NULL)
- {
- hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
- }
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- hi2c->MspDeInitCallback(hi2c);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_I2C_MspDeInit(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->State = HAL_I2C_STATE_RESET;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the I2C MSP.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the I2C MSP.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MspDeInit could be implemented in the user file
- */
-}
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-/**
- * @brief Register a User I2C Callback
- * To be used instead of the weak predefined callback
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param CallbackID ID of the callback to be registered
- * This parameter can be one of the following values:
- * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
- * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
- * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
- * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
- * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
- * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
- * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
- * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
- * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
- * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
- * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
- * @param pCallback pointer to the Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
- pI2C_CallbackTypeDef pCallback)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL)
- {
- /* Update the error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
- return HAL_ERROR;
- }
- /* Process locked */
- __HAL_LOCK(hi2c);
-
- if (HAL_I2C_STATE_READY == hi2c->State)
- {
- switch (CallbackID)
- {
- case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
- hi2c->MasterTxCpltCallback = pCallback;
- break;
-
- case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
- hi2c->MasterRxCpltCallback = pCallback;
- break;
-
- case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
- hi2c->SlaveTxCpltCallback = pCallback;
- break;
-
- case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
- hi2c->SlaveRxCpltCallback = pCallback;
- break;
-
- case HAL_I2C_LISTEN_COMPLETE_CB_ID :
- hi2c->ListenCpltCallback = pCallback;
- break;
-
- case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
- hi2c->MemTxCpltCallback = pCallback;
- break;
-
- case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
- hi2c->MemRxCpltCallback = pCallback;
- break;
-
- case HAL_I2C_ERROR_CB_ID :
- hi2c->ErrorCallback = pCallback;
- break;
-
- case HAL_I2C_ABORT_CB_ID :
- hi2c->AbortCpltCallback = pCallback;
- break;
-
- case HAL_I2C_MSPINIT_CB_ID :
- hi2c->MspInitCallback = pCallback;
- break;
-
- case HAL_I2C_MSPDEINIT_CB_ID :
- hi2c->MspDeInitCallback = pCallback;
- break;
-
- default :
- /* Update the error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else if (HAL_I2C_STATE_RESET == hi2c->State)
- {
- switch (CallbackID)
- {
- case HAL_I2C_MSPINIT_CB_ID :
- hi2c->MspInitCallback = pCallback;
- break;
-
- case HAL_I2C_MSPDEINIT_CB_ID :
- hi2c->MspDeInitCallback = pCallback;
- break;
-
- default :
- /* Update the error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- /* Update the error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
- return status;
-}
-
-/**
- * @brief Unregister an I2C Callback
- * I2C callback is redirected to the weak predefined callback
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param CallbackID ID of the callback to be unregistered
- * This parameter can be one of the following values:
- * This parameter can be one of the following values:
- * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
- * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
- * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
- * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
- * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
- * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
- * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
- * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
- * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
- * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
- * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hi2c);
-
- if (HAL_I2C_STATE_READY == hi2c->State)
- {
- switch (CallbackID)
- {
- case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
- hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
- break;
-
- case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
- hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
- break;
-
- case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
- hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
- break;
-
- case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
- hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
- break;
-
- case HAL_I2C_LISTEN_COMPLETE_CB_ID :
- hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
- break;
-
- case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
- hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
- break;
-
- case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
- hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
- break;
-
- case HAL_I2C_ERROR_CB_ID :
- hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
- break;
-
- case HAL_I2C_ABORT_CB_ID :
- hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
- break;
-
- case HAL_I2C_MSPINIT_CB_ID :
- hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
- break;
-
- case HAL_I2C_MSPDEINIT_CB_ID :
- hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
- break;
-
- default :
- /* Update the error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else if (HAL_I2C_STATE_RESET == hi2c->State)
- {
- switch (CallbackID)
- {
- case HAL_I2C_MSPINIT_CB_ID :
- hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
- break;
-
- case HAL_I2C_MSPDEINIT_CB_ID :
- hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
- break;
-
- default :
- /* Update the error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- /* Update the error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
- return status;
-}
-
-/**
- * @brief Register the Slave Address Match I2C Callback
- * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pCallback pointer to the Address Match Callback function
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL)
- {
- /* Update the error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
- return HAL_ERROR;
- }
- /* Process locked */
- __HAL_LOCK(hi2c);
-
- if (HAL_I2C_STATE_READY == hi2c->State)
- {
- hi2c->AddrCallback = pCallback;
- }
- else
- {
- /* Update the error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
- return status;
-}
-
-/**
- * @brief UnRegister the Slave Address Match I2C Callback
- * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hi2c);
-
- if (HAL_I2C_STATE_READY == hi2c->State)
- {
- hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
- }
- else
- {
- /* Update the error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
- return status;
-}
-
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the I2C data
- transfers.
-
- (#) There are two modes of transfer:
- (++) Blocking mode : The communication is performed in the polling mode.
- The status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode : The communication is performed using Interrupts
- or DMA. These functions return the status of the transfer startup.
- The end of the data processing will be indicated through the
- dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
-
- (#) Blocking mode functions are :
- (++) HAL_I2C_Master_Transmit()
- (++) HAL_I2C_Master_Receive()
- (++) HAL_I2C_Slave_Transmit()
- (++) HAL_I2C_Slave_Receive()
- (++) HAL_I2C_Mem_Write()
- (++) HAL_I2C_Mem_Read()
- (++) HAL_I2C_IsDeviceReady()
-
- (#) No-Blocking mode functions with Interrupt are :
- (++) HAL_I2C_Master_Transmit_IT()
- (++) HAL_I2C_Master_Receive_IT()
- (++) HAL_I2C_Slave_Transmit_IT()
- (++) HAL_I2C_Slave_Receive_IT()
- (++) HAL_I2C_Mem_Write_IT()
- (++) HAL_I2C_Mem_Read_IT()
- (++) HAL_I2C_Master_Seq_Transmit_IT()
- (++) HAL_I2C_Master_Seq_Receive_IT()
- (++) HAL_I2C_Slave_Seq_Transmit_IT()
- (++) HAL_I2C_Slave_Seq_Receive_IT()
- (++) HAL_I2C_EnableListen_IT()
- (++) HAL_I2C_DisableListen_IT()
- (++) HAL_I2C_Master_Abort_IT()
-
- (#) No-Blocking mode functions with DMA are :
- (++) HAL_I2C_Master_Transmit_DMA()
- (++) HAL_I2C_Master_Receive_DMA()
- (++) HAL_I2C_Slave_Transmit_DMA()
- (++) HAL_I2C_Slave_Receive_DMA()
- (++) HAL_I2C_Mem_Write_DMA()
- (++) HAL_I2C_Mem_Read_DMA()
- (++) HAL_I2C_Master_Seq_Transmit_DMA()
- (++) HAL_I2C_Master_Seq_Receive_DMA()
- (++) HAL_I2C_Slave_Seq_Transmit_DMA()
- (++) HAL_I2C_Slave_Seq_Receive_DMA()
-
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_I2C_MasterTxCpltCallback()
- (++) HAL_I2C_MasterRxCpltCallback()
- (++) HAL_I2C_SlaveTxCpltCallback()
- (++) HAL_I2C_SlaveRxCpltCallback()
- (++) HAL_I2C_MemTxCpltCallback()
- (++) HAL_I2C_MemRxCpltCallback()
- (++) HAL_I2C_AddrCallback()
- (++) HAL_I2C_ListenCpltCallback()
- (++) HAL_I2C_ErrorCallback()
- (++) HAL_I2C_AbortCpltCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmits in master mode an amount of data in blocking mode.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferISR = NULL;
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
- I2C_GENERATE_START_WRITE);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
- I2C_GENERATE_START_WRITE);
- }
-
- while (hi2c->XferCount > 0U)
- {
- /* Wait until TXIS flag is set */
- if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
- /* Write data to TXDR */
- hi2c->Instance->TXDR = *hi2c->pBuffPtr;
-
- /* Increment Buffer pointer */
- hi2c->pBuffPtr++;
-
- hi2c->XferCount--;
- hi2c->XferSize--;
-
- if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
- {
- /* Wait until TCR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
- I2C_NO_STARTSTOP);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
- I2C_NO_STARTSTOP);
- }
- }
- }
-
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is set */
- if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receives in master mode an amount of data in blocking mode.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferISR = NULL;
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
- I2C_GENERATE_START_READ);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
- I2C_GENERATE_START_READ);
- }
-
- while (hi2c->XferCount > 0U)
- {
- /* Wait until RXNE flag is set */
- if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Read data from RXDR */
- *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
-
- /* Increment Buffer pointer */
- hi2c->pBuffPtr++;
-
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
- {
- /* Wait until TCR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
- I2C_NO_STARTSTOP);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
- I2C_NO_STARTSTOP);
- }
- }
- }
-
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is set */
- if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmits in slave mode an amount of data in blocking mode.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
- uint32_t Timeout)
-{
- uint32_t tickstart;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferISR = NULL;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Wait until ADDR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-
- /* If 10bit addressing mode is selected */
- if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
- {
- /* Wait until ADDR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
- }
-
- /* Wait until DIR flag is set Transmitter mode */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
- }
-
- while (hi2c->XferCount > 0U)
- {
- /* Wait until TXIS flag is set */
- if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
- }
-
- /* Write data to TXDR */
- hi2c->Instance->TXDR = *hi2c->pBuffPtr;
-
- /* Increment Buffer pointer */
- hi2c->pBuffPtr++;
-
- hi2c->XferCount--;
- }
-
- /* Wait until AF flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
- }
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
-
- /* Clear AF flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Wait until STOP flag is set */
- if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- return HAL_ERROR;
- }
-
- /* Clear STOP flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Wait until BUSY flag is reset */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
- }
-
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in slave mode an amount of data in blocking mode
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
- uint32_t Timeout)
-{
- uint32_t tickstart;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferISR = NULL;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Wait until ADDR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-
- /* Wait until DIR flag is reset Receiver mode */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
- }
-
- while (hi2c->XferCount > 0U)
- {
- /* Wait until RXNE flag is set */
- if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- /* Store Last receive data if any */
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
- {
- /* Read data from RXDR */
- *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
-
- /* Increment Buffer pointer */
- hi2c->pBuffPtr++;
-
- hi2c->XferCount--;
- hi2c->XferSize--;
- }
-
- return HAL_ERROR;
- }
-
- /* Read data from RXDR */
- *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
-
- /* Increment Buffer pointer */
- hi2c->pBuffPtr++;
-
- hi2c->XferCount--;
- hi2c->XferSize--;
- }
-
- /* Wait until STOP flag is set */
- if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
- }
-
- /* Clear STOP flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Wait until BUSY flag is reset */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
- }
-
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size)
-{
- uint32_t xfermode;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
- I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size)
-{
- uint32_t xfermode;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable ERR, TC, STOP, NACK, RXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
- I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Slave_ISR_IT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
- I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Slave_ISR_IT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable ERR, TC, STOP, NACK, RXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
- I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size)
-{
- uint32_t xfermode;
- HAL_StatusTypeDef dmaxferstatus;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- if (hi2c->XferSize > 0U)
- {
- if (hi2c->hdmatx != NULL)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
- hi2c->XferSize);
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- if (dmaxferstatus == HAL_OK)
- {
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
- }
- else
- {
- /* Update Transfer ISR function pointer */
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- /* Send Slave Address */
- /* Set NBYTES to write and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
- I2C_GENERATE_START_WRITE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
- I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in master mode an amount of data in non-blocking mode with DMA
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size)
-{
- uint32_t xfermode;
- HAL_StatusTypeDef dmaxferstatus;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- if (hi2c->XferSize > 0U)
- {
- if (hi2c->hdmarx != NULL)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
- hi2c->XferSize);
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- if (dmaxferstatus == HAL_OK)
- {
- /* Send Slave Address */
- /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
- }
- else
- {
- /* Update Transfer ISR function pointer */
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- /* Send Slave Address */
- /* Set NBYTES to read and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
- I2C_GENERATE_START_READ);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
- I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef dmaxferstatus;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Slave_ISR_DMA;
-
- if (hi2c->hdmatx != NULL)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
- hi2c->XferSize);
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- if (dmaxferstatus == HAL_OK)
- {
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, STOP, NACK, ADDR interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef dmaxferstatus;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Slave_ISR_DMA;
-
- if (hi2c->hdmarx != NULL)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
- hi2c->XferSize);
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- if (dmaxferstatus == HAL_OK)
- {
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, STOP, NACK, ADDR interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-/**
- * @brief Write an amount of data in blocking mode to a specific memory address
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferISR = NULL;
-
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
-
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- }
-
- do
- {
- /* Wait until TXIS flag is set */
- if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Write data to TXDR */
- hi2c->Instance->TXDR = *hi2c->pBuffPtr;
-
- /* Increment Buffer pointer */
- hi2c->pBuffPtr++;
-
- hi2c->XferCount--;
- hi2c->XferSize--;
-
- if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
- {
- /* Wait until TCR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
- I2C_NO_STARTSTOP);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
- I2C_NO_STARTSTOP);
- }
- }
-
- } while (hi2c->XferCount > 0U);
-
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Read an amount of data in blocking mode from a specific memory address
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferISR = NULL;
-
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
- I2C_GENERATE_START_READ);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
- I2C_GENERATE_START_READ);
- }
-
- do
- {
- /* Wait until RXNE flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Read data from RXDR */
- *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
-
- /* Increment Buffer pointer */
- hi2c->pBuffPtr++;
-
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
- {
- /* Wait until TCR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
- I2C_NO_STARTSTOP);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
- I2C_NO_STARTSTOP);
- }
- }
- } while (hi2c->XferCount > 0U);
-
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-/**
- * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
- uint32_t tickstart;
- uint32_t xfermode;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
- return HAL_ERROR;
- }
-
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
- != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
-
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
- I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
- uint32_t tickstart;
- uint32_t xfermode;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
- return HAL_ERROR;
- }
-
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
-
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable ERR, TC, STOP, NACK, RXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
- I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-/**
- * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
- uint32_t tickstart;
- uint32_t xfermode;
- HAL_StatusTypeDef dmaxferstatus;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
- return HAL_ERROR;
- }
-
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
- != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
-
-
- if (hi2c->hdmatx != NULL)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
- hi2c->XferSize);
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- if (dmaxferstatus == HAL_OK)
- {
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be read
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
- uint32_t tickstart;
- uint32_t xfermode;
- HAL_StatusTypeDef dmaxferstatus;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
- return HAL_ERROR;
- }
-
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
-
- if (hi2c->hdmarx != NULL)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
- hi2c->XferSize);
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- if (dmaxferstatus == HAL_OK)
- {
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Checks if target device is ready for communication.
- * @note This function is used with Memory devices
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @param Trials Number of trials
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
- uint32_t Timeout)
-{
- uint32_t tickstart;
-
- __IO uint32_t I2C_Trials = 0UL;
-
- FlagStatus tmp1;
- FlagStatus tmp2;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- do
- {
- /* Generate Start */
- hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
-
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is set or a NACK flag is set*/
- tickstart = HAL_GetTick();
-
- tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
- tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
-
- while ((tmp1 == RESET) && (tmp2 == RESET))
- {
- if (Timeout != HAL_MAX_DELAY)
- {
- if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
- }
-
- tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
- tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
- }
-
- /* Check if the NACKF flag has not been set */
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
- {
- /* Wait until STOPF flag is reset */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Device is ready */
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- /* Wait until STOPF flag is reset */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Clear STOP Flag, auto generated with autoend*/
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- }
-
- /* Check if the maximum allowed number of trials has been reached */
- if (I2C_Trials == Trials)
- {
- /* Generate Stop */
- hi2c->Instance->CR2 |= I2C_CR2_STOP;
-
- /* Wait until STOPF flag is reset */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- }
-
- /* Increment Trials */
- I2C_Trials++;
- } while (I2C_Trials < Trials);
-
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t XferOptions)
-{
- uint32_t xfermode;
- uint32_t xferrequest = I2C_GENERATE_START_WRITE;
-
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = XferOptions;
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = hi2c->XferOptions;
- }
-
- /* If transfer direction not change and there is no request to start another frame,
- do not generate Restart Condition */
- /* Mean Previous state is same as current state */
- if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
- (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
- {
- xferrequest = I2C_NO_STARTSTOP;
- }
- else
- {
- /* Convert OTHER_xxx XferOptions if any */
- I2C_ConvertOtherXferOptions(hi2c);
-
- /* Update xfermode accordingly if no reload is necessary */
- if (hi2c->XferCount <= MAX_NBYTE_SIZE)
- {
- xfermode = hi2c->XferOptions;
- }
- }
-
- /* Send Slave Address and set NBYTES to write */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t XferOptions)
-{
- uint32_t xfermode;
- uint32_t xferrequest = I2C_GENERATE_START_WRITE;
- HAL_StatusTypeDef dmaxferstatus;
-
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = XferOptions;
- hi2c->XferISR = I2C_Master_ISR_DMA;
-
- /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = hi2c->XferOptions;
- }
-
- /* If transfer direction not change and there is no request to start another frame,
- do not generate Restart Condition */
- /* Mean Previous state is same as current state */
- if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
- (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
- {
- xferrequest = I2C_NO_STARTSTOP;
- }
- else
- {
- /* Convert OTHER_xxx XferOptions if any */
- I2C_ConvertOtherXferOptions(hi2c);
-
- /* Update xfermode accordingly if no reload is necessary */
- if (hi2c->XferCount <= MAX_NBYTE_SIZE)
- {
- xfermode = hi2c->XferOptions;
- }
- }
-
- if (hi2c->XferSize > 0U)
- {
- if (hi2c->hdmatx != NULL)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
- hi2c->XferSize);
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- if (dmaxferstatus == HAL_OK)
- {
- /* Send Slave Address and set NBYTES to write */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
- }
- else
- {
- /* Update Transfer ISR function pointer */
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- /* Send Slave Address */
- /* Set NBYTES to write and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
- I2C_GENERATE_START_WRITE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
- I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t XferOptions)
-{
- uint32_t xfermode;
- uint32_t xferrequest = I2C_GENERATE_START_READ;
-
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = XferOptions;
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = hi2c->XferOptions;
- }
-
- /* If transfer direction not change and there is no request to start another frame,
- do not generate Restart Condition */
- /* Mean Previous state is same as current state */
- if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
- (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
- {
- xferrequest = I2C_NO_STARTSTOP;
- }
- else
- {
- /* Convert OTHER_xxx XferOptions if any */
- I2C_ConvertOtherXferOptions(hi2c);
-
- /* Update xfermode accordingly if no reload is necessary */
- if (hi2c->XferCount <= MAX_NBYTE_SIZE)
- {
- xfermode = hi2c->XferOptions;
- }
- }
-
- /* Send Slave Address and set NBYTES to read */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t XferOptions)
-{
- uint32_t xfermode;
- uint32_t xferrequest = I2C_GENERATE_START_READ;
- HAL_StatusTypeDef dmaxferstatus;
-
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = XferOptions;
- hi2c->XferISR = I2C_Master_ISR_DMA;
-
- /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = hi2c->XferOptions;
- }
-
- /* If transfer direction not change and there is no request to start another frame,
- do not generate Restart Condition */
- /* Mean Previous state is same as current state */
- if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
- (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
- {
- xferrequest = I2C_NO_STARTSTOP;
- }
- else
- {
- /* Convert OTHER_xxx XferOptions if any */
- I2C_ConvertOtherXferOptions(hi2c);
-
- /* Update xfermode accordingly if no reload is necessary */
- if (hi2c->XferCount <= MAX_NBYTE_SIZE)
- {
- xfermode = hi2c->XferOptions;
- }
- }
-
- if (hi2c->XferSize > 0U)
- {
- if (hi2c->hdmarx != NULL)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
- hi2c->XferSize);
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- if (dmaxferstatus == HAL_OK)
- {
- /* Send Slave Address and set NBYTES to read */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
- }
- else
- {
- /* Update Transfer ISR function pointer */
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- /* Send Slave Address */
- /* Set NBYTES to read and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
- I2C_GENERATE_START_READ);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
- I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
- uint32_t XferOptions)
-{
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
- return HAL_ERROR;
- }
-
- /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
- /* and then toggle the HAL slave RX state to TX state */
- if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
- {
- /* Disable associated Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-
- /* Abort DMA Xfer if any */
- if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
- {
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
- if (hi2c->hdmarx != NULL)
- {
- /* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
- hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
-
- /* Abort DMA RX */
- if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
- {
- /* Call Directly XferAbortCallback function in case of error */
- hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
- }
- }
- }
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = XferOptions;
- hi2c->XferISR = I2C_Slave_ISR_IT;
-
- if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
- {
- /* Clear ADDR flag after prepare the transfer parameters */
- /* This action will generate an acknowledge to the Master */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* REnable ADDR interrupt */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
- uint32_t XferOptions)
-{
- HAL_StatusTypeDef dmaxferstatus;
-
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
-
- /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
- /* and then toggle the HAL slave RX state to TX state */
- if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
- {
- /* Disable associated Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-
- if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
- {
- /* Abort DMA Xfer if any */
- if (hi2c->hdmarx != NULL)
- {
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
- /* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
- hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
-
- /* Abort DMA RX */
- if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
- {
- /* Call Directly XferAbortCallback function in case of error */
- hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
- }
- }
- }
- }
- else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
- {
- if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
- {
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
- /* Abort DMA Xfer if any */
- if (hi2c->hdmatx != NULL)
- {
- /* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
- hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
-
- /* Abort DMA TX */
- if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
- {
- /* Call Directly XferAbortCallback function in case of error */
- hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
- }
- }
- }
- }
- else
- {
- /* Nothing to do */
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = XferOptions;
- hi2c->XferISR = I2C_Slave_ISR_DMA;
-
- if (hi2c->hdmatx != NULL)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
- hi2c->XferSize);
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- if (dmaxferstatus == HAL_OK)
- {
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
-
- /* Reset XferSize */
- hi2c->XferSize = 0;
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
- {
- /* Clear ADDR flag after prepare the transfer parameters */
- /* This action will generate an acknowledge to the Master */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, STOP, NACK, ADDR interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
- uint32_t XferOptions)
-{
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
- return HAL_ERROR;
- }
-
- /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
- /* and then toggle the HAL slave TX state to RX state */
- if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
- {
- /* Disable associated Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
- if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
- {
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
- /* Abort DMA Xfer if any */
- if (hi2c->hdmatx != NULL)
- {
- /* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
- hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
-
- /* Abort DMA TX */
- if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
- {
- /* Call Directly XferAbortCallback function in case of error */
- hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
- }
- }
- }
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = XferOptions;
- hi2c->XferISR = I2C_Slave_ISR_IT;
-
- if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
- {
- /* Clear ADDR flag after prepare the transfer parameters */
- /* This action will generate an acknowledge to the Master */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* REnable ADDR interrupt */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
- uint32_t XferOptions)
-{
- HAL_StatusTypeDef dmaxferstatus;
-
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
- return HAL_ERROR;
- }
-
- /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
- /* and then toggle the HAL slave TX state to RX state */
- if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
- {
- /* Disable associated Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
- if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
- {
- /* Abort DMA Xfer if any */
- if (hi2c->hdmatx != NULL)
- {
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
- /* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
- hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
-
- /* Abort DMA TX */
- if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
- {
- /* Call Directly XferAbortCallback function in case of error */
- hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
- }
- }
- }
- }
- else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
- {
- if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
- {
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
- /* Abort DMA Xfer if any */
- if (hi2c->hdmarx != NULL)
- {
- /* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
- hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
-
- /* Abort DMA RX */
- if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
- {
- /* Call Directly XferAbortCallback function in case of error */
- hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
- }
- }
- }
- }
- else
- {
- /* Nothing to do */
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = XferOptions;
- hi2c->XferISR = I2C_Slave_ISR_DMA;
-
- if (hi2c->hdmarx != NULL)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
- (uint32_t)pData, hi2c->XferSize);
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- if (dmaxferstatus == HAL_OK)
- {
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
-
- /* Reset XferSize */
- hi2c->XferSize = 0;
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
- {
- /* Clear ADDR flag after prepare the transfer parameters */
- /* This action will generate an acknowledge to the Master */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* REnable ADDR interrupt */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable the Address listen mode with Interrupt.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
-{
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->XferISR = I2C_Slave_ISR_IT;
-
- /* Enable the Address Match interrupt */
- I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Disable the Address listen mode with Interrupt.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
-{
- /* Declaration of tmp to prevent undefined behavior of volatile usage */
- uint32_t tmp;
-
- /* Disable Address listen mode only if a transfer is not ongoing */
- if (hi2c->State == HAL_I2C_STATE_LISTEN)
- {
- tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
- hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->XferISR = NULL;
-
- /* Disable the Address Match interrupt */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Abort a master I2C IT or DMA process communication with Interrupt.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
-{
- if (hi2c->Mode == HAL_I2C_MODE_MASTER)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Disable Interrupts and Store Previous state */
- if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
- {
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
- hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
- }
- else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
- {
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
- hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
- }
- else
- {
- /* Do nothing */
- }
-
- /* Set State at HAL_I2C_STATE_ABORT */
- hi2c->State = HAL_I2C_STATE_ABORT;
-
- /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
- /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
- I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
-
- return HAL_OK;
- }
- else
- {
- /* Wrong usage of abort function */
- /* This function should be used only in case of abort monitored by master device */
- return HAL_ERROR;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
-
-/**
- * @brief This function handles I2C event interrupt request.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
- /* Get current IT Flags and IT sources value */
- uint32_t itflags = READ_REG(hi2c->Instance->ISR);
- uint32_t itsources = READ_REG(hi2c->Instance->CR1);
-
- /* I2C events treatment -------------------------------------*/
- if (hi2c->XferISR != NULL)
- {
- hi2c->XferISR(hi2c, itflags, itsources);
- }
-}
-
-/**
- * @brief This function handles I2C error interrupt request.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
- uint32_t itflags = READ_REG(hi2c->Instance->ISR);
- uint32_t itsources = READ_REG(hi2c->Instance->CR1);
- uint32_t tmperror;
-
- /* I2C Bus error interrupt occurred ------------------------------------*/
- if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
- (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
-
- /* Clear BERR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
- }
-
- /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
- (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
-
- /* Clear OVR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
- }
-
- /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
- if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
- (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
-
- /* Clear ARLO flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
- }
-
- /* Store current volatile hi2c->ErrorCode, misra rule */
- tmperror = hi2c->ErrorCode;
-
- /* Call the Error Callback in case of Error detected */
- if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
- {
- I2C_ITError(hi2c, tmperror);
- }
-}
-
-/**
- * @brief Master Tx Transfer completed callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Master Rx Transfer completed callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
- */
-}
-
-/** @brief Slave Tx Transfer completed callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Slave Rx Transfer completed callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Slave Address Match callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
- * @param AddrMatchCode Address Match Code
- * @retval None
- */
-__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
- UNUSED(TransferDirection);
- UNUSED(AddrMatchCode);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_AddrCallback() could be implemented in the user file
- */
-}
-
-/**
- * @brief Listen Complete callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_ListenCpltCallback() could be implemented in the user file
- */
-}
-
-/**
- * @brief Memory Tx Transfer completed callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MemTxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Memory Rx Transfer completed callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MemRxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief I2C error callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief I2C abort callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_AbortCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
- * @brief Peripheral State, Mode and Error functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State, Mode and Error functions #####
- ===============================================================================
- [..]
- This subsection permit to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the I2C handle state.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL state
- */
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
-{
- /* Return I2C handle state */
- return hi2c->State;
-}
-
-/**
- * @brief Returns the I2C Master, Slave, Memory or no mode.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL mode
- */
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
-{
- return hi2c->Mode;
-}
-
-/**
- * @brief Return the I2C error code.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval I2C Error Code
- */
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
-{
- return hi2c->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup I2C_Private_Functions
- * @{
- */
-
-/**
- * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param ITFlags Interrupt flags to handle.
- * @param ITSources Interrupt sources enabled.
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
- uint32_t ITSources)
-{
- uint16_t devaddress;
- uint32_t tmpITFlags = ITFlags;
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Set corresponding Error Code */
- /* No need to generate STOP, it is automatically done */
- /* Error callback will be send during stop flag treatment */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
- }
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
- {
- /* Remove RXNE flag on temporary variable as read done */
- tmpITFlags &= ~I2C_FLAG_RXNE;
-
- /* Read data from RXDR */
- *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
-
- /* Increment Buffer pointer */
- hi2c->pBuffPtr++;
-
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
- {
- /* Write data to TXDR */
- hi2c->Instance->TXDR = *hi2c->pBuffPtr;
-
- /* Increment Buffer pointer */
- hi2c->pBuffPtr++;
-
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
- {
- if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
- {
- devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
- {
- I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
- hi2c->XferOptions, I2C_NO_STARTSTOP);
- }
- else
- {
- I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
- I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- }
- }
- }
- else
- {
- /* Call TxCpltCallback() if no stop mode is set */
- if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
- {
- /* Call I2C Master Sequential complete process */
- I2C_ITMasterSeqCplt(hi2c);
- }
- else
- {
- /* Wrong size Status regarding TCR flag event */
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
- }
- }
- }
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
- {
- if (hi2c->XferCount == 0U)
- {
- if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
- {
- /* Generate a stop condition in case of no transfer option */
- if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
- {
- /* Generate Stop */
- hi2c->Instance->CR2 |= I2C_CR2_STOP;
- }
- else
- {
- /* Call I2C Master Sequential complete process */
- I2C_ITMasterSeqCplt(hi2c);
- }
- }
- }
- else
- {
- /* Wrong size Status regarding TC flag event */
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
- }
- }
- else
- {
- /* Nothing to do */
- }
-
- if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
- {
- /* Call I2C Master complete process */
- I2C_ITMasterCplt(hi2c, tmpITFlags);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
-}
-
-/**
- * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param ITFlags Interrupt flags to handle.
- * @param ITSources Interrupt sources enabled.
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
- uint32_t ITSources)
-{
- uint32_t tmpoptions = hi2c->XferOptions;
- uint32_t tmpITFlags = ITFlags;
-
- /* Process locked */
- __HAL_LOCK(hi2c);
-
- /* Check if STOPF is set */
- if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
- {
- /* Call I2C Slave complete process */
- I2C_ITSlaveCplt(hi2c, tmpITFlags);
- }
-
- if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
- {
- /* Check that I2C transfer finished */
- /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
- /* Mean XferCount == 0*/
- /* So clear Flag NACKF only */
- if (hi2c->XferCount == 0U)
- {
- if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
- /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
- Warning[Pa134]: left and right operands are identical */
- {
- /* Call I2C Listen complete process */
- I2C_ITListenCplt(hi2c, tmpITFlags);
- }
- else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
-
- /* Last Byte is Transmitted */
- /* Call I2C Slave Sequential complete process */
- I2C_ITSlaveSeqCplt(hi2c);
- }
- else
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- }
- }
- else
- {
- /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
- if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
- {
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, hi2c->ErrorCode);
- }
- }
- }
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
- {
- if (hi2c->XferCount > 0U)
- {
- /* Read data from RXDR */
- *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
-
- /* Increment Buffer pointer */
- hi2c->pBuffPtr++;
-
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
-
- if ((hi2c->XferCount == 0U) && \
- (tmpoptions != I2C_NO_OPTION_FRAME))
- {
- /* Call I2C Slave Sequential complete process */
- I2C_ITSlaveSeqCplt(hi2c);
- }
- }
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
- {
- I2C_ITAddrCplt(hi2c, tmpITFlags);
- }
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
- {
- /* Write data to TXDR only if XferCount not reach "0" */
- /* A TXIS flag can be set, during STOP treatment */
- /* Check if all Data have already been sent */
- /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
- if (hi2c->XferCount > 0U)
- {
- /* Write data to TXDR */
- hi2c->Instance->TXDR = *hi2c->pBuffPtr;
-
- /* Increment Buffer pointer */
- hi2c->pBuffPtr++;
-
- hi2c->XferCount--;
- hi2c->XferSize--;
- }
- else
- {
- if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
- {
- /* Last Byte is Transmitted */
- /* Call I2C Slave Sequential complete process */
- I2C_ITSlaveSeqCplt(hi2c);
- }
- }
- }
- else
- {
- /* Nothing to do */
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
-}
-
-/**
- * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param ITFlags Interrupt flags to handle.
- * @param ITSources Interrupt sources enabled.
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
- uint32_t ITSources)
-{
- uint16_t devaddress;
- uint32_t xfermode;
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Set corresponding Error Code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
- /* No need to generate STOP, it is automatically done */
- /* But enable STOP interrupt, to treat it */
- /* Error callback will be send during stop flag treatment */
- I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
- }
- else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
- {
- /* Disable TC interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
-
- if (hi2c->XferCount != 0U)
- {
- /* Recover Slave address */
- devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
-
- /* Prepare the new XferSize to transfer */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
- {
- xfermode = hi2c->XferOptions;
- }
- else
- {
- xfermode = I2C_AUTOEND_MODE;
- }
- }
-
- /* Set the new XferSize in Nbytes register */
- I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
-
- /* Enable DMA Request */
- if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
- {
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
- }
- else
- {
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
- }
- }
- else
- {
- /* Call TxCpltCallback() if no stop mode is set */
- if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
- {
- /* Call I2C Master Sequential complete process */
- I2C_ITMasterSeqCplt(hi2c);
- }
- else
- {
- /* Wrong size Status regarding TCR flag event */
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
- }
- }
- }
- else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
- {
- if (hi2c->XferCount == 0U)
- {
- if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
- {
- /* Generate a stop condition in case of no transfer option */
- if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
- {
- /* Generate Stop */
- hi2c->Instance->CR2 |= I2C_CR2_STOP;
- }
- else
- {
- /* Call I2C Master Sequential complete process */
- I2C_ITMasterSeqCplt(hi2c);
- }
- }
- }
- else
- {
- /* Wrong size Status regarding TC flag event */
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
- }
- }
- else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
- {
- /* Call I2C Master complete process */
- I2C_ITMasterCplt(hi2c, ITFlags);
- }
- else
- {
- /* Nothing to do */
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
-}
-
-/**
- * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param ITFlags Interrupt flags to handle.
- * @param ITSources Interrupt sources enabled.
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
- uint32_t ITSources)
-{
- uint32_t tmpoptions = hi2c->XferOptions;
- uint32_t treatdmanack = 0U;
- HAL_I2C_StateTypeDef tmpstate;
-
- /* Process locked */
- __HAL_LOCK(hi2c);
-
- /* Check if STOPF is set */
- if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
- {
- /* Call I2C Slave complete process */
- I2C_ITSlaveCplt(hi2c, ITFlags);
- }
-
- if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
- {
- /* Check that I2C transfer finished */
- /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
- /* Mean XferCount == 0 */
- /* So clear Flag NACKF only */
- if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
- {
- /* Split check of hdmarx, for MISRA compliance */
- if (hi2c->hdmarx != NULL)
- {
- if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
- {
- if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
- {
- treatdmanack = 1U;
- }
- }
- }
-
- /* Split check of hdmatx, for MISRA compliance */
- if (hi2c->hdmatx != NULL)
- {
- if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
- {
- if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
- {
- treatdmanack = 1U;
- }
- }
- }
-
- if (treatdmanack == 1U)
- {
- if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
- /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
- Warning[Pa134]: left and right operands are identical */
- {
- /* Call I2C Listen complete process */
- I2C_ITListenCplt(hi2c, ITFlags);
- }
- else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
-
- /* Last Byte is Transmitted */
- /* Call I2C Slave Sequential complete process */
- I2C_ITSlaveSeqCplt(hi2c);
- }
- else
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- }
- }
- else
- {
- /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
- /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
- tmpstate = hi2c->State;
-
- if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
- {
- if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
- {
- hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
- }
- else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
- {
- hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
- }
- else
- {
- /* Do nothing */
- }
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, hi2c->ErrorCode);
- }
- }
- }
- else
- {
- /* Only Clear NACK Flag, no DMA treatment is pending */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- }
- }
- else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
- {
- I2C_ITAddrCplt(hi2c, ITFlags);
- }
- else
- {
- /* Nothing to do */
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
-}
-
-/**
- * @brief Master sends target device address followed by internal memory address for write request.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
- uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
- uint32_t Tickstart)
-{
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
-
- /* Wait until TXIS flag is set */
- if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* If Memory address size is 8Bit */
- if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
- {
- /* Send Memory Address */
- hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
- }
- /* If Memory address size is 16Bit */
- else
- {
- /* Send MSB of Memory Address */
- hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
-
- /* Wait until TXIS flag is set */
- if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Send LSB of Memory Address */
- hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
- }
-
- /* Wait until TCR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Master sends target device address followed by internal memory address for read request.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
- uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
- uint32_t Tickstart)
-{
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
-
- /* Wait until TXIS flag is set */
- if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* If Memory address size is 8Bit */
- if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
- {
- /* Send Memory Address */
- hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
- }
- /* If Memory address size is 16Bit */
- else
- {
- /* Send MSB of Memory Address */
- hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
-
- /* Wait until TXIS flag is set */
- if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Send LSB of Memory Address */
- hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
- }
-
- /* Wait until TC flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief I2C Address complete process callback.
- * @param hi2c I2C handle.
- * @param ITFlags Interrupt flags to handle.
- * @retval None
- */
-static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
- uint8_t transferdirection;
- uint16_t slaveaddrcode;
- uint16_t ownadd1code;
- uint16_t ownadd2code;
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(ITFlags);
-
- /* In case of Listen state, need to inform upper layer of address match code event */
- if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
- {
- transferdirection = I2C_GET_DIR(hi2c);
- slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
- ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
- ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
-
- /* If 10bits addressing mode is selected */
- if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
- {
- if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
- {
- slaveaddrcode = ownadd1code;
- hi2c->AddrEventCount++;
- if (hi2c->AddrEventCount == 2U)
- {
- /* Reset Address Event counter */
- hi2c->AddrEventCount = 0U;
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call Slave Addr callback */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
-#else
- HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
- }
- }
- else
- {
- slaveaddrcode = ownadd2code;
-
- /* Disable ADDR Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call Slave Addr callback */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
-#else
- HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
- }
- }
- /* else 7 bits addressing mode is selected */
- else
- {
- /* Disable ADDR Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call Slave Addr callback */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
-#else
- HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
- }
- }
- /* Else clear address flag only */
- else
- {
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- }
-}
-
-/**
- * @brief I2C Master sequential complete process.
- * @param hi2c I2C handle.
- * @retval None
- */
-static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
-{
- /* Reset I2C handle mode */
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* No Generate Stop, to permit restart mode */
- /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
- if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
- {
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
- hi2c->XferISR = NULL;
-
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->MasterTxCpltCallback(hi2c);
-#else
- HAL_I2C_MasterTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
- }
- /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
- else
- {
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
- hi2c->XferISR = NULL;
-
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->MasterRxCpltCallback(hi2c);
-#else
- HAL_I2C_MasterRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
- }
-}
-
-/**
- * @brief I2C Slave sequential complete process.
- * @param hi2c I2C handle.
- * @retval None
- */
-static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
-{
- uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
-
- /* Reset I2C handle mode */
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* If a DMA is ongoing, Update handle size context */
- if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
- {
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
- }
- else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
- {
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
- }
- else
- {
- /* Do nothing */
- }
-
- if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
- {
- /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
-
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->SlaveTxCpltCallback(hi2c);
-#else
- HAL_I2C_SlaveTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
- }
-
- else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
- {
- /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
-
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->SlaveRxCpltCallback(hi2c);
-#else
- HAL_I2C_SlaveRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
- }
- else
- {
- /* Nothing to do */
- }
-}
-
-/**
- * @brief I2C Master complete process.
- * @param hi2c I2C handle.
- * @param ITFlags Interrupt flags to handle.
- * @retval None
- */
-static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
- uint32_t tmperror;
- uint32_t tmpITFlags = ITFlags;
- __IO uint32_t tmpreg;
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Disable Interrupts and Store Previous state */
- if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
- {
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
- hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
- }
- else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
- {
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
- hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
- }
- else
- {
- /* Do nothing */
- }
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- /* Reset handle parameters */
- hi2c->XferISR = NULL;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
- if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Set acknowledge error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
-
- /* Fetch Last receive data if any */
- if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
- {
- /* Read data from RXDR */
- tmpreg = (uint8_t)hi2c->Instance->RXDR;
- UNUSED(tmpreg);
- }
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
-
- /* Store current volatile hi2c->ErrorCode, misra rule */
- tmperror = hi2c->ErrorCode;
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
- {
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, hi2c->ErrorCode);
- }
- /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
- else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
- {
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_NONE;
-
- if (hi2c->Mode == HAL_I2C_MODE_MEM)
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->MemTxCpltCallback(hi2c);
-#else
- HAL_I2C_MemTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
- }
- else
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->MasterTxCpltCallback(hi2c);
-#else
- HAL_I2C_MasterTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
- }
- }
- /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
- else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
- {
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_NONE;
-
- if (hi2c->Mode == HAL_I2C_MODE_MEM)
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->MemRxCpltCallback(hi2c);
-#else
- HAL_I2C_MemRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
- }
- else
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->MasterRxCpltCallback(hi2c);
-#else
- HAL_I2C_MasterRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
- }
- }
- else
- {
- /* Nothing to do */
- }
-}
-
-/**
- * @brief I2C Slave complete process.
- * @param hi2c I2C handle.
- * @param ITFlags Interrupt flags to handle.
- * @retval None
- */
-static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
- uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
- uint32_t tmpITFlags = ITFlags;
- HAL_I2C_StateTypeDef tmpstate = hi2c->State;
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Disable Interrupts and Store Previous state */
- if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
- {
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
- hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
- }
- else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
- {
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
- hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
- }
- else
- {
- /* Do nothing */
- }
-
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
-
- /* If a DMA is ongoing, Update handle size context */
- if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
- {
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
- if (hi2c->hdmatx != NULL)
- {
- hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
- }
- }
- else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
- {
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
- if (hi2c->hdmarx != NULL)
- {
- hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
- }
- }
- else
- {
- /* Do nothing */
- }
-
- /* Store Last receive data if any */
- if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
- {
- /* Remove RXNE flag on temporary variable as read done */
- tmpITFlags &= ~I2C_FLAG_RXNE;
-
- /* Read data from RXDR */
- *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
-
- /* Increment Buffer pointer */
- hi2c->pBuffPtr++;
-
- if ((hi2c->XferSize > 0U))
- {
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- }
-
- /* All data are not transferred, so set error code accordingly */
- if (hi2c->XferCount != 0U)
- {
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
-
- hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->XferISR = NULL;
-
- if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
- {
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, hi2c->ErrorCode);
-
- /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
- if (hi2c->State == HAL_I2C_STATE_LISTEN)
- {
- /* Call I2C Listen complete process */
- I2C_ITListenCplt(hi2c, tmpITFlags);
- }
- }
- else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
- {
- /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
- I2C_ITSlaveSeqCplt(hi2c);
-
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->ListenCpltCallback(hi2c);
-#else
- HAL_I2C_ListenCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
- }
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
- {
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->SlaveRxCpltCallback(hi2c);
-#else
- HAL_I2C_SlaveRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
- }
- else
- {
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->SlaveTxCpltCallback(hi2c);
-#else
- HAL_I2C_SlaveTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
- }
-}
-
-/**
- * @brief I2C Listen complete process.
- * @param hi2c I2C handle.
- * @param ITFlags Interrupt flags to handle.
- * @retval None
- */
-static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
- /* Reset handle parameters */
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->XferISR = NULL;
-
- /* Store Last receive data if any */
- if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
- {
- /* Read data from RXDR */
- *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
-
- /* Increment Buffer pointer */
- hi2c->pBuffPtr++;
-
- if ((hi2c->XferSize > 0U))
- {
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- }
-
- /* Disable all Interrupts*/
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->ListenCpltCallback(hi2c);
-#else
- HAL_I2C_ListenCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief I2C interrupts error process.
- * @param hi2c I2C handle.
- * @param ErrorCode Error code to handle.
- * @retval None
- */
-static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
-{
- HAL_I2C_StateTypeDef tmpstate = hi2c->State;
- uint32_t tmppreviousstate;
-
- /* Reset handle parameters */
- hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferCount = 0U;
-
- /* Set new error code */
- hi2c->ErrorCode |= ErrorCode;
-
- /* Disable Interrupts */
- if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
- (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
- (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
- {
- /* Disable all interrupts, except interrupts related to LISTEN state */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-
- /* keep HAL_I2C_STATE_LISTEN if set */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->XferISR = I2C_Slave_ISR_IT;
- }
- else
- {
- /* Disable all interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-
- /* If state is an abort treatment on going, don't change state */
- /* This change will be do later */
- if (hi2c->State != HAL_I2C_STATE_ABORT)
- {
- /* Set HAL_I2C_STATE_READY */
- hi2c->State = HAL_I2C_STATE_READY;
- }
- hi2c->XferISR = NULL;
- }
-
- /* Abort DMA TX transfer if any */
- tmppreviousstate = hi2c->PreviousState;
- if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
- (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
- {
- if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
- {
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
- }
-
- if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
- {
- /* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
- hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Abort DMA TX */
- if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
- {
- /* Call Directly XferAbortCallback function in case of error */
- hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
- }
- }
- else
- {
- I2C_TreatErrorCallback(hi2c);
- }
- }
- /* Abort DMA RX transfer if any */
- else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
- (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
- {
- if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
- {
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
- }
-
- if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
- {
- /* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
- hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Abort DMA RX */
- if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
- {
- /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
- hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
- }
- }
- else
- {
- I2C_TreatErrorCallback(hi2c);
- }
- }
- else
- {
- I2C_TreatErrorCallback(hi2c);
- }
-}
-
-/**
- * @brief I2C Error callback treatment.
- * @param hi2c I2C handle.
- * @retval None
- */
-static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
-{
- if (hi2c->State == HAL_I2C_STATE_ABORT)
- {
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->AbortCpltCallback(hi2c);
-#else
- HAL_I2C_AbortCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
- }
- else
- {
- hi2c->PreviousState = I2C_STATE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->ErrorCallback(hi2c);
-#else
- HAL_I2C_ErrorCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
- }
-}
-
-/**
- * @brief I2C Tx data register flush process.
- * @param hi2c I2C handle.
- * @retval None
- */
-static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
-{
- /* If a pending TXIS flag is set */
- /* Write a dummy data in TXDR to clear it */
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
- {
- hi2c->Instance->TXDR = 0x00U;
- }
-
- /* Flush TX register if not empty */
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
- {
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
- }
-}
-
-/**
- * @brief DMA I2C master transmit process complete callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
-{
- /* Derogation MISRAC2012-Rule-11.5 */
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
-
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
- /* If last transfer, enable STOP interrupt */
- if (hi2c->XferCount == 0U)
- {
- /* Enable STOP interrupt */
- I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
- }
- /* else prepare a new DMA transfer and enable TCReload interrupt */
- else
- {
- /* Update Buffer pointer */
- hi2c->pBuffPtr += hi2c->XferSize;
-
- /* Set the XferSize to transfer */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- }
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
- hi2c->XferSize) != HAL_OK)
- {
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
- }
- else
- {
- /* Enable TC interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
- }
- }
-}
-
-/**
- * @brief DMA I2C slave transmit process complete callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
-{
- /* Derogation MISRAC2012-Rule-11.5 */
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
- uint32_t tmpoptions = hi2c->XferOptions;
-
- if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
- {
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
- /* Last Byte is Transmitted */
- /* Call I2C Slave Sequential complete process */
- I2C_ITSlaveSeqCplt(hi2c);
- }
- else
- {
- /* No specific action, Master fully manage the generation of STOP condition */
- /* Mean that this generation can arrive at any time, at the end or during DMA process */
- /* So STOP condition should be manage through Interrupt treatment */
- }
-}
-
-/**
- * @brief DMA I2C master receive process complete callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- /* Derogation MISRAC2012-Rule-11.5 */
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
-
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
- /* If last transfer, enable STOP interrupt */
- if (hi2c->XferCount == 0U)
- {
- /* Enable STOP interrupt */
- I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
- }
- /* else prepare a new DMA transfer and enable TCReload interrupt */
- else
- {
- /* Update Buffer pointer */
- hi2c->pBuffPtr += hi2c->XferSize;
-
- /* Set the XferSize to transfer */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- }
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
- hi2c->XferSize) != HAL_OK)
- {
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
- }
- else
- {
- /* Enable TC interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
- }
- }
-}
-
-/**
- * @brief DMA I2C slave receive process complete callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- /* Derogation MISRAC2012-Rule-11.5 */
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
- uint32_t tmpoptions = hi2c->XferOptions;
-
- if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
- (tmpoptions != I2C_NO_OPTION_FRAME))
- {
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
- /* Call I2C Slave Sequential complete process */
- I2C_ITSlaveSeqCplt(hi2c);
- }
- else
- {
- /* No specific action, Master fully manage the generation of STOP condition */
- /* Mean that this generation can arrive at any time, at the end or during DMA process */
- /* So STOP condition should be manage through Interrupt treatment */
- }
-}
-
-/**
- * @brief DMA I2C communication error callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void I2C_DMAError(DMA_HandleTypeDef *hdma)
-{
- /* Derogation MISRAC2012-Rule-11.5 */
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
-
- /* Disable Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
-}
-
-/**
- * @brief DMA I2C communication abort callback
- * (To be called at end of DMA Abort procedure).
- * @param hdma DMA handle.
- * @retval None
- */
-static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
-{
- /* Derogation MISRAC2012-Rule-11.5 */
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
-
- /* Reset AbortCpltCallback */
- if (hi2c->hdmatx != NULL)
- {
- hi2c->hdmatx->XferAbortCallback = NULL;
- }
- if (hi2c->hdmarx != NULL)
- {
- hi2c->hdmarx->XferAbortCallback = NULL;
- }
-
- I2C_TreatErrorCallback(hi2c);
-}
-
-/**
- * @brief This function handles I2C Communication Timeout. It waits
- * until a flag is no longer in the specified status.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Flag Specifies the I2C flag to check.
- * @param Status The actual Flag status (SET or RESET).
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
- uint32_t Timeout, uint32_t Tickstart)
-{
- while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
- {
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
- {
- if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
- uint32_t Tickstart)
-{
- while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
- {
- /* Check if an error is detected */
- if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
- {
- if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
- uint32_t Tickstart)
-{
- while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
- {
- /* Check if an error is detected */
- if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Check for the Timeout */
- if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
- uint32_t Tickstart)
-{
- while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
- {
- /* Check if an error is detected */
- if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Check if a STOPF is detected */
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
- {
- /* Check if an RXNE is pending */
- /* Store Last receive data if any */
- if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
- {
- /* Return HAL_OK */
- /* The Reading of data from RXDR will be done in caller function */
- return HAL_OK;
- }
- else
- {
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
- {
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- hi2c->ErrorCode = HAL_I2C_ERROR_AF;
- }
- else
- {
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
- }
-
- /* Check for the Timeout */
- if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief This function handles errors detection during an I2C Communication.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t itflag = hi2c->Instance->ISR;
- uint32_t error_code = 0;
- uint32_t tickstart = Tickstart;
- uint32_t tmp1;
- HAL_I2C_ModeTypeDef tmp2;
-
- if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
- {
- /* Clear NACKF Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Wait until STOP Flag is set or timeout occurred */
- /* AutoEnd should be initiate after AF */
- while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
- {
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
- {
- if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
- {
- tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
- tmp2 = hi2c->Mode;
-
- /* In case of I2C still busy, try to regenerate a STOP manually */
- if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
- (tmp1 != I2C_CR2_STOP) && \
- (tmp2 != HAL_I2C_MODE_SLAVE))
- {
- /* Generate Stop */
- hi2c->Instance->CR2 |= I2C_CR2_STOP;
-
- /* Update Tick with new reference */
- tickstart = HAL_GetTick();
- }
-
- while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
- {
- /* Check for the Timeout */
- if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- status = HAL_ERROR;
- }
- }
- }
- }
- }
-
- /* In case STOP Flag is detected, clear it */
- if (status == HAL_OK)
- {
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- }
-
- error_code |= HAL_I2C_ERROR_AF;
-
- status = HAL_ERROR;
- }
-
- /* Refresh Content of Status register */
- itflag = hi2c->Instance->ISR;
-
- /* Then verify if an additional errors occurs */
- /* Check if a Bus error occurred */
- if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
- {
- error_code |= HAL_I2C_ERROR_BERR;
-
- /* Clear BERR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
-
- status = HAL_ERROR;
- }
-
- /* Check if an Over-Run/Under-Run error occurred */
- if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
- {
- error_code |= HAL_I2C_ERROR_OVR;
-
- /* Clear OVR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
-
- status = HAL_ERROR;
- }
-
- /* Check if an Arbitration Loss error occurred */
- if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
- {
- error_code |= HAL_I2C_ERROR_ARLO;
-
- /* Clear ARLO flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
-
- status = HAL_ERROR;
- }
-
- if (status != HAL_OK)
- {
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->ErrorCode |= error_code;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- }
-
- return status;
-}
-
-/**
- * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
- * @param hi2c I2C handle.
- * @param DevAddress Specifies the slave address to be programmed.
- * @param Size Specifies the number of bytes to be programmed.
- * This parameter must be a value between 0 and 255.
- * @param Mode New state of the I2C START condition generation.
- * This parameter can be one of the following values:
- * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
- * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
- * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
- * @param Request New state of the I2C START condition generation.
- * This parameter can be one of the following values:
- * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
- * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
- * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
- * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
- * @retval None
- */
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
- uint32_t Request)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
- assert_param(IS_TRANSFER_MODE(Mode));
- assert_param(IS_TRANSFER_REQUEST(Request));
-
- /* Declaration of tmp to prevent undefined behavior of volatile usage */
- uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
- (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
- (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
-
- /* update CR2 register */
- MODIFY_REG(hi2c->Instance->CR2, \
- ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
- (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
- I2C_CR2_START | I2C_CR2_STOP)), tmp);
-}
-
-/**
- * @brief Manage the enabling of Interrupts.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
- * @retval None
- */
-static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
-{
- uint32_t tmpisr = 0U;
-
- if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
- (hi2c->XferISR == I2C_Slave_ISR_DMA))
- {
- if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
- {
- /* Enable ERR, STOP, NACK and ADDR interrupts */
- tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
- }
-
- if (InterruptRequest == I2C_XFER_ERROR_IT)
- {
- /* Enable ERR and NACK interrupts */
- tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
- }
-
- if (InterruptRequest == I2C_XFER_CPLT_IT)
- {
- /* Enable STOP interrupts */
- tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
- }
-
- if (InterruptRequest == I2C_XFER_RELOAD_IT)
- {
- /* Enable TC interrupts */
- tmpisr |= I2C_IT_TCI;
- }
- }
- else
- {
- if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
- {
- /* Enable ERR, STOP, NACK, and ADDR interrupts */
- tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
- }
-
- if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
- {
- /* Enable ERR, TC, STOP, NACK and RXI interrupts */
- tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
- }
-
- if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
- {
- /* Enable ERR, TC, STOP, NACK and TXI interrupts */
- tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
- }
-
- if (InterruptRequest == I2C_XFER_CPLT_IT)
- {
- /* Enable STOP interrupts */
- tmpisr |= I2C_IT_STOPI;
- }
- }
-
- /* Enable interrupts only at the end */
- /* to avoid the risk of I2C interrupt handle execution before */
- /* all interrupts requested done */
- __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
-}
-
-/**
- * @brief Manage the disabling of Interrupts.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
- * @retval None
- */
-static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
-{
- uint32_t tmpisr = 0U;
-
- if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
- {
- /* Disable TC and TXI interrupts */
- tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
-
- if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
- {
- /* Disable NACK and STOP interrupts */
- tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
- }
- }
-
- if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
- {
- /* Disable TC and RXI interrupts */
- tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
-
- if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
- {
- /* Disable NACK and STOP interrupts */
- tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
- }
- }
-
- if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
- {
- /* Disable ADDR, NACK and STOP interrupts */
- tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
- }
-
- if (InterruptRequest == I2C_XFER_ERROR_IT)
- {
- /* Enable ERR and NACK interrupts */
- tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
- }
-
- if (InterruptRequest == I2C_XFER_CPLT_IT)
- {
- /* Enable STOP interrupts */
- tmpisr |= I2C_IT_STOPI;
- }
-
- if (InterruptRequest == I2C_XFER_RELOAD_IT)
- {
- /* Enable TC interrupts */
- tmpisr |= I2C_IT_TCI;
- }
-
- /* Disable interrupts only at the end */
- /* to avoid a breaking situation like at "t" time */
- /* all disable interrupts request are not done */
- __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
-}
-
-/**
- * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
- * @param hi2c I2C handle.
- * @retval None
- */
-static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
-{
- /* if user set XferOptions to I2C_OTHER_FRAME */
- /* it request implicitly to generate a restart condition */
- /* set XferOptions to I2C_FIRST_FRAME */
- if (hi2c->XferOptions == I2C_OTHER_FRAME)
- {
- hi2c->XferOptions = I2C_FIRST_FRAME;
- }
- /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
- /* it request implicitly to generate a restart condition */
- /* then generate a stop condition at the end of transfer */
- /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
- else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
- {
- hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
- }
- else
- {
- /* Nothing to do */
- }
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_I2C_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c
deleted file mode 100644
index f111b69..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c
+++ /dev/null
@@ -1,368 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_i2c_ex.c
- * @author MCD Application Team
- * @brief I2C Extended HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of I2C Extended peripheral:
- * + Filter Mode Functions
- * + WakeUp Mode Functions
- * + FastModePlus Functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### I2C peripheral Extended features #####
- ==============================================================================
-
- [..] Comparing to other previous devices, the I2C interface for STM32L4xx
- devices contains the following additional features
-
- (+) Possibility to disable or enable Analog Noise Filter
- (+) Use of a configured Digital Noise Filter
- (+) Disable or enable wakeup from Stop mode(s)
- (+) Disable or enable Fast Mode Plus
-
- ##### How to use this driver #####
- ==============================================================================
- [..] This driver provides functions to configure Noise Filter and Wake Up Feature
- (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
- (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
- (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
- (++) HAL_I2CEx_EnableWakeUp()
- (++) HAL_I2CEx_DisableWakeUp()
- (#) Configure the enable or disable of fast mode plus driving capability using the functions :
- (++) HAL_I2CEx_EnableFastModePlus()
- (++) HAL_I2CEx_DisableFastModePlus()
- @endverbatim
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup I2CEx I2CEx
- * @brief I2C Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_I2C_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
- * @{
- */
-
-/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
- * @brief Filter Mode Functions
- *
-@verbatim
- ===============================================================================
- ##### Filter Mode Functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure Noise Filters
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure I2C Analog noise filter.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2Cx peripheral.
- * @param AnalogFilter New state of the Analog filter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
- assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
- /* Reset I2Cx ANOFF bit */
- hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
-
- /* Set analog filter bit*/
- hi2c->Instance->CR1 |= AnalogFilter;
-
- __HAL_I2C_ENABLE(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Configure I2C Digital noise filter.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2Cx peripheral.
- * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
-{
- uint32_t tmpreg;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
- assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
- /* Get the old register value */
- tmpreg = hi2c->Instance->CR1;
-
- /* Reset I2Cx DNF bits [11:8] */
- tmpreg &= ~(I2C_CR1_DNF);
-
- /* Set I2Cx DNF coefficient */
- tmpreg |= DigitalFilter << 8U;
-
- /* Store the new register value */
- hi2c->Instance->CR1 = tmpreg;
-
- __HAL_I2C_ENABLE(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
- * @brief WakeUp Mode Functions
- *
-@verbatim
- ===============================================================================
- ##### WakeUp Mode Functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure Wake Up Feature
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enable I2C wakeup from Stop mode(s).
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2Cx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
-{
- /* Check the parameters */
- assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
- /* Enable wakeup from stop mode */
- hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
-
- __HAL_I2C_ENABLE(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Disable I2C wakeup from Stop mode(s).
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2Cx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
-{
- /* Check the parameters */
- assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
- /* Enable wakeup from stop mode */
- hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
-
- __HAL_I2C_ENABLE(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
- * @brief Fast Mode Plus Functions
- *
-@verbatim
- ===============================================================================
- ##### Fast Mode Plus Functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure Fast Mode Plus
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enable the I2C fast mode plus driving capability.
- * @param ConfigFastModePlus Selects the pin.
- * This parameter can be one of the @ref I2CEx_FastModePlus values
- * @note For I2C1, fast mode plus driving capability can be enabled on all selected
- * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
- * on each one of the following pins PB6, PB7, PB8 and PB9.
- * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
- * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
- * @note For all I2C2 pins fast mode plus driving capability can be enabled
- * only by using I2C_FASTMODEPLUS_I2C2 parameter.
- * @note For all I2C3 pins fast mode plus driving capability can be enabled
- * only by using I2C_FASTMODEPLUS_I2C3 parameter.
- * @note For all I2C4 pins fast mode plus driving capability can be enabled
- * only by using I2C_FASTMODEPLUS_I2C4 parameter.
- * @retval None
- */
-void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
-{
- /* Check the parameter */
- assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
-
- /* Enable SYSCFG clock */
- __HAL_RCC_SYSCFG_CLK_ENABLE();
-
- /* Enable fast mode plus driving capability for selected pin */
- SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
-}
-
-/**
- * @brief Disable the I2C fast mode plus driving capability.
- * @param ConfigFastModePlus Selects the pin.
- * This parameter can be one of the @ref I2CEx_FastModePlus values
- * @note For I2C1, fast mode plus driving capability can be disabled on all selected
- * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
- * on each one of the following pins PB6, PB7, PB8 and PB9.
- * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
- * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
- * @note For all I2C2 pins fast mode plus driving capability can be disabled
- * only by using I2C_FASTMODEPLUS_I2C2 parameter.
- * @note For all I2C3 pins fast mode plus driving capability can be disabled
- * only by using I2C_FASTMODEPLUS_I2C3 parameter.
- * @note For all I2C4 pins fast mode plus driving capability can be disabled
- * only by using I2C_FASTMODEPLUS_I2C4 parameter.
- * @retval None
- */
-void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
-{
- /* Check the parameter */
- assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
-
- /* Enable SYSCFG clock */
- __HAL_RCC_SYSCFG_CLK_ENABLE();
-
- /* Disable fast mode plus driving capability for selected pin */
- CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
-}
-/**
- * @}
- */
-/**
- * @}
- */
-
-#endif /* HAL_I2C_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c
deleted file mode 100644
index 8638eec..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c
+++ /dev/null
@@ -1,658 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_pwr.c
- * @author MCD Application Team
- * @brief PWR HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Power Controller (PWR) peripheral:
- * + Initialization/de-initialization functions
- * + Peripheral Control functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup PWR PWR
- * @brief PWR HAL module driver
- * @{
- */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup PWR_Private_Defines PWR Private Defines
- * @{
- */
-
-/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
- * @{
- */
-#define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */
-#define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */
-#define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */
-#define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Functions PWR Exported Functions
- * @{
- */
-
-/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
- * @retval None
- */
-void HAL_PWR_DeInit(void)
-{
- __HAL_RCC_PWR_FORCE_RESET();
- __HAL_RCC_PWR_RELEASE_RESET();
-}
-
-/**
- * @brief Enable access to the backup domain
- * (RTC registers, RTC backup data registers).
- * @note After reset, the backup domain is protected against
- * possible unwanted write accesses.
- * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
- * In order to set or modify the RTC clock, the backup domain access must be
- * disabled.
- * @note LSEON bit that switches on and off the LSE crystal belongs as well to the
- * back-up domain.
- * @retval None
- */
-void HAL_PWR_EnableBkUpAccess(void)
-{
- SET_BIT(PWR->CR1, PWR_CR1_DBP);
-}
-
-/**
- * @brief Disable access to the backup domain
- * (RTC registers, RTC backup data registers).
- * @retval None
- */
-void HAL_PWR_DisableBkUpAccess(void)
-{
- CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
-}
-
-
-
-
-/**
- * @}
- */
-
-
-
-/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
- * @brief Low Power modes configuration functions
- *
-@verbatim
-
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
-
- [..]
- *** PVD configuration ***
- =========================
- [..]
- (+) The PVD is used to monitor the VDD power supply by comparing it to a
- threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
-
- (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
- than the PVD threshold. This event is internally connected to the EXTI
- line16 and can generate an interrupt if enabled. This is done through
- __HAL_PVD_EXTI_ENABLE_IT() macro.
- (+) The PVD is stopped in Standby mode.
-
-
- *** WakeUp pin configuration ***
- ================================
- [..]
- (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
- The polarity of these pins can be set to configure event detection on high
- level (rising edge) or low level (falling edge).
-
-
-
- *** Low Power modes configuration ***
- =====================================
- [..]
- The devices feature 8 low-power modes:
- (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
- (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
- (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
- (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
- (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
- (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
- (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
- (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
- (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
-
-
- *** Low-power run mode ***
- ==========================
- [..]
- (+) Entry: (from main run mode)
- (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
-
- (+) Exit:
- (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
- then can the system clock frequency be increased above 2 MHz.
-
-
- *** Sleep mode / Low-power sleep mode ***
- =========================================
- [..]
- (+) Entry:
- The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
- in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
- (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
- (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
- In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
- (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
- (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-
- (+) WFI Exit:
- (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
- controller (NVIC) or any wake-up event.
-
- (+) WFE Exit:
- (++) Any wake-up event such as an EXTI line configured in event mode.
-
- [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
- the MCU is in Low-power Run mode.
-
- *** Stop 0, Stop 1 and Stop 2 modes ***
- ===============================
- [..]
- (+) Entry:
- The Stop 0, Stop 1 or Stop 2 modes are entered through the following API's:
- (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
- (++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
- (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
- (++) PWR_MAINREGULATOR_ON
- (++) PWR_LOWPOWERREGULATOR_ON
- (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
- (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
- (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
-
- (+) WFI Exit:
- (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
- (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
- when programmed in wakeup mode.
- (+) WFE Exit:
- (++) Any EXTI Line (Internal or External) configured in Event mode.
-
- [..]
- When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
- depending on the LPR bit setting.
- When exiting Stop 2 mode, the MCU is in Run mode.
-
- *** Standby mode ***
- ====================
- [..]
- The Standby mode offers two options:
- (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
- SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
- and Standby circuitry.
- (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
- SRAM and register contents are lost except for the RTC registers, RTC backup registers
- and Standby circuitry.
-
- (++) Entry:
- (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
- SRAM1 and register contents are lost except for registers in the Backup domain and
- Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
- To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
- to set RRS bit.
-
- (++) Exit:
- (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
- external reset in NRST pin, IWDG reset.
-
- [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset.
-
-
- *** Shutdown mode ***
- ======================
- [..]
- In Shutdown mode,
- voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
- SRAM and registers contents are lost except for backup domain registers.
-
- (+) Entry:
- The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.
-
- (+) Exit:
- (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
- external reset in NRST pin.
-
- [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
-
-
- *** Auto-wakeup (AWU) from low-power mode ***
- =============================================
- [..]
- The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
- Wakeup event, a tamper event or a time-stamp event, without depending on
- an external interrupt (Auto-wakeup mode).
-
- (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
-
-
- (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
- configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
-
- (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
- is necessary to configure the RTC to detect the tamper or time stamp event using the
- HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
-
- (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
- configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
-
-@endverbatim
- * @{
- */
-
-
-
-/**
- * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
- * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD
- * configuration information.
- * @note Refer to the electrical characteristics of your device datasheet for
- * more details about the voltage thresholds corresponding to each
- * detection level.
- * @retval None
- */
-HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
-{
- /* Check the parameters */
- assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
- assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
-
- /* Set PLS bits according to PVDLevel value */
- MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
-
- /* Clear any previous config. Keep it clear if no event or IT mode is selected */
- __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
- __HAL_PWR_PVD_EXTI_DISABLE_IT();
- __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
- __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
-
- /* Configure interrupt mode */
- if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_IT();
- }
-
- /* Configure event mode */
- if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
- }
-
- /* Configure the edge */
- if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
- }
-
- if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
- }
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Enable the Power Voltage Detector (PVD).
- * @retval None
- */
-void HAL_PWR_EnablePVD(void)
-{
- SET_BIT(PWR->CR2, PWR_CR2_PVDE);
-}
-
-/**
- * @brief Disable the Power Voltage Detector (PVD).
- * @retval None
- */
-void HAL_PWR_DisablePVD(void)
-{
- CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
-}
-
-
-
-
-/**
- * @brief Enable the WakeUp PINx functionality.
- * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
- * This parameter can be one of the following legacy values which set the default polarity
- * i.e. detection on high level (rising edge):
- * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
- *
- * or one of the following value where the user can explicitly specify the enabled pin and
- * the chosen polarity:
- * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
- * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
- * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
- * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
- * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
- * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
- * @retval None
- */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
-{
- assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
-
- /* Specifies the Wake-Up pin polarity for the event detection
- (rising or falling edge) */
- MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
-
- /* Enable wake-up pin */
- SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
-
-
-}
-
-/**
- * @brief Disable the WakeUp PINx functionality.
- * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
- * This parameter can be one of the following values:
- * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
- * @retval None
- */
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
-{
- assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
-
- CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
-}
-
-
-/**
- * @brief Enter Sleep or Low-power Sleep mode.
- * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
- * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
- * This parameter can be one of the following values:
- * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
- * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
- * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
- * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
- * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
- * Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
- * Additionally, the clock frequency must be reduced below 2 MHz.
- * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
- * be done before calling HAL_PWR_EnterSLEEPMode() API.
- * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
- * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
- * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
- * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
- * @note When WFI entry is used, tick interrupt have to be disabled if not desired as
- * the interrupt wake up source.
- * @retval None
- */
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
-{
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(Regulator));
- assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
-
- /* Set Regulator parameter */
- if (Regulator == PWR_MAINREGULATOR_ON)
- {
- /* If in low-power run mode at this point, exit it */
- if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
- {
- if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
- {
- return ;
- }
- }
- /* Regulator now in main mode. */
- }
- else
- {
- /* If in run mode, first move to low-power run mode.
- The system clock frequency must be below 2 MHz at this point. */
- if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
- {
- HAL_PWREx_EnableLowPowerRunMode();
- }
- }
-
- /* Clear SLEEPDEEP bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
- /* Select SLEEP mode entry -------------------------------------------------*/
- if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __SEV();
- __WFE();
- __WFE();
- }
-
-}
-
-
-/**
- * @brief Enter Stop mode
- * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
- * on devices where only "Stop mode" is mentioned with main or low power regulator ON.
- * @note In Stop mode, all I/O pins keep the same state as in Run mode.
- * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
- * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
- * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
- * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
- * only to the peripheral requesting it.
- * SRAM1, SRAM2 and register contents are preserved.
- * The BOR is available.
- * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
- * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
- * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
- * is set; the MSI oscillator is selected if STOPWUCK is cleared.
- * @note When the voltage regulator operates in low power mode (Stop 1), an additional
- * startup delay is incurred when waking up.
- * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
- * is higher although the startup time is reduced.
- * @param Regulator: Specifies the regulator state in Stop mode.
- * This parameter can be one of the following values:
- * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
- * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
- * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
- * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
- * @retval None
- */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
-{
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(Regulator));
-
- if(Regulator == PWR_LOWPOWERREGULATOR_ON)
- {
- HAL_PWREx_EnterSTOP1Mode(STOPEntry);
- }
- else
- {
- HAL_PWREx_EnterSTOP0Mode(STOPEntry);
- }
-}
-
-/**
- * @brief Enter Standby mode.
- * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched
- * off. The voltage regulator is disabled, except when SRAM2 content is preserved
- * in which case the regulator is in low-power mode.
- * SRAM1 and register contents are lost except for registers in the Backup domain and
- * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
- * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
- * to set RRS bit.
- * The BOR is available.
- * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
- * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
- * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
- * same.
- * These states are effective in Standby mode only if APC bit is set through
- * HAL_PWREx_EnablePullUpPullDownConfig() API.
- * @retval None
- */
-void HAL_PWR_EnterSTANDBYMode(void)
-{
- /* Set Stand-by mode */
- MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
-/* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM)
- __force_stores();
-#endif
- /* Request Wait For Interrupt */
- __WFI();
-}
-
-
-
-/**
- * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
- * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
- * re-enters SLEEP mode when an interruption handling is over.
- * Setting this bit is useful when the processor is expected to run only on
- * interruptions handling.
- * @retval None
- */
-void HAL_PWR_EnableSleepOnExit(void)
-{
- /* Set SLEEPONEXIT bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-
-/**
- * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
- * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
- * re-enters SLEEP mode when an interruption handling is over.
- * @retval None
- */
-void HAL_PWR_DisableSleepOnExit(void)
-{
- /* Clear SLEEPONEXIT bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-
-
-/**
- * @brief Enable CORTEX M4 SEVONPEND bit.
- * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
- * WFE to wake up when an interrupt moves from inactive to pended.
- * @retval None
- */
-void HAL_PWR_EnableSEVOnPend(void)
-{
- /* Set SEVONPEND bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-
-/**
- * @brief Disable CORTEX M4 SEVONPEND bit.
- * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
- * WFE to wake up when an interrupt moves from inactive to pended.
- * @retval None
- */
-void HAL_PWR_DisableSEVOnPend(void)
-{
- /* Clear SEVONPEND bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-
-
-
-
-/**
- * @brief PWR PVD interrupt callback
- * @retval None
- */
-__weak void HAL_PWR_PVDCallback(void)
-{
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_PWR_PVDCallback can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c
deleted file mode 100644
index 0b6eb2f..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c
+++ /dev/null
@@ -1,1474 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_pwr_ex.c
- * @author MCD Application Team
- * @brief Extended PWR HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Power Controller (PWR) peripheral:
- * + Extended Initialization and de-initialization functions
- * + Extended Peripheral Control functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup PWREx PWREx
- * @brief PWR Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
-#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */
-#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
-#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */
-#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
-#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x00000003) /* PH0/PH1 */
-#elif defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000FFFF) /* PH0..PH15 */
-#endif
-
-#if defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define PWR_PORTI_AVAILABLE_PINS ((uint32_t)0x00000FFF) /* PI0..PI11 */
-#endif
-
-/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
- * @{
- */
-
-/** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
- * @{
- */
-#define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */
-#define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */
-#define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */
-#define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */
-/**
- * @}
- */
-
-/** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
- * @{
- */
-#define PWR_FLAG_SETTING_DELAY_US 50UL /*!< Time out value for REGLPF and VOSF flags setting */
-/**
- * @}
- */
-
-
-
-/**
- * @}
- */
-
-
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
- * @{
- */
-
-/** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
- * @brief Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Extended Peripheral Initialization and de-initialization functions #####
- ===============================================================================
- [..]
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Return Voltage Scaling Range.
- * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
- * or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
- */
-uint32_t HAL_PWREx_GetVoltageRange(void)
-{
-#if defined(PWR_CR5_R1MODE)
- if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
- {
- return PWR_REGULATOR_VOLTAGE_SCALE2;
- }
- else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE)
- {
- /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */
- return PWR_REGULATOR_VOLTAGE_SCALE1;
- }
- else
- {
- return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
- }
-#else
- return (PWR->CR1 & PWR_CR1_VOS);
-#endif
-}
-
-
-
-/**
- * @brief Configure the main internal regulator output voltage.
- * @param VoltageScaling specifies the regulator output voltage to achieve
- * a tradeoff between performance and power consumption.
- * This parameter can be one of the following values:
- @if STM32L4S9xx
- * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode,
- * typical output voltage at 1.2 V,
- * system frequency up to 120 MHz.
- @endif
- * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
- * typical output voltage at 1.2 V,
- * system frequency up to 80 MHz.
- * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
- * typical output voltage at 1.0 V,
- * system frequency up to 26 MHz.
- * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
- * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
- * When moving from Range 2 to Range 1, the system frequency can be increased to
- * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API. For
- * some devices, the system frequency can be increased up to 120 MHz.
- * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be
- * cleared before returning the status. If the flag is not cleared within
- * 50 microseconds, HAL_TIMEOUT status is reported.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
-{
- uint32_t wait_loop_index;
-
- assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
-
-#if defined(PWR_CR5_R1MODE)
- if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)
- {
- /* If current range is range 2 */
- if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
- {
- /* Make sure Range 1 Boost is enabled */
- CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
-
- /* Set Range 1 */
- MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
-
- /* Wait until VOSF is cleared */
- wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1;
- while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
- {
- wait_loop_index--;
- }
- if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
- {
- return HAL_TIMEOUT;
- }
- }
- /* If current range is range 1 normal or boost mode */
- else
- {
- /* Enable Range 1 Boost (no issue if bit already reset) */
- CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
- }
- }
- else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
- {
- /* If current range is range 2 */
- if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
- {
- /* Make sure Range 1 Boost is disabled */
- SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
-
- /* Set Range 1 */
- MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
-
- /* Wait until VOSF is cleared */
- wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1;
- while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
- {
- wait_loop_index--;
- }
- if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
- {
- return HAL_TIMEOUT;
- }
- }
- /* If current range is range 1 normal or boost mode */
- else
- {
- /* Disable Range 1 Boost (no issue if bit already set) */
- SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
- }
- }
- else
- {
- /* Set Range 2 */
- MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
- /* No need to wait for VOSF to be cleared for this transition */
- /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */
- }
-
-#else
-
- /* If Set Range 1 */
- if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
- {
- if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
- {
- /* Set Range 1 */
- MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
-
- /* Wait until VOSF is cleared */
- wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
- while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
- {
- wait_loop_index--;
- }
- if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
- {
- /* Set Range 2 */
- MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
- /* No need to wait for VOSF to be cleared for this transition */
- }
- }
-#endif
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Enable battery charging.
- * When VDD is present, charge the external battery on VBAT through an internal resistor.
- * @param ResistorSelection specifies the resistor impedance.
- * This parameter can be one of the following values:
- * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
- * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
- * @retval None
- */
-void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
-{
- assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
-
- /* Specify resistor selection */
- MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
-
- /* Enable battery charging */
- SET_BIT(PWR->CR4, PWR_CR4_VBE);
-}
-
-
-/**
- * @brief Disable battery charging.
- * @retval None
- */
-void HAL_PWREx_DisableBatteryCharging(void)
-{
- CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
-}
-
-
-#if defined(PWR_CR2_USV)
-/**
- * @brief Enable VDDUSB supply.
- * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
- * @retval None
- */
-void HAL_PWREx_EnableVddUSB(void)
-{
- SET_BIT(PWR->CR2, PWR_CR2_USV);
-}
-
-
-/**
- * @brief Disable VDDUSB supply.
- * @retval None
- */
-void HAL_PWREx_DisableVddUSB(void)
-{
- CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
-}
-#endif /* PWR_CR2_USV */
-
-#if defined(PWR_CR2_IOSV)
-/**
- * @brief Enable VDDIO2 supply.
- * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present.
- * @retval None
- */
-void HAL_PWREx_EnableVddIO2(void)
-{
- SET_BIT(PWR->CR2, PWR_CR2_IOSV);
-}
-
-
-/**
- * @brief Disable VDDIO2 supply.
- * @retval None
- */
-void HAL_PWREx_DisableVddIO2(void)
-{
- CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
-}
-#endif /* PWR_CR2_IOSV */
-
-
-/**
- * @brief Enable Internal Wake-up Line.
- * @retval None
- */
-void HAL_PWREx_EnableInternalWakeUpLine(void)
-{
- SET_BIT(PWR->CR3, PWR_CR3_EIWF);
-}
-
-
-/**
- * @brief Disable Internal Wake-up Line.
- * @retval None
- */
-void HAL_PWREx_DisableInternalWakeUpLine(void)
-{
- CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
-}
-
-
-
-/**
- * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
- * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in
- * pull-up state in Standby and Shutdown modes.
- * @note This state is effective in Standby and Shutdown modes only if APC bit
- * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
- * @note The configuration is lost when exiting the Shutdown mode due to the
- * power-on reset, maintained when exiting the Standby mode.
- * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
- * PDy bit of PWR_PDCRx register is cleared unless it is reserved.
- * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input
- * parameter at the same time are set.
- * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
- * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
- * @param GPIONumber Specify the I/O pins numbers.
- * This parameter can be one of the following values:
- * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
- * I/O pins are available) or the logical OR of several of them to set
- * several bits for a given port in a single API call.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- assert_param(IS_PWR_GPIO(GPIO));
- assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
-
- switch (GPIO)
- {
- case PWR_GPIO_A:
- SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
- CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
- break;
- case PWR_GPIO_B:
- SET_BIT(PWR->PUCRB, GPIONumber);
- CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
- break;
- case PWR_GPIO_C:
- SET_BIT(PWR->PUCRC, GPIONumber);
- CLEAR_BIT(PWR->PDCRC, GPIONumber);
- break;
-#if defined(GPIOD)
- case PWR_GPIO_D:
- SET_BIT(PWR->PUCRD, GPIONumber);
- CLEAR_BIT(PWR->PDCRD, GPIONumber);
- break;
-#endif
-#if defined(GPIOE)
- case PWR_GPIO_E:
- SET_BIT(PWR->PUCRE, GPIONumber);
- CLEAR_BIT(PWR->PDCRE, GPIONumber);
- break;
-#endif
-#if defined(GPIOF)
- case PWR_GPIO_F:
- SET_BIT(PWR->PUCRF, GPIONumber);
- CLEAR_BIT(PWR->PDCRF, GPIONumber);
- break;
-#endif
-#if defined(GPIOG)
- case PWR_GPIO_G:
- SET_BIT(PWR->PUCRG, GPIONumber);
- CLEAR_BIT(PWR->PDCRG, GPIONumber);
- break;
-#endif
- case PWR_GPIO_H:
- SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
-#if defined (STM32L496xx) || defined (STM32L4A6xx)
- CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));
-#else
- CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
-#endif
- break;
-#if defined(GPIOI)
- case PWR_GPIO_I:
- SET_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
- CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
- break;
-#endif
- default:
- status = HAL_ERROR;
- break;
- }
-
- return status;
-}
-
-
-/**
- * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
- * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
- * in pull-up state in Standby and Shutdown modes.
- * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input
- * parameter at the same time are reset.
- * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
- * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
- * @param GPIONumber Specify the I/O pins numbers.
- * This parameter can be one of the following values:
- * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
- * I/O pins are available) or the logical OR of several of them to reset
- * several bits for a given port in a single API call.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- assert_param(IS_PWR_GPIO(GPIO));
- assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
-
- switch (GPIO)
- {
- case PWR_GPIO_A:
- CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
- break;
- case PWR_GPIO_B:
- CLEAR_BIT(PWR->PUCRB, GPIONumber);
- break;
- case PWR_GPIO_C:
- CLEAR_BIT(PWR->PUCRC, GPIONumber);
- break;
-#if defined(GPIOD)
- case PWR_GPIO_D:
- CLEAR_BIT(PWR->PUCRD, GPIONumber);
- break;
-#endif
-#if defined(GPIOE)
- case PWR_GPIO_E:
- CLEAR_BIT(PWR->PUCRE, GPIONumber);
- break;
-#endif
-#if defined(GPIOF)
- case PWR_GPIO_F:
- CLEAR_BIT(PWR->PUCRF, GPIONumber);
- break;
-#endif
-#if defined(GPIOG)
- case PWR_GPIO_G:
- CLEAR_BIT(PWR->PUCRG, GPIONumber);
- break;
-#endif
- case PWR_GPIO_H:
- CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
- break;
-#if defined(GPIOI)
- case PWR_GPIO_I:
- CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
- break;
-#endif
- default:
- status = HAL_ERROR;
- break;
- }
-
- return status;
-}
-
-
-
-/**
- * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
- * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in
- * pull-down state in Standby and Shutdown modes.
- * @note This state is effective in Standby and Shutdown modes only if APC bit
- * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
- * @note The configuration is lost when exiting the Shutdown mode due to the
- * power-on reset, maintained when exiting the Standby mode.
- * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
- * PUy bit of PWR_PUCRx register is cleared unless it is reserved.
- * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input
- * parameter at the same time are set.
- * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
- * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
- * @param GPIONumber Specify the I/O pins numbers.
- * This parameter can be one of the following values:
- * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
- * I/O pins are available) or the logical OR of several of them to set
- * several bits for a given port in a single API call.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- assert_param(IS_PWR_GPIO(GPIO));
- assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
-
- switch (GPIO)
- {
- case PWR_GPIO_A:
- SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
- CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
- break;
- case PWR_GPIO_B:
- SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
- CLEAR_BIT(PWR->PUCRB, GPIONumber);
- break;
- case PWR_GPIO_C:
- SET_BIT(PWR->PDCRC, GPIONumber);
- CLEAR_BIT(PWR->PUCRC, GPIONumber);
- break;
-#if defined(GPIOD)
- case PWR_GPIO_D:
- SET_BIT(PWR->PDCRD, GPIONumber);
- CLEAR_BIT(PWR->PUCRD, GPIONumber);
- break;
-#endif
-#if defined(GPIOE)
- case PWR_GPIO_E:
- SET_BIT(PWR->PDCRE, GPIONumber);
- CLEAR_BIT(PWR->PUCRE, GPIONumber);
- break;
-#endif
-#if defined(GPIOF)
- case PWR_GPIO_F:
- SET_BIT(PWR->PDCRF, GPIONumber);
- CLEAR_BIT(PWR->PUCRF, GPIONumber);
- break;
-#endif
-#if defined(GPIOG)
- case PWR_GPIO_G:
- SET_BIT(PWR->PDCRG, GPIONumber);
- CLEAR_BIT(PWR->PUCRG, GPIONumber);
- break;
-#endif
- case PWR_GPIO_H:
-#if defined (STM32L496xx) || defined (STM32L4A6xx)
- SET_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));
-#else
- SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
-#endif
- CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
- break;
-#if defined(GPIOI)
- case PWR_GPIO_I:
- SET_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
- CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
- break;
-#endif
- default:
- status = HAL_ERROR;
- break;
- }
-
- return status;
-}
-
-
-/**
- * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
- * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
- * in pull-down state in Standby and Shutdown modes.
- * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input
- * parameter at the same time are reset.
- * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
- * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
- * @param GPIONumber Specify the I/O pins numbers.
- * This parameter can be one of the following values:
- * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
- * I/O pins are available) or the logical OR of several of them to reset
- * several bits for a given port in a single API call.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- assert_param(IS_PWR_GPIO(GPIO));
- assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
-
- switch (GPIO)
- {
- case PWR_GPIO_A:
- CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
- break;
- case PWR_GPIO_B:
- CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
- break;
- case PWR_GPIO_C:
- CLEAR_BIT(PWR->PDCRC, GPIONumber);
- break;
-#if defined(GPIOD)
- case PWR_GPIO_D:
- CLEAR_BIT(PWR->PDCRD, GPIONumber);
- break;
-#endif
-#if defined(GPIOE)
- case PWR_GPIO_E:
- CLEAR_BIT(PWR->PDCRE, GPIONumber);
- break;
-#endif
-#if defined(GPIOF)
- case PWR_GPIO_F:
- CLEAR_BIT(PWR->PDCRF, GPIONumber);
- break;
-#endif
-#if defined(GPIOG)
- case PWR_GPIO_G:
- CLEAR_BIT(PWR->PDCRG, GPIONumber);
- break;
-#endif
- case PWR_GPIO_H:
-#if defined (STM32L496xx) || defined (STM32L4A6xx)
- CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));
-#else
- CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
-#endif
- break;
-#if defined(GPIOI)
- case PWR_GPIO_I:
- CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
- break;
-#endif
- default:
- status = HAL_ERROR;
- break;
- }
-
- return status;
-}
-
-
-
-/**
- * @brief Enable pull-up and pull-down configuration.
- * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in
- * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
- * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
- * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
- * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there
- * is no conflict when setting PUy or PDy bit.
- * @retval None
- */
-void HAL_PWREx_EnablePullUpPullDownConfig(void)
-{
- SET_BIT(PWR->CR3, PWR_CR3_APC);
-}
-
-
-/**
- * @brief Disable pull-up and pull-down configuration.
- * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
- * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
- * @retval None
- */
-void HAL_PWREx_DisablePullUpPullDownConfig(void)
-{
- CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
-}
-
-
-
-/**
- * @brief Enable Full SRAM2 content retention in Standby mode.
- * @retval None
- */
-void HAL_PWREx_EnableSRAM2ContentRetention(void)
-{
- (void) HAL_PWREx_SetSRAM2ContentRetention(PWR_FULL_SRAM2_RETENTION);
-}
-
-/**
- * @brief Disable SRAM2 content retention in Standby mode.
- * @retval None
- */
-void HAL_PWREx_DisableSRAM2ContentRetention(void)
-{
- (void) HAL_PWREx_SetSRAM2ContentRetention(PWR_NO_SRAM2_RETENTION);
-}
-
-/**
- * @brief Enable SRAM2 content retention in Standby mode.
- * @param SRAM2Size: specifies the SRAM2 size kept in Standby mode
- * This parameter can be one of the following values:
- * @arg @ref PWR_NO_SRAM2_RETENTION SRAM2 is powered off in Standby mode (SRAM2 content is lost)
- * @arg @ref PWR_FULL_SRAM2_RETENTION Full SRAM2 is powered by the low-power regulator in Standby mode
- * @arg @ref PWR_4KBYTES_SRAM2_RETENTION Only 4 Kbytes of SRAM2 is powered by the low-power regulator in Standby mode
- * @note PWR_4KBYTES_SRAM2_RETENTION parameter is not available on all devices
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_PWREx_SetSRAM2ContentRetention(uint32_t SRAM2Size)
-{
- assert_param(IS_PWR_SRAM2_RETENTION(SRAM2Size));
-
- if (SRAM2Size == PWR_NO_SRAM2_RETENTION)
- {
- CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
- }
- else if (SRAM2Size == PWR_FULL_SRAM2_RETENTION)
- {
- MODIFY_REG(PWR->CR3, PWR_CR3_RRS, PWR_FULL_SRAM2_RETENTION);
- }
-#if defined(PWR_CR3_RRS_1)
- else if (SRAM2Size == PWR_4KBYTES_SRAM2_RETENTION)
- {
- MODIFY_REG(PWR->CR3, PWR_CR3_RRS, PWR_4KBYTES_SRAM2_RETENTION);
- }
-#endif /* PWR_CR3_RRS_1 */
- else {
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-
-#if defined(PWR_CR3_ENULP)
-/**
- * @brief Enable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes.
- * @note All the other modes are not affected by this bit.
- * @retval None
- */
-void HAL_PWREx_EnableBORPVD_ULP(void)
-{
- SET_BIT(PWR->CR3, PWR_CR3_ENULP);
-}
-
-
-/**
- * @brief Disable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes.
- * @note All the other modes are not affected by this bit
- * @retval None
- */
-void HAL_PWREx_DisableBORPVD_ULP(void)
-{
- CLEAR_BIT(PWR->CR3, PWR_CR3_ENULP);
-}
-#endif /* PWR_CR3_ENULP */
-
-
-#if defined(PWR_CR4_EXT_SMPS_ON)
-/**
- * @brief Enable the CFLDO working @ 0.95V.
- * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the
- * internal CFLDO can be reduced to 0.95V.
- * @retval None
- */
-void HAL_PWREx_EnableExtSMPS_0V95(void)
-{
- SET_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);
-}
-
-/**
- * @brief Disable the CFLDO working @ 0.95V
- * @note Before SMPS is switched off, the regulated voltage of the
- * internal CFLDO shall be set to 1.00V.
- * 1.00V. is also default operating Range 2 voltage.
- * @retval None
- */
-void HAL_PWREx_DisableExtSMPS_0V95(void)
-{
- CLEAR_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);
-}
-#endif /* PWR_CR4_EXT_SMPS_ON */
-
-
-#if defined(PWR_CR1_RRSTP)
-/**
- * @brief Enable SRAM3 content retention in Stop 2 mode.
- * @note When RRSTP bit is set, SRAM3 is powered by the low-power regulator in
- * Stop 2 mode and its content is kept.
- * @retval None
- */
-void HAL_PWREx_EnableSRAM3ContentRetention(void)
-{
- SET_BIT(PWR->CR1, PWR_CR1_RRSTP);
-}
-
-
-/**
- * @brief Disable SRAM3 content retention in Stop 2 mode.
- * @note When RRSTP bit is reset, SRAM3 is powered off in Stop 2 mode
- * and its content is lost.
- * @retval None
- */
-void HAL_PWREx_DisableSRAM3ContentRetention(void)
-{
- CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP);
-}
-#endif /* PWR_CR1_RRSTP */
-
-#if defined(PWR_CR3_DSIPDEN)
-/**
- * @brief Enable pull-down activation on DSI pins.
- * @retval None
- */
-void HAL_PWREx_EnableDSIPinsPDActivation(void)
-{
- SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN);
-}
-
-
-/**
- * @brief Disable pull-down activation on DSI pins.
- * @retval None
- */
-void HAL_PWREx_DisableDSIPinsPDActivation(void)
-{
- CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN);
-}
-#endif /* PWR_CR3_DSIPDEN */
-
-#if defined(PWR_CR2_PVME1)
-/**
- * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
- * @retval None
- */
-void HAL_PWREx_EnablePVM1(void)
-{
- SET_BIT(PWR->CR2, PWR_PVM_1);
-}
-
-/**
- * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
- * @retval None
- */
-void HAL_PWREx_DisablePVM1(void)
-{
- CLEAR_BIT(PWR->CR2, PWR_PVM_1);
-}
-#endif /* PWR_CR2_PVME1 */
-
-
-#if defined(PWR_CR2_PVME2)
-/**
- * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
- * @retval None
- */
-void HAL_PWREx_EnablePVM2(void)
-{
- SET_BIT(PWR->CR2, PWR_PVM_2);
-}
-
-/**
- * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
- * @retval None
- */
-void HAL_PWREx_DisablePVM2(void)
-{
- CLEAR_BIT(PWR->CR2, PWR_PVM_2);
-}
-#endif /* PWR_CR2_PVME2 */
-
-
-/**
- * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
- * @retval None
- */
-void HAL_PWREx_EnablePVM3(void)
-{
- SET_BIT(PWR->CR2, PWR_PVM_3);
-}
-
-/**
- * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
- * @retval None
- */
-void HAL_PWREx_DisablePVM3(void)
-{
- CLEAR_BIT(PWR->CR2, PWR_PVM_3);
-}
-
-
-/**
- * @brief Enable the Power Voltage Monitoring 4: VDDA versus 2.2V.
- * @retval None
- */
-void HAL_PWREx_EnablePVM4(void)
-{
- SET_BIT(PWR->CR2, PWR_PVM_4);
-}
-
-/**
- * @brief Disable the Power Voltage Monitoring 4: VDDA versus 2.2V.
- * @retval None
- */
-void HAL_PWREx_DisablePVM4(void)
-{
- CLEAR_BIT(PWR->CR2, PWR_PVM_4);
-}
-
-
-
-
-/**
- * @brief Configure the Peripheral Voltage Monitoring (PVM).
- * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
- * PVM configuration information.
- * @note The API configures a single PVM according to the information contained
- * in the input structure. To configure several PVMs, the API must be singly
- * called for each PVM used.
- * @note Refer to the electrical characteristics of your device datasheet for
- * more details about the voltage thresholds corresponding to each
- * detection level and to each monitored supply.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
- assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
-
-
- /* Configure EXTI 35 to 38 interrupts if so required:
- scan through PVMType to detect which PVMx is set and
- configure the corresponding EXTI line accordingly. */
- switch (sConfigPVM->PVMType)
- {
-#if defined(PWR_CR2_PVME1)
- case PWR_PVM_1:
- /* Clear any previous config. Keep it clear if no event or IT mode is selected */
- __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
- __HAL_PWR_PVM1_EXTI_DISABLE_IT();
- __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
- __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
-
- /* Configure interrupt mode */
- if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
- {
- __HAL_PWR_PVM1_EXTI_ENABLE_IT();
- }
-
- /* Configure event mode */
- if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
- {
- __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
- }
-
- /* Configure the edge */
- if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
- {
- __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
- }
-
- if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
- {
- __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
- }
- break;
-#endif /* PWR_CR2_PVME1 */
-
-#if defined(PWR_CR2_PVME2)
- case PWR_PVM_2:
- /* Clear any previous config. Keep it clear if no event or IT mode is selected */
- __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
- __HAL_PWR_PVM2_EXTI_DISABLE_IT();
- __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();
- __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
-
- /* Configure interrupt mode */
- if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
- {
- __HAL_PWR_PVM2_EXTI_ENABLE_IT();
- }
-
- /* Configure event mode */
- if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
- {
- __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
- }
-
- /* Configure the edge */
- if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
- {
- __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
- }
-
- if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
- {
- __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
- }
- break;
-#endif /* PWR_CR2_PVME2 */
-
- case PWR_PVM_3:
- /* Clear any previous config. Keep it clear if no event or IT mode is selected */
- __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
- __HAL_PWR_PVM3_EXTI_DISABLE_IT();
- __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
- __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
-
- /* Configure interrupt mode */
- if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
- {
- __HAL_PWR_PVM3_EXTI_ENABLE_IT();
- }
-
- /* Configure event mode */
- if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
- {
- __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
- }
-
- /* Configure the edge */
- if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
- {
- __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
- }
-
- if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
- {
- __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
- }
- break;
-
- case PWR_PVM_4:
- /* Clear any previous config. Keep it clear if no event or IT mode is selected */
- __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
- __HAL_PWR_PVM4_EXTI_DISABLE_IT();
- __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();
- __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
-
- /* Configure interrupt mode */
- if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
- {
- __HAL_PWR_PVM4_EXTI_ENABLE_IT();
- }
-
- /* Configure event mode */
- if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
- {
- __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
- }
-
- /* Configure the edge */
- if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
- {
- __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
- }
-
- if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
- {
- __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
- }
- break;
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- return status;
-}
-
-
-
-/**
- * @brief Enter Low-power Run mode
- * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode.
- * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
- * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.
- * Additionally, the clock frequency must be reduced below 2 MHz.
- * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must
- * be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
- * @retval None
- */
-void HAL_PWREx_EnableLowPowerRunMode(void)
-{
- /* Set Regulator parameter */
- SET_BIT(PWR->CR1, PWR_CR1_LPR);
-}
-
-
-/**
- * @brief Exit Low-power Run mode.
- * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
- * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
- * returns HAL_TIMEOUT status). The system clock frequency can then be
- * increased above 2 MHz.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
-{
- uint32_t wait_loop_index;
-
- /* Clear LPR bit */
- CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
-
- /* Wait until REGLPF is reset */
- wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
- while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))
- {
- wait_loop_index--;
- }
- if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
- {
- return HAL_TIMEOUT;
- }
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Enter Stop 0 mode.
- * @note In Stop 0 mode, main and low voltage regulators are ON.
- * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode.
- * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
- * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
- * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
- * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
- * only to the peripheral requesting it.
- * SRAM1, SRAM2 and register contents are preserved.
- * The BOR is available.
- * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
- * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
- * is set; the MSI oscillator is selected if STOPWUCK is cleared.
- * @note By keeping the internal regulator ON during Stop 0 mode, the consumption
- * is higher although the startup time is reduced.
- * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
- * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
- * @retval None
- */
-void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
-{
- /* Check the parameters */
- assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-
- /* Stop 0 mode with Main Regulator */
- MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
- /* Select Stop mode entry --------------------------------------------------*/
- if(STOPEntry == PWR_STOPENTRY_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __SEV();
- __WFE();
- __WFE();
- }
-
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-
-/**
- * @brief Enter Stop 1 mode.
- * @note In Stop 1 mode, only low power voltage regulator is ON.
- * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode.
- * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
- * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
- * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
- * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
- * only to the peripheral requesting it.
- * SRAM1, SRAM2 and register contents are preserved.
- * The BOR is available.
- * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
- * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
- * is set; the MSI oscillator is selected if STOPWUCK is cleared.
- * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
- * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
- * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
- * @retval None
- */
-void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
-{
- /* Check the parameters */
- assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-
- /* Stop 1 mode with Low-Power Regulator */
- MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
- /* Select Stop mode entry --------------------------------------------------*/
- if(STOPEntry == PWR_STOPENTRY_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __SEV();
- __WFE();
- __WFE();
- }
-
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-
-/**
- * @brief Enter Stop 2 mode.
- * @note In Stop 2 mode, only low power voltage regulator is ON.
- * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode.
- * @note All clocks in the VCORE domain are stopped, the PLL, the MSI,
- * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability
- * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after
- * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only
- * to the peripheral requesting it.
- * SRAM1, SRAM2 and register contents are preserved.
- * SRAM3 content is preserved depending on RRSTP bit setting (not available on all devices).
- * The BOR is available.
- * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.
- * Otherwise, Stop 1 mode is entered.
- * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event,
- * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
- * is set; the MSI oscillator is selected if STOPWUCK is cleared.
- * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
- * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
- * @retval None
- */
-void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
-{
- /* Check the parameter */
- assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-
- /* Set Stop mode 2 */
- MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2);
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
- /* Select Stop mode entry --------------------------------------------------*/
- if(STOPEntry == PWR_STOPENTRY_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __SEV();
- __WFE();
- __WFE();
- }
-
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-
-
-
-
-/**
- * @brief Enter Shutdown mode.
- * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched
- * off. The voltage regulator is disabled and Vcore domain is powered off.
- * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
- * The BOR is not available.
- * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
- * @retval None
- */
-void HAL_PWREx_EnterSHUTDOWNMode(void)
-{
-
- /* Set Shutdown mode */
- MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
-/* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM)
- __force_stores();
-#endif
- /* Request Wait For Interrupt */
- __WFI();
-}
-
-
-
-
-/**
- * @brief This function handles the PWR PVD/PVMx interrupt request.
- * @note This API should be called under the PVD_PVM_IRQHandler().
- * @retval None
- */
-void HAL_PWREx_PVD_PVM_IRQHandler(void)
-{
- /* Check PWR exti flag */
- if(__HAL_PWR_PVD_EXTI_GET_FLAG() != 0x0U)
- {
- /* PWR PVD interrupt user callback */
- HAL_PWR_PVDCallback();
-
- /* Clear PVD exti pending bit */
- __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
- }
- /* Next, successively check PVMx exti flags */
-#if defined(PWR_CR2_PVME1)
- if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0x0U)
- {
- /* PWR PVM1 interrupt user callback */
- HAL_PWREx_PVM1Callback();
-
- /* Clear PVM1 exti pending bit */
- __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
- }
-#endif /* PWR_CR2_PVME1 */
-#if defined(PWR_CR2_PVME2)
- if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != 0x0U)
- {
- /* PWR PVM2 interrupt user callback */
- HAL_PWREx_PVM2Callback();
-
- /* Clear PVM2 exti pending bit */
- __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();
- }
-#endif /* PWR_CR2_PVME2 */
- if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0x0U)
- {
- /* PWR PVM3 interrupt user callback */
- HAL_PWREx_PVM3Callback();
-
- /* Clear PVM3 exti pending bit */
- __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
- }
- if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != 0x0U)
- {
- /* PWR PVM4 interrupt user callback */
- HAL_PWREx_PVM4Callback();
-
- /* Clear PVM4 exti pending bit */
- __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
- }
-}
-
-
-#if defined(PWR_CR2_PVME1)
-/**
- * @brief PWR PVM1 interrupt callback
- * @retval None
- */
-__weak void HAL_PWREx_PVM1Callback(void)
-{
- /* NOTE : This function should not be modified; when the callback is needed,
- HAL_PWREx_PVM1Callback() API can be implemented in the user file
- */
-}
-#endif /* PWR_CR2_PVME1 */
-
-#if defined(PWR_CR2_PVME2)
-/**
- * @brief PWR PVM2 interrupt callback
- * @retval None
- */
-__weak void HAL_PWREx_PVM2Callback(void)
-{
- /* NOTE : This function should not be modified; when the callback is needed,
- HAL_PWREx_PVM2Callback() API can be implemented in the user file
- */
-}
-#endif /* PWR_CR2_PVME2 */
-
-/**
- * @brief PWR PVM3 interrupt callback
- * @retval None
- */
-__weak void HAL_PWREx_PVM3Callback(void)
-{
- /* NOTE : This function should not be modified; when the callback is needed,
- HAL_PWREx_PVM3Callback() API can be implemented in the user file
- */
-}
-
-/**
- * @brief PWR PVM4 interrupt callback
- * @retval None
- */
-__weak void HAL_PWREx_PVM4Callback(void)
-{
- /* NOTE : This function should not be modified; when the callback is needed,
- HAL_PWREx_PVM4Callback() API can be implemented in the user file
- */
-}
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c
deleted file mode 100644
index 71da794..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c
+++ /dev/null
@@ -1,1948 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_rcc.c
- * @author MCD Application Team
- * @brief RCC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Reset and Clock Control (RCC) peripheral:
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- *
- @verbatim
- ==============================================================================
- ##### RCC specific features #####
- ==============================================================================
- [..]
- After reset the device is running from Multiple Speed Internal oscillator
- (4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
- and I-Cache are disabled, and all peripherals are off except internal
- SRAM, Flash and JTAG.
-
- (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses:
- all peripherals mapped on these busses are running at MSI speed.
- (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
- (+) All GPIOs are in analog mode, except the JTAG pins which
- are assigned to be used for debug purpose.
-
- [..]
- Once the device started from reset, the user application has to:
- (+) Configure the clock source to be used to drive the System clock
- (if the application needs higher frequency/performance)
- (+) Configure the System clock frequency and Flash settings
- (+) Configure the AHB and APB busses prescalers
- (+) Enable the clock for the peripheral(s) to be used
- (+) Configure the clock source(s) for peripherals which clocks are not
- derived from the System clock (SAIx, RTC, ADC, USB OTG FS/SDMMC1/RNG)
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file in
- * the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup RCC RCC
- * @brief RCC HAL module driver
- * @{
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup RCC_Private_Constants RCC Private Constants
- * @{
- */
-#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-#define MSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-#if defined(RCC_CSR_LSIPREDIV)
-#define LSI_TIMEOUT_VALUE 17U /* 17 ms (16 ms starting time + 1) */
-#else
-#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-#endif /* RCC_CSR_LSIPREDIV */
-#define HSI48_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup RCC_Private_Macros RCC Private Macros
- * @{
- */
-#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
-#define MCO1_GPIO_PORT GPIOA
-#define MCO1_PIN GPIO_PIN_8
-
-#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \
- (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__)))
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup RCC_Private_Functions RCC Private Functions
- * @{
- */
-static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange);
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
- defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-static uint32_t RCC_GetSysClockFreqFromPLLSource(void);
-#endif
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Functions RCC Exported Functions
- * @{
- */
-
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
- @verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to configure the internal and external oscillators
- (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
- and APB2).
-
- [..] Internal/external clock and PLL configuration
- (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
- the PLL as System clock source.
-
- (+) MSI (Multiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.
- It can be used to generate the clock for the USB OTG FS (48 MHz).
- The number of flash wait states is automatically adjusted when MSI range is updated with
- HAL_RCC_OscConfig() and the MSI is used as System clock source.
-
- (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
- clock source.
-
- (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or
- through the PLL as System clock source. Can be used also optionally as RTC clock source.
-
- (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.
-
- (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
- (++) The first output is used to generate the high speed system clock (up to 80MHz).
- (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
- the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
- (++) The third output is used to generate an accurate clock to achieve
- high-quality audio performance on SAI interface.
-
- (+) PLLSAI1 (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
- (++) The first output is used to generate SAR ADC1 clock.
- (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
- the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
- (++) The third output is used to generate an accurate clock to achieve
- high-quality audio performance on SAI interface.
-
- (+) PLLSAI2 (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
- (++) The first output is used to generate an accurate clock to achieve
- high-quality audio performance on SAI interface.
- (++) The second output is used to generate either SAR ADC2 clock if ADC2 is present
- or LCD clock if LTDC is present.
- (++) The third output is used to generate DSI clock if DSI is present.
-
- (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs
- (HSE used directly or through PLL as System clock source), the System clock
- is automatically switched to HSI and an interrupt is generated if enabled.
- The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
- exception vector.
-
- (+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE or
- main PLL clock (through a configurable prescaler) on PA8 pin.
-
- [..] System, AHB and APB busses clocks configuration
- (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
- HSE and main PLL.
- The AHB clock (HCLK) is derived from System clock through configurable
- prescaler and used to clock the CPU, memory and peripherals mapped
- on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
- from AHB clock through configurable prescalers and used to clock
- the peripherals mapped on these busses. You can use
- "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
-
- -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
-
- (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLSAI1) or (PLLSAI2) or
- from an external clock mapped on the SAI_CKIN pin.
- You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
- (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
- divided by 2 to 31.
- You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
- to configure this clock.
- (+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz
- to work correctly, while the SDMMC1 and RNG peripherals require a frequency
- equal or lower than to 48 MHz. This clock is derived of the main PLL or PLLSAI1
- through PLLQ divider. You have to enable the peripheral clock and use
- HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
- (+@) IWDG clock which is always the LSI clock.
-
-
- (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz.
- The clock source frequency should be adapted depending on the device voltage range
- as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.
-
- @endverbatim
-
- Table 1. HCLK clock frequency for other STM32L4 devices
- +-------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |-------------------------------------|
- | | voltage range 1 | voltage range 2 |
- | | 1.2 V | 1.0 V |
- |-----------------|------------------|------------------|
- |0WS(1 CPU cycles)| 0 < HCLK <= 16 | 0 < HCLK <= 6 |
- |-----------------|------------------|------------------|
- |1WS(2 CPU cycles)| 16 < HCLK <= 32 | 6 < HCLK <= 12 |
- |-----------------|------------------|------------------|
- |2WS(3 CPU cycles)| 32 < HCLK <= 48 | 12 < HCLK <= 18 |
- |-----------------|------------------|------------------|
- |3WS(4 CPU cycles)| 48 < HCLK <= 64 | 18 < HCLK <= 26 |
- |-----------------|------------------|------------------|
- |4WS(5 CPU cycles)| 64 < HCLK <= 80 | 18 < HCLK <= 26 |
- +-------------------------------------------------------+
-
- Table 2. HCLK clock frequency for STM32L4+ devices
- +--------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |--------------------------------------|
- | | voltage range 1 | voltage range 2 |
- | | 1.2 V | 1.0 V |
- |-----------------|-------------------|------------------|
- |0WS(1 CPU cycles)| 0 < HCLK <= 20 | 0 < HCLK <= 8 |
- |-----------------|-------------------|------------------|
- |1WS(2 CPU cycles)| 20 < HCLK <= 40 | 8 < HCLK <= 16 |
- |-----------------|-------------------|------------------|
- |2WS(3 CPU cycles)| 40 < HCLK <= 60 | 16 < HCLK <= 26 |
- |-----------------|-------------------|------------------|
- |3WS(4 CPU cycles)| 60 < HCLK <= 80 | 16 < HCLK <= 26 |
- |-----------------|-------------------|------------------|
- |4WS(5 CPU cycles)| 80 < HCLK <= 100 | 16 < HCLK <= 26 |
- |-----------------|-------------------|------------------|
- |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26 |
- +--------------------------------------------------------+
- * @{
- */
-
-/**
- * @brief Reset the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * - MSI ON and used as system clock source
- * - HSE, HSI, PLL, PLLSAI1 and PLLSAI2 OFF
- * - AHB, APB1 and APB2 prescalers set to 1.
- * - CSS, MCO1 OFF
- * - All interrupts disabled
- * - All interrupt and reset flags cleared
- * @note This function does not modify the configuration of the
- * - Peripheral clock sources
- * - LSI, LSE and RTC clocks (Backup domain)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCC_DeInit(void)
-{
- uint32_t tickstart;
-
- /* Reset to default System clock */
- /* Set MSION bit */
- SET_BIT(RCC->CR, RCC_CR_MSION);
-
- /* Insure MSIRDY bit is set before writing default MSIRANGE value */
- /* Get start tick */
- tickstart = HAL_GetTick();
-
- /* Wait till MSI is ready */
- while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
- {
- if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Set MSIRANGE default value */
- MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, RCC_MSIRANGE_6);
-
- /* Reset CFGR register (MSI is selected as system clock source) */
- CLEAR_REG(RCC->CFGR);
-
- /* Update the SystemCoreClock global variable for MSI as system clock source */
- SystemCoreClock = MSI_VALUE;
-
- /* Configure the source of time base considering new system clock settings */
- if(HAL_InitTick(uwTickPrio) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Insure MSI selected as system clock source */
- /* Get start tick */
- tickstart = HAL_GetTick();
-
- /* Wait till system clock source is ready */
- while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI)
- {
- if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Reset HSION, HSIKERON, HSIASFS, HSEON, HSECSSON, PLLON, PLLSAIxON bits */
-#if defined(RCC_PLLSAI2_SUPPORT)
-
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON);
-
-#elif defined(RCC_PLLSAI1_SUPPORT)
-
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON);
-
-#else
-
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON);
-
-#endif /* RCC_PLLSAI2_SUPPORT */
-
- /* Insure PLLRDY, PLLSAI1RDY and PLLSAI2RDY (if present) are reset */
- /* Get start tick */
- tickstart = HAL_GetTick();
-
-#if defined(RCC_PLLSAI2_SUPPORT)
-
- while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U)
-
-#elif defined(RCC_PLLSAI1_SUPPORT)
-
- while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U)
-
-#else
-
- while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
-
-#endif
- {
- if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Reset PLLCFGR register */
- CLEAR_REG(RCC->PLLCFGR);
- SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4 );
-
-#if defined(RCC_PLLSAI1_SUPPORT)
-
- /* Reset PLLSAI1CFGR register */
- CLEAR_REG(RCC->PLLSAI1CFGR);
- SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N_4 );
-
-#endif /* RCC_PLLSAI1_SUPPORT */
-
-#if defined(RCC_PLLSAI2_SUPPORT)
-
- /* Reset PLLSAI2CFGR register */
- CLEAR_REG(RCC->PLLSAI2CFGR);
- SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N_4 );
-
-#endif /* RCC_PLLSAI2_SUPPORT */
-
- /* Reset HSEBYP bit */
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-
- /* Disable all interrupts */
- CLEAR_REG(RCC->CIER);
-
- /* Clear all interrupt flags */
- WRITE_REG(RCC->CICR, 0xFFFFFFFFU);
-
- /* Clear all reset flags */
- SET_BIT(RCC->CSR, RCC_CSR_RMVF);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the RCC Oscillators according to the specified parameters in the
- * RCC_OscInitTypeDef.
- * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
- * contains the configuration information for the RCC Oscillators.
- * @note The PLL is not disabled when used as system clock.
- * @note The PLL source is not updated when used as PLLSAI(s) clock source.
- * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
- * supported by this macro. User should request a transition to LSE Off
- * first and then LSE On or LSE Bypass.
- * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
- * supported by this macro. User should request a transition to HSE Off
- * first and then HSE On or HSE Bypass.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
-{
- uint32_t tickstart;
- HAL_StatusTypeDef status;
- uint32_t sysclk_source, pll_config;
-
- /* Check Null pointer */
- if(RCC_OscInitStruct == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-
- sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
- pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
-
- /*----------------------------- MSI Configuration --------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
- {
- /* Check the parameters */
- assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
- assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
- assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
-
- /* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
- if((sysclk_source == RCC_CFGR_SWS_MSI) ||
- ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))
- {
- if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
- {
- return HAL_ERROR;
- }
-
- /* Otherwise, just the calibration and MSI range change are allowed */
- else
- {
- /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock
- (HCLK) and the supply voltage of the device. */
- if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
- {
- /* First increase number of wait states update if necessary */
- if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Selects the Multiple Speed oscillator (MSI) clock range .*/
- __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
- /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
- __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
- }
- else
- {
- /* Else, keep current flash latency while decreasing applies */
- /* Selects the Multiple Speed oscillator (MSI) clock range .*/
- __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
- /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
- __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
-
- /* Decrease number of wait states update if necessary */
- /* Only possible when MSI is the System clock source */
- if(sysclk_source == RCC_CFGR_SWS_MSI)
- {
- if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
- {
- return HAL_ERROR;
- }
- }
- }
-
- /* Update the SystemCoreClock global variable */
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
-
- /* Configure the source of time base considering new system clocks settings*/
- status = HAL_InitTick(uwTickPrio);
- if(status != HAL_OK)
- {
- return status;
- }
- }
- }
- else
- {
- /* Check the MSI State */
- if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
- {
- /* Enable the Internal High Speed oscillator (MSI). */
- __HAL_RCC_MSI_ENABLE();
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till MSI is ready */
- while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
- {
- if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- /* Selects the Multiple Speed oscillator (MSI) clock range .*/
- __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
- /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
- __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
-
- }
- else
- {
- /* Disable the Internal High Speed oscillator (MSI). */
- __HAL_RCC_MSI_DISABLE();
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till MSI is ready */
- while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
- {
- if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- /*------------------------------- HSE Configuration ------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
-
- /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
- if((sysclk_source == RCC_CFGR_SWS_HSE) ||
- ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))
- {
- if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- {
- return HAL_ERROR;
- }
- }
- else
- {
- /* Set the new HSE configuration ---------------------------------------*/
- __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-
- /* Check the HSE State */
- if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is ready */
- while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
- {
- if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is disabled */
- while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
- {
- if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- /*----------------------------- HSI Configuration --------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
- assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
- /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
- if((sysclk_source == RCC_CFGR_SWS_HSI) ||
- ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))
- {
- /* When HSI is used as system clock it will not be disabled */
- if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
- {
- return HAL_ERROR;
- }
- /* Otherwise, just the calibration is allowed */
- else
- {
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- }
- }
- else
- {
- /* Check the HSI State */
- if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
- {
- /* Enable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is ready */
- while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
- {
- if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- }
- else
- {
- /* Disable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is disabled */
- while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
- {
- if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- /*------------------------------ LSI Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- {
- /* Check the parameters */
- assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
- /* Check the LSI State */
- if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
- {
-#if defined(RCC_CSR_LSIPREDIV)
- uint32_t csr_temp = RCC->CSR;
-
- /* Check LSI division factor */
- assert_param(IS_RCC_LSIDIV(RCC_OscInitStruct->LSIDiv));
-
- if (RCC_OscInitStruct->LSIDiv != (csr_temp & RCC_CSR_LSIPREDIV))
- {
- if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \
- ((csr_temp & RCC_CSR_LSION) != RCC_CSR_LSION))
- {
- /* If LSIRDY is set while LSION is not enabled,
- LSIPREDIV can't be updated */
- return HAL_ERROR;
- }
-
- /* Turn off LSI before changing RCC_CSR_LSIPREDIV */
- if ((csr_temp & RCC_CSR_LSION) == RCC_CSR_LSION)
- {
- __HAL_RCC_LSI_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSI is disabled */
- while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
- {
- if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Set LSI division factor */
- MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);
- }
-#endif /* RCC_CSR_LSIPREDIV */
-
- /* Enable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSI is ready */
- while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
- {
- if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Disable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSI is disabled */
- while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
- {
- if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- /*------------------------------ LSE Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- {
- FlagStatus pwrclkchanged = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
- /* Update LSE configuration in Backup Domain control register */
- /* Requires to enable write access to Backup Domain of necessary */
- if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
- {
- __HAL_RCC_PWR_CLK_ENABLE();
- pwrclkchanged = SET;
- }
-
- if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- {
- /* Enable write access to Backup domain */
- SET_BIT(PWR->CR1, PWR_CR1_DBP);
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- {
- if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Set the new LSE configuration -----------------------------------------*/
-#if defined(RCC_BDCR_LSESYSDIS)
- if((RCC_OscInitStruct->LSEState & RCC_BDCR_LSEON) != 0U)
- {
- /* Set LSESYSDIS bit according to LSE propagation option (enabled or disabled) */
- MODIFY_REG(RCC->BDCR, RCC_BDCR_LSESYSDIS, (RCC_OscInitStruct->LSEState & RCC_BDCR_LSESYSDIS));
-
- if((RCC_OscInitStruct->LSEState & RCC_BDCR_LSEBYP) != 0U)
- {
- /* LSE oscillator bypass enable */
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
- }
- else
- {
- /* LSE oscillator enable */
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
- }
- }
- else
- {
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
- }
-#else
- __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
-#endif /* RCC_BDCR_LSESYSDIS */
-
- /* Check the LSE State */
- if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
- {
- if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is disabled */
- while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
- {
- if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
-#if defined(RCC_BDCR_LSESYSDIS)
- /* By default, stop disabling LSE propagation */
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
-#endif /* RCC_BDCR_LSESYSDIS */
- }
-
- /* Restore clock configuration if changed */
- if(pwrclkchanged == SET)
- {
- __HAL_RCC_PWR_CLK_DISABLE();
- }
- }
-#if defined(RCC_HSI48_SUPPORT)
- /*------------------------------ HSI48 Configuration -----------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
-
- /* Check the LSI State */
- if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
- {
- /* Enable the Internal Low Speed oscillator (HSI48). */
- __HAL_RCC_HSI48_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSI48 is ready */
- while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
- {
- if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Disable the Internal Low Speed oscillator (HSI48). */
- __HAL_RCC_HSI48_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSI48 is disabled */
- while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
- {
- if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
-#endif /* RCC_HSI48_SUPPORT */
- /*-------------------------------- PLL Configuration -----------------------*/
- /* Check the parameters */
- assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
-
- if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
- {
- /* PLL On ? */
- if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
- {
- /* Check the parameters */
- assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
- assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
- assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
-#if defined(RCC_PLLP_SUPPORT)
- assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
-#endif /* RCC_PLLP_SUPPORT */
- assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
- assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
-
- /* Do nothing if PLL configuration is the unchanged */
- pll_config = RCC->PLLCFGR;
- if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
- (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
- (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
-#if defined(RCC_PLLP_SUPPORT)
-#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
- (READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
-#else
- (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
-#endif
-#endif
- (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
- (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
- {
- /* Check if the PLL is used as system clock or not */
- if(sysclk_source != RCC_CFGR_SWS_PLL)
- {
-#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT)
- /* Check if main PLL can be updated */
- /* Not possible if the source is shared by other enabled PLLSAIx */
- if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
-#if defined(RCC_PLLSAI2_SUPPORT)
- || (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U)
-#endif
- )
- {
- return HAL_ERROR;
- }
- else
-#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */
- {
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
- {
- if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Configure the main PLL clock source, multiplication and division factors. */
-#if defined(RCC_PLLP_SUPPORT)
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- RCC_OscInitStruct->PLL.PLLM,
- RCC_OscInitStruct->PLL.PLLN,
- RCC_OscInitStruct->PLL.PLLP,
- RCC_OscInitStruct->PLL.PLLQ,
- RCC_OscInitStruct->PLL.PLLR);
-#else
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- RCC_OscInitStruct->PLL.PLLM,
- RCC_OscInitStruct->PLL.PLLN,
- RCC_OscInitStruct->PLL.PLLQ,
- RCC_OscInitStruct->PLL.PLLR);
-#endif
-
- /* Enable the main PLL. */
- __HAL_RCC_PLL_ENABLE();
-
- /* Enable PLL System Clock output. */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
- {
- if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- /* PLL is already used as System core clock */
- return HAL_ERROR;
- }
- }
- else
- {
- /* PLL configuration is unchanged */
- /* Re-enable PLL if it was disabled (ie. low power mode) */
- if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
- {
- /* Enable the main PLL. */
- __HAL_RCC_PLL_ENABLE();
-
- /* Enable PLL System Clock output. */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
- {
- if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- else
- {
- /* Check that PLL is not used as system clock or not */
- if(sysclk_source != RCC_CFGR_SWS_PLL)
- {
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
-
- /* Disable all PLL outputs to save power if no PLLs on */
-#if defined(RCC_PLLSAI1_SUPPORT) && defined(RCC_CR_PLLSAI2RDY)
- if(READ_BIT(RCC->CR, (RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY)) == 0U)
- {
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
- }
-#elif defined(RCC_PLLSAI1_SUPPORT)
- if(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
- {
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
- }
-#else
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
-#endif /* RCC_PLLSAI1_SUPPORT && RCC_CR_PLLSAI2RDY */
-
-#if defined(RCC_PLLSAI2_SUPPORT)
- __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
-#elif defined(RCC_PLLSAI1_SUPPORT)
- __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI2CLK);
-#else
- __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK);
-#endif /* RCC_PLLSAI2_SUPPORT */
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is disabled */
- while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
- {
- if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* PLL is already used as System core clock */
- return HAL_ERROR;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the CPU, AHB and APB busses clocks according to the specified
- * parameters in the RCC_ClkInitStruct.
- * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
- * contains the configuration information for the RCC peripheral.
- * @param FLatency FLASH Latency
- * This parameter can be one of the following values:
- * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle
- * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle
- * @arg FLASH_LATENCY_2 FLASH 2 Latency cycles
- * @arg FLASH_LATENCY_3 FLASH 3 Latency cycles
- * @arg FLASH_LATENCY_4 FLASH 4 Latency cycles
- @if STM32L4S9xx
- * @arg FLASH_LATENCY_5 FLASH 5 Latency cycles
- * @arg FLASH_LATENCY_6 FLASH 6 Latency cycles
- * @arg FLASH_LATENCY_7 FLASH 7 Latency cycles
- * @arg FLASH_LATENCY_8 FLASH 8 Latency cycles
- * @arg FLASH_LATENCY_9 FLASH 9 Latency cycles
- * @arg FLASH_LATENCY_10 FLASH 10 Latency cycles
- * @arg FLASH_LATENCY_11 FLASH 11 Latency cycles
- * @arg FLASH_LATENCY_12 FLASH 12 Latency cycles
- * @arg FLASH_LATENCY_13 FLASH 13 Latency cycles
- * @arg FLASH_LATENCY_14 FLASH 14 Latency cycles
- * @arg FLASH_LATENCY_15 FLASH 15 Latency cycles
- @endif
- *
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
- * and updated by HAL_RCC_GetHCLKFreq() function called within this function
- *
- * @note The MSI is used by default as system clock source after
- * startup from Reset, wake-up from STANDBY mode. After restart from Reset,
- * the MSI frequency is set to its default value 4 MHz.
- *
- * @note The HSI can be selected as system clock source after
- * from STOP modes or in case of failure of the HSE used directly or indirectly
- * as system clock (if the Clock Security System CSS is enabled).
- *
- * @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after startup delay or PLL locked).
- * If a clock source which is not yet ready is selected, the switch will
- * occur when the clock source is ready.
- *
- * @note You can use HAL_RCC_GetClockConfig() function to know which clock is
- * currently used as system clock source.
- *
- * @note Depending on the device voltage range, the software has to set correctly
- * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
- * (for more details refer to section above "Initialization/de-initialization functions")
- * @retval None
- */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
-{
- uint32_t tickstart;
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
- defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
- uint32_t hpre = RCC_SYSCLK_DIV1;
-#endif
- HAL_StatusTypeDef status;
-
- /* Check Null pointer */
- if(RCC_ClkInitStruct == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
- assert_param(IS_FLASH_LATENCY(FLatency));
-
- /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock
- (HCLK) and the supply voltage of the device. */
-
- /* Increasing the number of wait states because of higher CPU frequency */
- if(FLatency > __HAL_FLASH_GET_LATENCY())
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if(__HAL_FLASH_GET_LATENCY() != FLatency)
- {
- return HAL_ERROR;
- }
- }
-
- /*------------------------- SYSCLK Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- {
- assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
- /* PLL is selected as System Clock Source */
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- /* Check the PLL ready flag */
- if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
- {
- return HAL_ERROR;
- }
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
- defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
- /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */
- /* Compute target PLL output frequency */
- if(RCC_GetSysClockFreqFromPLLSource() > 80000000U)
- {
- if(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)
- {
- /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
- hpre = RCC_SYSCLK_DIV2;
- }
- else if((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1))
- {
- /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
- hpre = RCC_SYSCLK_DIV2;
- }
- else
- {
- /* nothing to do */
- }
- }
-#endif
- }
- else
- {
- /* HSE is selected as System Clock Source */
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- {
- /* Check the HSE ready flag */
- if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
- {
- return HAL_ERROR;
- }
- }
- /* MSI is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
- {
- /* Check the MSI ready flag */
- if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
- {
- return HAL_ERROR;
- }
- }
- /* HSI is selected as System Clock Source */
- else
- {
- /* Check the HSI ready flag */
- if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
- {
- return HAL_ERROR;
- }
- }
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
- defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
- /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */
- if(HAL_RCC_GetSysClockFreq() > 80000000U)
- {
- /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
- hpre = RCC_SYSCLK_DIV2;
- }
-#endif
-
- }
-
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- {
- if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /*-------------------------- HCLK Configuration --------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- {
- assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- }
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
- defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
- else
- {
- /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */
- if(hpre == RCC_SYSCLK_DIV2)
- {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
- }
- }
-#endif
-
- /* Decreasing the number of wait states because of lower CPU frequency */
- if(FLatency < __HAL_FLASH_GET_LATENCY())
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if(__HAL_FLASH_GET_LATENCY() != FLatency)
- {
- return HAL_ERROR;
- }
- }
-
- /*-------------------------- PCLK1 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
- }
-
- /*-------------------------- PCLK2 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
- }
-
- /* Update the SystemCoreClock global variable */
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
-
- /* Configure the source of time base considering new system clocks settings*/
- status = HAL_InitTick(uwTickPrio);
-
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
- * @brief RCC clocks control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to:
-
- (+) Output clock to MCO pin.
- (+) Retrieve current clock frequencies.
- (+) Enable the Clock Security System.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Select the clock source to output on MCO pin(PA8).
- * @note PA8 should be configured in alternate function mode.
- * @param RCC_MCOx specifies the output direction for the clock source.
- * For STM32L4xx family this parameter can have only one value:
- * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
- * @param RCC_MCOSource specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO
- * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
- * @arg @ref RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
- @if STM32L443xx
- * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
- @endif
- * @param RCC_MCODiv specifies the MCO prescaler.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
- * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock
- * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock
- * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock
- * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock
- * @retval None
- */
-void HAL_RCC_MCOConfig( uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
-{
- GPIO_InitTypeDef GPIO_InitStruct;
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO(RCC_MCOx));
- assert_param(IS_RCC_MCODIV(RCC_MCODiv));
- assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
-
- /* Prevent unused argument(s) compilation warning if no assert_param check */
- UNUSED(RCC_MCOx);
-
- /* MCO Clock Enable */
- __MCO1_CLK_ENABLE();
-
- /* Configure the MCO1 pin in alternate function mode */
- GPIO_InitStruct.Pin = MCO1_PIN;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
- HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
-
- /* Mask MCOSEL[] and MCOPRE[] bits then set MCO1 clock source and prescaler */
- MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv ));
-}
-
-/**
- * @brief Return the SYSCLK frequency.
- *
- * @note The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- * @note If SYSCLK source is MSI, function returns values based on MSI
- * Value as defined by the MSI range.
- * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
- * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
- * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**),
- * HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors.
- * @note (*) HSI_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value
- * 16 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- * @note (**) HSE_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * @note The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @note This function can be used by the user application to compute the
- * baudrate for the communication peripherals or configure other parameters.
- *
- * @note Each time SYSCLK changes, this function must be called to update the
- * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
- *
- *
- * @retval SYSCLK frequency
- */
-uint32_t HAL_RCC_GetSysClockFreq(void)
-{
- uint32_t msirange = 0U, sysclockfreq = 0U;
- uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */
- uint32_t sysclk_source, pll_oscsource;
-
- sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
- pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
-
- if((sysclk_source == RCC_CFGR_SWS_MSI) ||
- ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
- {
- /* MSI or PLL with MSI source used as system clock source */
-
- /* Get SYSCLK source */
- if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
- { /* MSISRANGE from RCC_CSR applies */
- msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
- }
- else
- { /* MSIRANGE from RCC_CR applies */
- msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
- }
- /*MSI frequency range in HZ*/
- msirange = MSIRangeTable[msirange];
-
- if(sysclk_source == RCC_CFGR_SWS_MSI)
- {
- /* MSI used as system clock source */
- sysclockfreq = msirange;
- }
- }
- else if(sysclk_source == RCC_CFGR_SWS_HSI)
- {
- /* HSI used as system clock source */
- sysclockfreq = HSI_VALUE;
- }
- else if(sysclk_source == RCC_CFGR_SWS_HSE)
- {
- /* HSE used as system clock source */
- sysclockfreq = HSE_VALUE;
- }
- else
- {
- /* unexpected case: sysclockfreq at 0 */
- }
-
- if(sysclk_source == RCC_CFGR_SWS_PLL)
- {
- /* PLL used as system clock source */
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
- SYSCLK = PLL_VCO / PLLR
- */
- pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
-
- switch (pllsource)
- {
- case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
- pllvco = HSI_VALUE;
- break;
-
- case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
- pllvco = HSE_VALUE;
- break;
-
- case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
- default:
- pllvco = msirange;
- break;
- }
- pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
- pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;
- pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
- sysclockfreq = pllvco / pllr;
- }
-
- return sysclockfreq;
-}
-
-/**
- * @brief Return the HCLK frequency.
- * @note Each time HCLK changes, this function must be called to update the
- * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
- *
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
- * @retval HCLK frequency in Hz
- */
-uint32_t HAL_RCC_GetHCLKFreq(void)
-{
- return SystemCoreClock;
-}
-
-/**
- * @brief Return the PCLK1 frequency.
- * @note Each time PCLK1 changes, this function must be called to update the
- * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK1 frequency in Hz
- */
-uint32_t HAL_RCC_GetPCLK1Freq(void)
-{
- /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
-}
-
-/**
- * @brief Return the PCLK2 frequency.
- * @note Each time PCLK2 changes, this function must be called to update the
- * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK2 frequency in Hz
- */
-uint32_t HAL_RCC_GetPCLK2Freq(void)
-{
- /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
-}
-
-/**
- * @brief Configure the RCC_OscInitStruct according to the internal
- * RCC configuration registers.
- * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
- * will be configured.
- * @retval None
- */
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
-{
- /* Check the parameters */
- assert_param(RCC_OscInitStruct != (void *)NULL);
-
- /* Set all possible values for the Oscillator type parameter ---------------*/
-#if defined(RCC_HSI48_SUPPORT)
- RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
- RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;
-#else
- RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
- RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
-#endif /* RCC_HSI48_SUPPORT */
-
- /* Get the HSE configuration -----------------------------------------------*/
- if(READ_BIT(RCC->CR, RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
- }
- else if(READ_BIT(RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON)
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_ON;
- }
- else
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
- }
-
- /* Get the MSI configuration -----------------------------------------------*/
- if(READ_BIT(RCC->CR, RCC_CR_MSION) == RCC_CR_MSION)
- {
- RCC_OscInitStruct->MSIState = RCC_MSI_ON;
- }
- else
- {
- RCC_OscInitStruct->MSIState = RCC_MSI_OFF;
- }
-
- RCC_OscInitStruct->MSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos;
- RCC_OscInitStruct->MSIClockRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE);
-
- /* Get the HSI configuration -----------------------------------------------*/
- if(READ_BIT(RCC->CR, RCC_CR_HSION) == RCC_CR_HSION)
- {
- RCC_OscInitStruct->HSIState = RCC_HSI_ON;
- }
- else
- {
- RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
- }
-
- RCC_OscInitStruct->HSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos;
-
- /* Get the LSE configuration -----------------------------------------------*/
- if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
- {
-#if defined(RCC_BDCR_LSESYSDIS)
- if((RCC->BDCR & RCC_BDCR_LSESYSDIS) == RCC_BDCR_LSESYSDIS)
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_RTC_ONLY;
- }
- else
-#endif /* RCC_BDCR_LSESYSDIS */
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
- }
- }
- else if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
- {
-#if defined(RCC_BDCR_LSESYSDIS)
- if((RCC->BDCR & RCC_BDCR_LSESYSDIS) == RCC_BDCR_LSESYSDIS)
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_ON_RTC_ONLY;
- }
- else
-#endif /* RCC_BDCR_LSESYSDIS */
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_ON;
- }
- }
- else
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
- }
-
- /* Get the LSI configuration -----------------------------------------------*/
- if(READ_BIT(RCC->CSR, RCC_CSR_LSION) == RCC_CSR_LSION)
- {
- RCC_OscInitStruct->LSIState = RCC_LSI_ON;
- }
- else
- {
- RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
- }
-#if defined(RCC_CSR_LSIPREDIV)
-
- /* Get the LSI configuration -----------------------------------------------*/
- if((RCC->CSR & RCC_CSR_LSIPREDIV) == RCC_CSR_LSIPREDIV)
- {
- RCC_OscInitStruct->LSIDiv = RCC_LSI_DIV128;
- }
- else
- {
- RCC_OscInitStruct->LSIDiv = RCC_LSI_DIV1;
- }
-#endif /* RCC_CSR_LSIPREDIV */
-
-#if defined(RCC_HSI48_SUPPORT)
- /* Get the HSI48 configuration ---------------------------------------------*/
- if(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)
- {
- RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
- }
- else
- {
- RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
- }
-#else
- RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
-#endif /* RCC_HSI48_SUPPORT */
-
- /* Get the PLL configuration -----------------------------------------------*/
- if(READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON)
- {
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
- }
- else
- {
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
- }
- RCC_OscInitStruct->PLL.PLLSource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
- RCC_OscInitStruct->PLL.PLLM = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;
- RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
- RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);
- RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U) << 1U);
-#if defined(RCC_PLLP_SUPPORT)
-#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
- RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
-#else
- if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)
- {
- RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV17;
- }
- else
- {
- RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV7;
- }
-#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
-#endif /* RCC_PLLP_SUPPORT */
-}
-
-/**
- * @brief Configure the RCC_ClkInitStruct according to the internal
- * RCC configuration registers.
- * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
- * will be configured.
- * @param pFLatency Pointer on the Flash Latency.
- * @retval None
- */
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
-{
- /* Check the parameters */
- assert_param(RCC_ClkInitStruct != (void *)NULL);
- assert_param(pFLatency != (void *)NULL);
-
- /* Set all possible values for the Clock type parameter --------------------*/
- RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-
- /* Get the SYSCLK configuration --------------------------------------------*/
- RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW);
-
- /* Get the HCLK configuration ----------------------------------------------*/
- RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE);
-
- /* Get the APB1 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1);
-
- /* Get the APB2 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U);
-
- /* Get the Flash Wait State (Latency) configuration ------------------------*/
- *pFLatency = __HAL_FLASH_GET_LATENCY();
-}
-
-/**
- * @brief Enable the Clock Security System.
- * @note If a failure is detected on the HSE oscillator clock, this oscillator
- * is automatically disabled and an interrupt is generated to inform the
- * software about the failure (Clock Security System Interrupt, CSSI),
- * allowing the MCU to perform rescue operations. The CSSI is linked to
- * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
- * @note The Clock Security System can only be cleared by reset.
- * @retval None
- */
-void HAL_RCC_EnableCSS(void)
-{
- SET_BIT(RCC->CR, RCC_CR_CSSON) ;
-}
-
-/**
- * @brief Handle the RCC Clock Security System interrupt request.
- * @note This API should be called under the NMI_Handler().
- * @retval None
- */
-void HAL_RCC_NMI_IRQHandler(void)
-{
- /* Check RCC CSSF interrupt flag */
- if(__HAL_RCC_GET_IT(RCC_IT_CSS))
- {
- /* RCC Clock Security System interrupt user callback */
- HAL_RCC_CSSCallback();
-
- /* Clear RCC CSS pending bit */
- __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
- }
-}
-
-/**
- * @brief RCC Clock Security System interrupt callback.
- * @retval none
- */
-__weak void HAL_RCC_CSSCallback(void)
-{
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RCC_CSSCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Get and clear reset flags
- * @param None
- * @note Once reset flags are retrieved, this API is clearing them in order
- * to isolate next reset reason.
- * @retval can be a combination of @ref RCC_Reset_Flag
- */
-uint32_t HAL_RCC_GetResetSource(void)
-{
- uint32_t reset;
-
- /* Get all reset flags */
- reset = RCC->CSR & RCC_RESET_FLAG_ALL;
-
- /* Clear Reset flags */
- RCC->CSR |= RCC_CSR_RMVF;
-
- return reset;
-}
-
-/** * @}
- */
-
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup RCC_Private_Functions
- * @{
- */
-/**
- * @brief Update number of Flash wait states in line with MSI range and current
- voltage range.
- * @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
- * @retval HAL status
- */
-static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
-{
- uint32_t vos;
- uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
-
- if(__HAL_RCC_PWR_IS_CLK_ENABLED())
- {
- vos = HAL_PWREx_GetVoltageRange();
- }
- else
- {
- __HAL_RCC_PWR_CLK_ENABLE();
- vos = HAL_PWREx_GetVoltageRange();
- __HAL_RCC_PWR_CLK_DISABLE();
- }
-
- if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
- {
- if(msirange > RCC_MSIRANGE_8)
- {
- /* MSI > 16Mhz */
- if(msirange > RCC_MSIRANGE_10)
- {
- /* MSI 48Mhz */
- latency = FLASH_LATENCY_2; /* 2WS */
- }
- else
- {
- /* MSI 24Mhz or 32Mhz */
- latency = FLASH_LATENCY_1; /* 1WS */
- }
- }
- /* else MSI <= 16Mhz default FLASH_LATENCY_0 0WS */
- }
- else
- {
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
- defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
- if(msirange >= RCC_MSIRANGE_8)
- {
- /* MSI >= 16Mhz */
- latency = FLASH_LATENCY_2; /* 2WS */
- }
- else
- {
- if(msirange == RCC_MSIRANGE_7)
- {
- /* MSI 8Mhz */
- latency = FLASH_LATENCY_1; /* 1WS */
- }
- /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
- }
-#else
- if(msirange > RCC_MSIRANGE_8)
- {
- /* MSI > 16Mhz */
- latency = FLASH_LATENCY_3; /* 3WS */
- }
- else
- {
- if(msirange == RCC_MSIRANGE_8)
- {
- /* MSI 16Mhz */
- latency = FLASH_LATENCY_2; /* 2WS */
- }
- else if(msirange == RCC_MSIRANGE_7)
- {
- /* MSI 8Mhz */
- latency = FLASH_LATENCY_1; /* 1WS */
- }
- /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
- }
-#endif
- }
-
- __HAL_FLASH_SET_LATENCY(latency);
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if(__HAL_FLASH_GET_LATENCY() != latency)
- {
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
- defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-/**
- * @brief Compute SYSCLK frequency based on PLL SYSCLK source.
- * @retval SYSCLK frequency
- */
-static uint32_t RCC_GetSysClockFreqFromPLLSource(void)
-{
- uint32_t msirange = 0U;
- uint32_t pllvco, pllsource, pllr, pllm, sysclockfreq; /* no init needed */
-
- if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI)
- {
- /* Get MSI range source */
- if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
- { /* MSISRANGE from RCC_CSR applies */
- msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
- }
- else
- { /* MSIRANGE from RCC_CR applies */
- msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
- }
- /*MSI frequency range in HZ*/
- msirange = MSIRangeTable[msirange];
- }
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
- SYSCLK = PLL_VCO / PLLR
- */
- pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
-
- switch (pllsource)
- {
- case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
- pllvco = HSI_VALUE;
- break;
-
- case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
- pllvco = HSE_VALUE;
- break;
-
- case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
- default:
- pllvco = msirange;
- break;
- }
- pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
- pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;
- pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
- sysclockfreq = pllvco / pllr;
-
- return sysclockfreq;
-}
-#endif
-
-/**
- * @}
- */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c
deleted file mode 100644
index 2457b7f..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c
+++ /dev/null
@@ -1,3552 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_rcc_ex.c
- * @author MCD Application Team
- * @brief Extended RCC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities RCC extended peripheral:
- * + Extended Peripheral Control functions
- * + Extended Clock management functions
- * + Extended Clock Recovery System Control functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file in
- * the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup RCCEx RCCEx
- * @brief RCC Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
- * @{
- */
-#define PLLSAI1_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-#define PLLSAI2_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-
-#define DIVIDER_P_UPDATE 0U
-#define DIVIDER_Q_UPDATE 1U
-#define DIVIDER_R_UPDATE 2U
-
-#define __LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
-#define LSCO_GPIO_PORT GPIOA
-#define LSCO_PIN GPIO_PIN_2
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup RCCEx_Private_Functions RCCEx Private Functions
- * @{
- */
-#if defined(RCC_PLLSAI1_SUPPORT)
-
-static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider);
-
-#endif /* RCC_PLLSAI1_SUPPORT */
-
-#if defined(RCC_PLLSAI2_SUPPORT)
-
-static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider);
-
-#endif /* RCC_PLLSAI2_SUPPORT */
-
-#if defined(SAI1)
-
-static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t InputFrequency);
-
-#endif /* SAI1 */
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
- * @{
- */
-
-/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
- * @brief Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Extended Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the RCC Clocks
- frequencies.
- [..]
- (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
- select the RTC clock source; in this case the Backup domain will be reset in
- order to modify the RTC Clock source, as consequence RTC registers (including
- the backup registers) are set to their reset values.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initialize the RCC extended peripherals clocks according to the specified
- * parameters in the RCC_PeriphCLKInitTypeDef.
- * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
- * contains a field PeriphClockSelection which can be a combination of the following values:
- * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
- @if STM32L462xx
- * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM1)
- @endif
- @if STM32L486xx
- * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM1)
- @endif
- @if STM32L4A6xx
- * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM1)
- @endif
- * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
- @if STM32L462xx
- * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4)
- @endif
- @if STM32L4A6xx
- * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4)
- @endif
- @if STM32L4S9xx
- * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4)
- @endif
- * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
- * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (only for devices with SAI1)
- @if STM32L486xx
- * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2)
- @endif
- @if STM32L4A6xx
- * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2)
- @endif
- @if STM32L4S9xx
- * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2)
- @endif
- * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock
- @if STM32L443xx
- * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1)
- @endif
- @if STM32L486xx
- * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1)
- @endif
- @if STM32L4A6xx
- * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1)
- @endif
- * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USART2 USART1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USART3 USART1 peripheral clock
- @if STM32L462xx
- * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4)
- @endif
- @if STM32L486xx
- * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4)
- * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5)
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB)
- @endif
- @if STM32L4A6xx
- * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4)
- * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5)
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB)
- @endif
- @if STM32L4S9xx
- * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4)
- * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5)
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB)
- * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral kernel clock (only for devices with DFSDM1)
- * @arg @ref RCC_PERIPHCLK_DFSDM1AUDIO DFSDM1 peripheral audio clock (only for devices with DFSDM1)
- * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (only for devices with LTDC)
- * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock (only for devices with DSI)
- * @arg @ref RCC_PERIPHCLK_OSPI OctoSPI peripheral clock (only for devices with OctoSPI)
- @endif
- *
- * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
- * the RTC clock source: in this case the access to Backup domain is enabled.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
-{
- uint32_t tmpregister, tickstart; /* no init needed */
- HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
- HAL_StatusTypeDef status = HAL_OK; /* Final status */
-
- /* Check the parameters */
- assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
-#if defined(SAI1)
-
- /*-------------------------- SAI1 clock source configuration ---------------------*/
- if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
- {
- /* Check the parameters */
- assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
-
- switch(PeriphClkInit->Sai1ClockSelection)
- {
- case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
- /* Enable SAI Clock output generated from System PLL . */
-#if defined(RCC_PLLSAI2_SUPPORT)
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
-#else
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
-#endif /* RCC_PLLSAI2_SUPPORT */
- /* SAI1 clock source config set later after clock selection check */
- break;
-
- case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/
- /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
- ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
- /* SAI1 clock source config set later after clock selection check */
- break;
-
-#if defined(RCC_PLLSAI2_SUPPORT)
-
- case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/
- /* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */
- ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
- /* SAI1 clock source config set later after clock selection check */
- break;
-
-#endif /* RCC_PLLSAI2_SUPPORT */
-
- case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
- case RCC_SAI1CLKSOURCE_HSI: /* HSI is used as source of SAI1 clock*/
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
- /* SAI1 clock source config set later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of SAI1 clock*/
- __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
- }
- else
- {
- /* set overall return value */
- status = ret;
- }
- }
-
-#endif /* SAI1 */
-
-#if defined(SAI2)
-
- /*-------------------------- SAI2 clock source configuration ---------------------*/
- if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
- {
- /* Check the parameters */
- assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));
-
- switch(PeriphClkInit->Sai2ClockSelection)
- {
- case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
- /* Enable SAI Clock output generated from System PLL . */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
- /* SAI2 clock source config set later after clock selection check */
- break;
-
- case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
- /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
- ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
- /* SAI2 clock source config set later after clock selection check */
- break;
-
- case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/
- /* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */
- ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
- /* SAI2 clock source config set later after clock selection check */
- break;
-
- case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
- case RCC_SAI2CLKSOURCE_HSI: /* HSI is used as source of SAI2 clock*/
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
- /* SAI2 clock source config set later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of SAI2 clock*/
- __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
- }
- else
- {
- /* set overall return value */
- status = ret;
- }
- }
-#endif /* SAI2 */
-
- /*-------------------------- RTC clock source configuration ----------------------*/
- if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
- {
- FlagStatus pwrclkchanged = RESET;
-
- /* Check for RTC Parameters used to output RTCCLK */
- assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
- /* Enable Power Clock */
- if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
- {
- __HAL_RCC_PWR_CLK_ENABLE();
- pwrclkchanged = SET;
- }
-
- /* Enable write access to Backup domain */
- SET_BIT(PWR->CR1, PWR_CR1_DBP);
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
- {
- if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- {
- ret = HAL_TIMEOUT;
- break;
- }
- }
-
- if(ret == HAL_OK)
- {
- /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
- tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
-
- if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
- {
- /* Store the content of BDCR register before the reset of Backup Domain */
- tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
- /* RTC Clock selection can be changed only if the Backup Domain is reset */
- __HAL_RCC_BACKUPRESET_FORCE();
- __HAL_RCC_BACKUPRESET_RELEASE();
- /* Restore the Content of BDCR register */
- RCC->BDCR = tmpregister;
- }
-
- /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
- if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
- {
- if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
- {
- ret = HAL_TIMEOUT;
- break;
- }
- }
- }
-
- if(ret == HAL_OK)
- {
- /* Apply new RTC clock source selection */
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
- }
- else
- {
- /* set overall return value */
- status = ret;
- }
- }
- else
- {
- /* set overall return value */
- status = ret;
- }
-
- /* Restore clock configuration if changed */
- if(pwrclkchanged == SET)
- {
- __HAL_RCC_PWR_CLK_DISABLE();
- }
- }
-
- /*-------------------------- USART1 clock source configuration -------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
-
- /* Configure the USART1 clock source */
- __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
- }
-
- /*-------------------------- USART2 clock source configuration -------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
-
- /* Configure the USART2 clock source */
- __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
- }
-
-#if defined(USART3)
-
- /*-------------------------- USART3 clock source configuration -------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
-
- /* Configure the USART3 clock source */
- __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
- }
-
-#endif /* USART3 */
-
-#if defined(UART4)
-
- /*-------------------------- UART4 clock source configuration --------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
-
- /* Configure the UART4 clock source */
- __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
- }
-
-#endif /* UART4 */
-
-#if defined(UART5)
-
- /*-------------------------- UART5 clock source configuration --------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
-
- /* Configure the UART5 clock source */
- __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
- }
-
-#endif /* UART5 */
-
- /*-------------------------- LPUART1 clock source configuration ------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
- {
- /* Check the parameters */
- assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
-
- /* Configure the LPUART1 clock source */
- __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
- }
-
- /*-------------------------- LPTIM1 clock source configuration -------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
- {
- assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
- __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
- }
-
- /*-------------------------- LPTIM2 clock source configuration -------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
- {
- assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
- __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
- }
-
- /*-------------------------- I2C1 clock source configuration ---------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
-
- /* Configure the I2C1 clock source */
- __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
- }
-
-#if defined(I2C2)
-
- /*-------------------------- I2C2 clock source configuration ---------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
-
- /* Configure the I2C2 clock source */
- __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
- }
-
-#endif /* I2C2 */
-
- /*-------------------------- I2C3 clock source configuration ---------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
-
- /* Configure the I2C3 clock source */
- __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
- }
-
-#if defined(I2C4)
-
- /*-------------------------- I2C4 clock source configuration ---------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
-
- /* Configure the I2C4 clock source */
- __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
- }
-
-#endif /* I2C4 */
-
-#if defined(USB_OTG_FS) || defined(USB)
-
- /*-------------------------- USB clock source configuration ----------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
- {
- assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
- __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
-
- if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
- {
- /* Enable PLL48M1CLK output clock */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
- }
- else
- {
-#if defined(RCC_PLLSAI1_SUPPORT)
- if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
- {
- /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
- ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
-
- if(ret != HAL_OK)
- {
- /* set overall return value */
- status = ret;
- }
- }
-#endif /* RCC_PLLSAI1_SUPPORT */
- }
- }
-
-#endif /* USB_OTG_FS || USB */
-
-#if defined(SDMMC1)
-
- /*-------------------------- SDMMC1 clock source configuration -------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
- {
- assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
- __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
-
- if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */
- {
- /* Enable PLL48M1CLK output clock */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
- }
-#if defined(RCC_CCIPR2_SDMMCSEL)
- else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLP) /* PLL "P" ? */
- {
- /* Enable PLLSAI3CLK output */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
- }
-#endif
- else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
- {
- /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
- ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
-
- if(ret != HAL_OK)
- {
- /* set overall return value */
- status = ret;
- }
- }
- else
- {
- /* nothing to do */
- }
- }
-
-#endif /* SDMMC1 */
-
- /*-------------------------- RNG clock source configuration ----------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
- {
- assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
- __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
-
- if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
- {
- /* Enable PLL48M1CLK output clock */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
- }
-#if defined(RCC_PLLSAI1_SUPPORT)
- else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
- {
- /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
- ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
-
- if(ret != HAL_OK)
- {
- /* set overall return value */
- status = ret;
- }
- }
-#endif /* RCC_PLLSAI1_SUPPORT */
- else
- {
- /* nothing to do */
- }
- }
-
- /*-------------------------- ADC clock source configuration ----------------------*/
-#if !defined(STM32L412xx) && !defined(STM32L422xx)
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
- {
- /* Check the parameters */
- assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
-
- /* Configure the ADC interface clock source */
- __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
-
-#if defined(RCC_PLLSAI1_SUPPORT)
- if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
- {
- /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
- ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
-
- if(ret != HAL_OK)
- {
- /* set overall return value */
- status = ret;
- }
- }
-#endif /* RCC_PLLSAI1_SUPPORT */
-
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
-
- else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
- {
- /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
- ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
-
- if(ret != HAL_OK)
- {
- /* set overall return value */
- status = ret;
- }
- }
-
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
-
- }
-#endif /* !STM32L412xx && !STM32L422xx */
-
-#if defined(SWPMI1)
-
- /*-------------------------- SWPMI1 clock source configuration -------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
- {
- /* Check the parameters */
- assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
-
- /* Configure the SWPMI1 clock source */
- __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
- }
-
-#endif /* SWPMI1 */
-
-#if defined(DFSDM1_Filter0)
-
- /*-------------------------- DFSDM1 clock source configuration -------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
- {
- /* Check the parameters */
- assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
-
- /* Configure the DFSDM1 interface clock source */
- __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
- }
-
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
- /*-------------------------- DFSDM1 audio clock source configuration -------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO)
- {
- /* Check the parameters */
- assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
-
- /* Configure the DFSDM1 interface audio clock source */
- __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
- }
-
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-#endif /* DFSDM1_Filter0 */
-
-#if defined(LTDC)
-
- /*-------------------------- LTDC clock source configuration --------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
- {
- /* Check the parameters */
- assert_param(IS_RCC_LTDCCLKSOURCE(PeriphClkInit->LtdcClockSelection));
-
- /* Disable the PLLSAI2 */
- __HAL_RCC_PLLSAI2_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLLSAI2 is ready */
- while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
- {
- if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
- {
- ret = HAL_TIMEOUT;
- break;
- }
- }
-
- if(ret == HAL_OK)
- {
- /* Configure the LTDC clock source */
- __HAL_RCC_LTDC_CONFIG(PeriphClkInit->LtdcClockSelection);
-
- /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
- ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
- }
-
- if(ret != HAL_OK)
- {
- /* set overall return value */
- status = ret;
- }
- }
-
-#endif /* LTDC */
-
-#if defined(DSI)
-
- /*-------------------------- DSI clock source configuration ---------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)
- {
- /* Check the parameters */
- assert_param(IS_RCC_DSICLKSOURCE(PeriphClkInit->DsiClockSelection));
-
- /* Configure the DSI clock source */
- __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);
-
- if(PeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLLSAI2)
- {
- /* PLLSAI2 input clock, parameters M, N & Q configuration and clock output (PLLSAI2ClockOut) */
- ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_Q_UPDATE);
-
- if(ret != HAL_OK)
- {
- /* set overall return value */
- status = ret;
- }
- }
- }
-
-#endif /* DSI */
-
-#if defined(OCTOSPI1) || defined(OCTOSPI2)
-
- /*-------------------------- OctoSPIx clock source configuration ----------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
- {
- /* Check the parameters */
- assert_param(IS_RCC_OSPICLKSOURCE(PeriphClkInit->OspiClockSelection));
-
- /* Configure the OctoSPI clock source */
- __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);
-
- if(PeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL)
- {
- /* Enable PLL48M1CLK output */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
- }
- }
-
-#endif /* OCTOSPI1 || OCTOSPI2 */
-
- return status;
-}
-
-/**
- * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
- * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
- * returns the configuration information for the Extended Peripherals
- * clocks(SAI1, SAI2, LPTIM1, LPTIM2, I2C1, I2C2, I2C3, I2C4, LPUART1,
- * USART1, USART2, USART3, UART4, UART5, RTC, ADCx, DFSDMx, SWPMI1, USB, SDMMC1 and RNG).
- * @retval None
- */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
-{
- /* Set all possible values for the extended clock type parameter------------*/
-
-#if defined(STM32L412xx) || defined(STM32L422xx)
-
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_USB | \
- RCC_PERIPHCLK_RNG | \
- RCC_PERIPHCLK_RTC ;
-
-#elif defined(STM32L431xx)
-
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | \
- RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \
- RCC_PERIPHCLK_RTC ;
-
-#elif defined(STM32L432xx) || defined(STM32L442xx)
-
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
- RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \
- RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \
- RCC_PERIPHCLK_RTC ;
-
-#elif defined(STM32L433xx) || defined(STM32L443xx)
-
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \
- RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \
- RCC_PERIPHCLK_RTC ;
-
-#elif defined(STM32L451xx)
-
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \
- RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | \
- RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \
- RCC_PERIPHCLK_RTC ;
-
-#elif defined(STM32L452xx) || defined(STM32L462xx)
-
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \
- RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \
- RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \
- RCC_PERIPHCLK_RTC ;
-
-#elif defined(STM32L471xx)
-
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
- RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
- RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
- RCC_PERIPHCLK_RTC ;
-
-#elif defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
-
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
- RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \
- RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
- RCC_PERIPHCLK_RTC ;
-
-#elif defined(STM32L496xx) || defined(STM32L4A6xx)
-
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
- RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \
- RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
- RCC_PERIPHCLK_RTC ;
-
-#elif defined(STM32L4R5xx) || defined(STM32L4S5xx)
-
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
- RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \
- RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \
- RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI;
-
-#elif defined(STM32L4R7xx) || defined(STM32L4S7xx) || defined(STM32L4Q5xx)
-
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
- RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \
- RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \
- RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC;
-
-#elif defined(STM32L4R9xx) || defined(STM32L4S9xx)
-
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
- RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \
- RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \
- RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_DSI;
-
-#endif /* STM32L431xx */
-
-#if defined(RCC_PLLSAI1_SUPPORT)
-
- /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/
-
- PeriphClkInit->PLLSAI1.PLLSAI1Source = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) >> RCC_PLLCFGR_PLLSRC_Pos;
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
- PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U;
-#else
- PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;
-#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
- PeriphClkInit->PLLSAI1.PLLSAI1N = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
- PeriphClkInit->PLLSAI1.PLLSAI1P = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) >> RCC_PLLSAI1CFGR_PLLSAI1P_Pos) << 4U) + 7U;
- PeriphClkInit->PLLSAI1.PLLSAI1Q = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) * 2U;
- PeriphClkInit->PLLSAI1.PLLSAI1R = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) * 2U;
-
-#endif /* RCC_PLLSAI1_SUPPORT */
-
-#if defined(RCC_PLLSAI2_SUPPORT)
-
- /* Get the PLLSAI2 Clock configuration -----------------------------------------------*/
-
- PeriphClkInit->PLLSAI2.PLLSAI2Source = PeriphClkInit->PLLSAI1.PLLSAI1Source;
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
- PeriphClkInit->PLLSAI2.PLLSAI2M = (READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U;
-#else
- PeriphClkInit->PLLSAI2.PLLSAI2M = PeriphClkInit->PLLSAI1.PLLSAI1M;
-#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
- PeriphClkInit->PLLSAI2.PLLSAI2N = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos;
- PeriphClkInit->PLLSAI2.PLLSAI2P = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) >> RCC_PLLSAI2CFGR_PLLSAI2P_Pos) << 4U) + 7U;
-#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
- PeriphClkInit->PLLSAI2.PLLSAI2Q = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) * 2U;
-#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
- PeriphClkInit->PLLSAI2.PLLSAI2R = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R)>> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) * 2U;
-
-#endif /* RCC_PLLSAI2_SUPPORT */
-
- /* Get the USART1 clock source ---------------------------------------------*/
- PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
- /* Get the USART2 clock source ---------------------------------------------*/
- PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
-
-#if defined(USART3)
- /* Get the USART3 clock source ---------------------------------------------*/
- PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
-#endif /* USART3 */
-
-#if defined(UART4)
- /* Get the UART4 clock source ----------------------------------------------*/
- PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
-#endif /* UART4 */
-
-#if defined(UART5)
- /* Get the UART5 clock source ----------------------------------------------*/
- PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
-#endif /* UART5 */
-
- /* Get the LPUART1 clock source --------------------------------------------*/
- PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
-
- /* Get the I2C1 clock source -----------------------------------------------*/
- PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
-
-#if defined(I2C2)
- /* Get the I2C2 clock source ----------------------------------------------*/
- PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
-#endif /* I2C2 */
-
- /* Get the I2C3 clock source -----------------------------------------------*/
- PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
-
-#if defined(I2C4)
- /* Get the I2C4 clock source -----------------------------------------------*/
- PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
-#endif /* I2C4 */
-
- /* Get the LPTIM1 clock source ---------------------------------------------*/
- PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
-
- /* Get the LPTIM2 clock source ---------------------------------------------*/
- PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
-
-#if defined(SAI1)
- /* Get the SAI1 clock source -----------------------------------------------*/
- PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
-#endif /* SAI1 */
-
-#if defined(SAI2)
- /* Get the SAI2 clock source -----------------------------------------------*/
- PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
-#endif /* SAI2 */
-
- /* Get the RTC clock source ------------------------------------------------*/
- PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
-
-#if defined(USB_OTG_FS) || defined(USB)
- /* Get the USB clock source ------------------------------------------------*/
- PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
-#endif /* USB_OTG_FS || USB */
-
-#if defined(SDMMC1)
- /* Get the SDMMC1 clock source ---------------------------------------------*/
- PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
-#endif /* SDMMC1 */
-
- /* Get the RNG clock source ------------------------------------------------*/
- PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
-
-#if !defined(STM32L412xx) && !defined(STM32L422xx)
- /* Get the ADC clock source ------------------------------------------------*/
- PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
-#endif /* !STM32L412xx && !STM32L422xx */
-
-#if defined(SWPMI1)
- /* Get the SWPMI1 clock source ---------------------------------------------*/
- PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE();
-#endif /* SWPMI1 */
-
-#if defined(DFSDM1_Filter0)
- /* Get the DFSDM1 clock source ---------------------------------------------*/
- PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
-
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
- /* Get the DFSDM1 audio clock source ---------------------------------------*/
- PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-#endif /* DFSDM1_Filter0 */
-
-#if defined(LTDC)
- /* Get the LTDC clock source -----------------------------------------------*/
- PeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE();
-#endif /* LTDC */
-
-#if defined(DSI)
- /* Get the DSI clock source ------------------------------------------------*/
- PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE();
-#endif /* DSI */
-
-#if defined(OCTOSPI1) || defined(OCTOSPI2)
- /* Get the OctoSPIclock source --------------------------------------------*/
- PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE();
-#endif /* OCTOSPI1 || OCTOSPI2 */
-}
-
-/**
- * @brief Return the peripheral clock frequency for peripherals with clock source from PLLSAIs
- * @note Return 0 if peripheral clock identifier not managed by this API
- * @param PeriphClk Peripheral clock identifier
- * This parameter can be one of the following values:
- * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
- @if STM32L462xx
- * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM)
- @endif
- @if STM32L486xx
- * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM)
- @endif
- @if STM32L4A6xx
- * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM)
- @endif
- * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
- @if STM32L462xx
- * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4)
- @endif
- @if STM32L4A6xx
- * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4)
- @endif
- @if STM32L4S9xx
- * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4)
- @endif
- * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
- * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (only for devices with SAI1)
- @if STM32L486xx
- * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2)
- @endif
- @if STM32L4A6xx
- * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2)
- @endif
- @if STM32L4S9xx
- * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2)
- @endif
- * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock
- @if STM32L443xx
- * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1)
- @endif
- @if STM32L486xx
- * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1)
- @endif
- @if STM32L4A6xx
- * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1)
- @endif
- * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USART2 USART1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USART3 USART1 peripheral clock
- @if STM32L462xx
- * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4)
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB)
- @endif
- @if STM32L486xx
- * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4)
- * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5)
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB)
- @endif
- @if STM32L4A6xx
- * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4)
- * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5)
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB)
- @endif
- @if STM32L4S9xx
- * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4)
- * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5)
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB)
- * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral kernel clock (only for devices with DFSDM1)
- * @arg @ref RCC_PERIPHCLK_DFSDM1AUDIO DFSDM1 peripheral audio clock (only for devices with DFSDM1)
- * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (only for devices with LTDC)
- * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock (only for devices with DSI)
- * @arg @ref RCC_PERIPHCLK_OSPI OctoSPI peripheral clock (only for devices with OctoSPI)
- @endif
- * @retval Frequency in Hz
- */
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
-{
- uint32_t frequency = 0U;
- uint32_t srcclk, pll_oscsource, pllvco, plln; /* no init needed */
-#if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL)
- uint32_t pllp; /* no init needed */
-#endif
-
- /* Check the parameters */
- assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
-
- if(PeriphClk == RCC_PERIPHCLK_RTC)
- {
- /* Get the current RTC source */
- srcclk = __HAL_RCC_GET_RTC_SOURCE();
-
- switch(srcclk)
- {
- case RCC_RTCCLKSOURCE_LSE:
- /* Check if LSE is ready */
- if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
- {
- frequency = LSE_VALUE;
- }
- break;
- case RCC_RTCCLKSOURCE_LSI:
- /* Check if LSI is ready */
- if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))
- {
-#if defined(RCC_CSR_LSIPREDIV)
- if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV))
- {
- frequency = LSI_VALUE/128U;
- }
- else
-#endif /* RCC_CSR_LSIPREDIV */
- {
- frequency = LSI_VALUE;
- }
- }
- break;
- case RCC_RTCCLKSOURCE_HSE_DIV32:
- /* Check if HSE is ready */
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
- {
- frequency = HSE_VALUE / 32U;
- }
- break;
- default:
- /* No clock source, frequency default init at 0 */
- break;
- }
- }
- else
- {
- /* Other external peripheral clock source than RTC */
- pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
-
- /* Compute PLL clock input */
- switch(pll_oscsource)
- {
- case RCC_PLLSOURCE_MSI: /* MSI ? */
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
- {
- /*MSI frequency range in HZ*/
- pllvco = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];
- }
- else
- {
- pllvco = 0U;
- }
- break;
- case RCC_PLLSOURCE_HSI: /* HSI ? */
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- pllvco = HSI_VALUE;
- }
- else
- {
- pllvco = 0U;
- }
- break;
- case RCC_PLLSOURCE_HSE: /* HSE ? */
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
- {
- pllvco = HSE_VALUE;
- }
- else
- {
- pllvco = 0U;
- }
- break;
- default:
- /* No source */
- pllvco = 0U;
- break;
- }
-
- switch(PeriphClk)
- {
-#if defined(SAI1)
-
- case RCC_PERIPHCLK_SAI1:
- frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI1, pllvco);
- break;
-
-#endif
-
-#if defined(SAI2)
-
- case RCC_PERIPHCLK_SAI2:
- frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI2, pllvco);
- break;
-
-#endif
-
-#if defined(USB_OTG_FS) || defined(USB)
-
- case RCC_PERIPHCLK_USB:
-
-#endif /* USB_OTG_FS || USB */
-
- case RCC_PERIPHCLK_RNG:
-
-#if defined(SDMMC1) && !defined(RCC_CCIPR2_SDMMCSEL)
-
- case RCC_PERIPHCLK_SDMMC1:
-
-#endif /* SDMMC1 && !RCC_CCIPR2_SDMMCSEL */
- {
- srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL);
-
- switch(srcclk)
- {
- case RCC_CCIPR_CLK48SEL: /* MSI ? */
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
- {
- /*MSI frequency range in HZ*/
- frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];
- }
- break;
- case RCC_CCIPR_CLK48SEL_1: /* PLL ? */
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
- {
- if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))
- {
- /* f(PLL Source) * PLLN / PLLM */
- plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
- pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
- /* f(PLL48M1CLK) = f(VCO input) / PLLQ */
- frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U));
- }
- }
- break;
-#if defined(RCC_PLLSAI1_SUPPORT)
- case RCC_CCIPR_CLK48SEL_0: /* PLLSAI1 ? */
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY))
- {
- if(HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN))
- {
- plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
- /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */
- /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */
- pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));
-#else
- /* f(PLL Source) * PLLSAI1N / PLLM */
- pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
-#endif
- /* f(PLL48M2CLK) = f(VCOSAI1 input) / PLLSAI1Q */
- frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U));
- }
- }
- break;
-#endif /* RCC_PLLSAI1_SUPPORT */
-#if defined(RCC_HSI48_SUPPORT)
- case 0U:
- if(HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) /* HSI48 ? */
- {
- frequency = HSI48_VALUE;
- }
- break;
-#endif /* RCC_HSI48_SUPPORT */
- default:
- /* No clock source, frequency default init at 0 */
- break;
- } /* switch(srcclk) */
- break;
- }
-
-#if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL)
-
- case RCC_PERIPHCLK_SDMMC1:
-
- if(HAL_IS_BIT_SET(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL)) /* PLL "P" ? */
- {
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
- {
- if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN))
- {
- /* f(PLL Source) * PLLN / PLLM */
- plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
- pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
- /* f(PLLSAI3CLK) = f(VCO input) / PLLP */
- pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
- if(pllp == 0U)
- {
- if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)
- {
- pllp = 17U;
- }
- else
- {
- pllp = 7U;
- }
- }
- frequency = (pllvco / pllp);
- }
- }
- }
- else /* 48MHz from PLL "Q" or MSI or PLLSAI1Q or HSI48 */
- {
- srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL);
-
- switch(srcclk)
- {
- case RCC_CCIPR_CLK48SEL: /* MSI ? */
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
- {
- /*MSI frequency range in HZ*/
- frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];
- }
- break;
- case RCC_CCIPR_CLK48SEL_1: /* PLL "Q" ? */
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
- {
- if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))
- {
- /* f(PLL Source) * PLLN / PLLM */
- plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
- pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
- /* f(PLL48M1CLK) = f(VCO input) / PLLQ */
- frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U));
- }
- }
- break;
- case RCC_CCIPR_CLK48SEL_0: /* PLLSAI1 ? */
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY))
- {
- if(HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN))
- {
- /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */
- plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
- pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));
- /* f(PLL48M2CLK) = f(VCOSAI1 input) / PLLSAI1Q */
- frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U));
- }
- }
- break;
- case 0U:
- if(HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) /* HSI48 ? */
- {
- frequency = HSI48_VALUE;
- }
- break;
- default:
- /* No clock source, frequency default init at 0 */
- break;
- } /* switch(srcclk) */
- }
- break;
-
-#endif /* SDMMC1 && RCC_CCIPR2_SDMMCSEL */
-
- case RCC_PERIPHCLK_USART1:
- {
- /* Get the current USART1 source */
- srcclk = __HAL_RCC_GET_USART1_SOURCE();
-
- switch(srcclk)
- {
- case RCC_USART1CLKSOURCE_PCLK2:
- frequency = HAL_RCC_GetPCLK2Freq();
- break;
- case RCC_USART1CLKSOURCE_SYSCLK:
- frequency = HAL_RCC_GetSysClockFreq();
- break;
- case RCC_USART1CLKSOURCE_HSI:
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- break;
- case RCC_USART1CLKSOURCE_LSE:
- if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
- {
- frequency = LSE_VALUE;
- }
- break;
- default:
- /* No clock source, frequency default init at 0 */
- break;
- }
-
- break;
- }
-
- case RCC_PERIPHCLK_USART2:
- {
- /* Get the current USART2 source */
- srcclk = __HAL_RCC_GET_USART2_SOURCE();
-
- switch(srcclk)
- {
- case RCC_USART2CLKSOURCE_PCLK1:
- frequency = HAL_RCC_GetPCLK1Freq();
- break;
- case RCC_USART2CLKSOURCE_SYSCLK:
- frequency = HAL_RCC_GetSysClockFreq();
- break;
- case RCC_USART2CLKSOURCE_HSI:
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- break;
- case RCC_USART2CLKSOURCE_LSE:
- if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
- {
- frequency = LSE_VALUE;
- }
- break;
- default:
- /* No clock source, frequency default init at 0 */
- break;
- }
-
- break;
- }
-
-#if defined(USART3)
-
- case RCC_PERIPHCLK_USART3:
- {
- /* Get the current USART3 source */
- srcclk = __HAL_RCC_GET_USART3_SOURCE();
-
- switch(srcclk)
- {
- case RCC_USART3CLKSOURCE_PCLK1:
- frequency = HAL_RCC_GetPCLK1Freq();
- break;
- case RCC_USART3CLKSOURCE_SYSCLK:
- frequency = HAL_RCC_GetSysClockFreq();
- break;
- case RCC_USART3CLKSOURCE_HSI:
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- break;
- case RCC_USART3CLKSOURCE_LSE:
- if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
- {
- frequency = LSE_VALUE;
- }
- break;
- default:
- /* No clock source, frequency default init at 0 */
- break;
- }
-
- break;
- }
-
-#endif /* USART3 */
-
-#if defined(UART4)
-
- case RCC_PERIPHCLK_UART4:
- {
- /* Get the current UART4 source */
- srcclk = __HAL_RCC_GET_UART4_SOURCE();
-
- switch(srcclk)
- {
- case RCC_UART4CLKSOURCE_PCLK1:
- frequency = HAL_RCC_GetPCLK1Freq();
- break;
- case RCC_UART4CLKSOURCE_SYSCLK:
- frequency = HAL_RCC_GetSysClockFreq();
- break;
- case RCC_UART4CLKSOURCE_HSI:
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- break;
- case RCC_UART4CLKSOURCE_LSE:
- if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
- {
- frequency = LSE_VALUE;
- }
- break;
- default:
- /* No clock source, frequency default init at 0 */
- break;
- }
-
- break;
- }
-
-#endif /* UART4 */
-
-#if defined(UART5)
-
- case RCC_PERIPHCLK_UART5:
- {
- /* Get the current UART5 source */
- srcclk = __HAL_RCC_GET_UART5_SOURCE();
-
- switch(srcclk)
- {
- case RCC_UART5CLKSOURCE_PCLK1:
- frequency = HAL_RCC_GetPCLK1Freq();
- break;
- case RCC_UART5CLKSOURCE_SYSCLK:
- frequency = HAL_RCC_GetSysClockFreq();
- break;
- case RCC_UART5CLKSOURCE_HSI:
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- break;
- case RCC_UART5CLKSOURCE_LSE:
- if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
- {
- frequency = LSE_VALUE;
- }
- break;
- default:
- /* No clock source, frequency default init at 0 */
- break;
- }
-
- break;
- }
-
-#endif /* UART5 */
-
- case RCC_PERIPHCLK_LPUART1:
- {
- /* Get the current LPUART1 source */
- srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
-
- switch(srcclk)
- {
- case RCC_LPUART1CLKSOURCE_PCLK1:
- frequency = HAL_RCC_GetPCLK1Freq();
- break;
- case RCC_LPUART1CLKSOURCE_SYSCLK:
- frequency = HAL_RCC_GetSysClockFreq();
- break;
- case RCC_LPUART1CLKSOURCE_HSI:
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- break;
- case RCC_LPUART1CLKSOURCE_LSE:
- if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
- {
- frequency = LSE_VALUE;
- }
- break;
- default:
- /* No clock source, frequency default init at 0 */
- break;
- }
-
- break;
- }
-
- case RCC_PERIPHCLK_ADC:
- {
- srcclk = __HAL_RCC_GET_ADC_SOURCE();
-
- switch(srcclk)
- {
- case RCC_ADCCLKSOURCE_SYSCLK:
- frequency = HAL_RCC_GetSysClockFreq();
- break;
-#if defined(RCC_PLLSAI1_SUPPORT)
- case RCC_ADCCLKSOURCE_PLLSAI1:
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && (__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != 0U))
- {
- plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
- /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */
- /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */
- pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));
-#else
- /* f(PLL Source) * PLLSAI1N / PLLM */
- pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
-#endif
- /* f(PLLADC1CLK) = f(VCOSAI1 input) / PLLSAI1R */
- frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U));
- }
- break;
-#endif /* RCC_PLLSAI1_SUPPORT */
-#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
- case RCC_ADCCLKSOURCE_PLLSAI2:
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI2RDY) && (__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != 0U))
- {
- plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos;
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
- /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */
- /* f(PLLSAI2 Source) * PLLSAI2N / PLLSAI2M */
- pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U));
-#else
- /* f(PLL Source) * PLLSAI2N / PLLM */
- pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
-#endif
- /* f(PLLADC2CLK) = f(VCOSAI2 input) / PLLSAI2R */
- frequency = (pllvco / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) << 1U));
- }
- break;
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
- default:
- /* No clock source, frequency default init at 0 */
- break;
- }
-
- break;
- }
-
-#if defined(DFSDM1_Filter0)
-
- case RCC_PERIPHCLK_DFSDM1:
- {
- /* Get the current DFSDM1 source */
- srcclk = __HAL_RCC_GET_DFSDM1_SOURCE();
-
- if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK2)
- {
- frequency = HAL_RCC_GetPCLK2Freq();
- }
- else
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
-
- break;
- }
-
-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-
- case RCC_PERIPHCLK_DFSDM1AUDIO:
- {
- /* Get the current DFSDM1 audio source */
- srcclk = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
-
- switch(srcclk)
- {
- case RCC_DFSDM1AUDIOCLKSOURCE_SAI1:
- frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI1, pllvco);
- break;
- case RCC_DFSDM1AUDIOCLKSOURCE_MSI:
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
- {
- /*MSI frequency range in HZ*/
- frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];
- }
- break;
- case RCC_DFSDM1AUDIOCLKSOURCE_HSI:
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- break;
- default:
- /* No clock source, frequency default init at 0 */
- break;
- }
-
- break;
- }
-
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-#endif /* DFSDM1_Filter0 */
-
- case RCC_PERIPHCLK_I2C1:
- {
- /* Get the current I2C1 source */
- srcclk = __HAL_RCC_GET_I2C1_SOURCE();
-
- switch(srcclk)
- {
- case RCC_I2C1CLKSOURCE_PCLK1:
- frequency = HAL_RCC_GetPCLK1Freq();
- break;
- case RCC_I2C1CLKSOURCE_SYSCLK:
- frequency = HAL_RCC_GetSysClockFreq();
- break;
- case RCC_I2C1CLKSOURCE_HSI:
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- break;
- default:
- /* No clock source, frequency default init at 0 */
- break;
- }
-
- break;
- }
-
-#if defined(I2C2)
-
- case RCC_PERIPHCLK_I2C2:
- {
- /* Get the current I2C2 source */
- srcclk = __HAL_RCC_GET_I2C2_SOURCE();
-
- switch(srcclk)
- {
- case RCC_I2C2CLKSOURCE_PCLK1:
- frequency = HAL_RCC_GetPCLK1Freq();
- break;
- case RCC_I2C2CLKSOURCE_SYSCLK:
- frequency = HAL_RCC_GetSysClockFreq();
- break;
- case RCC_I2C2CLKSOURCE_HSI:
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- break;
- default:
- /* No clock source, frequency default init at 0 */
- break;
- }
-
- break;
- }
-
-#endif /* I2C2 */
-
- case RCC_PERIPHCLK_I2C3:
- {
- /* Get the current I2C3 source */
- srcclk = __HAL_RCC_GET_I2C3_SOURCE();
-
- switch(srcclk)
- {
- case RCC_I2C3CLKSOURCE_PCLK1:
- frequency = HAL_RCC_GetPCLK1Freq();
- break;
- case RCC_I2C3CLKSOURCE_SYSCLK:
- frequency = HAL_RCC_GetSysClockFreq();
- break;
- case RCC_I2C3CLKSOURCE_HSI:
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- break;
- default:
- /* No clock source, frequency default init at 0 */
- break;
- }
-
- break;
- }
-
-#if defined(I2C4)
-
- case RCC_PERIPHCLK_I2C4:
- {
- /* Get the current I2C4 source */
- srcclk = __HAL_RCC_GET_I2C4_SOURCE();
-
- switch(srcclk)
- {
- case RCC_I2C4CLKSOURCE_PCLK1:
- frequency = HAL_RCC_GetPCLK1Freq();
- break;
- case RCC_I2C4CLKSOURCE_SYSCLK:
- frequency = HAL_RCC_GetSysClockFreq();
- break;
- case RCC_I2C4CLKSOURCE_HSI:
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- break;
- default:
- /* No clock source, frequency default init at 0 */
- break;
- }
-
- break;
- }
-
-#endif /* I2C4 */
-
- case RCC_PERIPHCLK_LPTIM1:
- {
- /* Get the current LPTIM1 source */
- srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
-
- switch(srcclk)
- {
- case RCC_LPTIM1CLKSOURCE_PCLK1:
- frequency = HAL_RCC_GetPCLK1Freq();
- break;
- case RCC_LPTIM1CLKSOURCE_LSI:
- if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))
- {
-#if defined(RCC_CSR_LSIPREDIV)
- if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV))
- {
- frequency = LSI_VALUE/128U;
- }
- else
-#endif /* RCC_CSR_LSIPREDIV */
- {
- frequency = LSI_VALUE;
- }
- }
- break;
- case RCC_LPTIM1CLKSOURCE_HSI:
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- break;
- case RCC_LPTIM1CLKSOURCE_LSE:
- if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
- {
- frequency = LSE_VALUE;
- }
- break;
- default:
- /* No clock source, frequency default init at 0 */
- break;
- }
-
- break;
- }
-
- case RCC_PERIPHCLK_LPTIM2:
- {
- /* Get the current LPTIM2 source */
- srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
-
- switch(srcclk)
- {
- case RCC_LPTIM2CLKSOURCE_PCLK1:
- frequency = HAL_RCC_GetPCLK1Freq();
- break;
- case RCC_LPTIM2CLKSOURCE_LSI:
- if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))
- {
-#if defined(RCC_CSR_LSIPREDIV)
- if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV))
- {
- frequency = LSI_VALUE/128U;
- }
- else
-#endif /* RCC_CSR_LSIPREDIV */
- {
- frequency = LSI_VALUE;
- }
- }
- break;
- case RCC_LPTIM2CLKSOURCE_HSI:
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- break;
- case RCC_LPTIM2CLKSOURCE_LSE:
- if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
- {
- frequency = LSE_VALUE;
- }
- break;
- default:
- /* No clock source, frequency default init at 0 */
- break;
- }
-
- break;
- }
-
-#if defined(SWPMI1)
-
- case RCC_PERIPHCLK_SWPMI1:
- {
- /* Get the current SWPMI1 source */
- srcclk = __HAL_RCC_GET_SWPMI1_SOURCE();
-
- switch(srcclk)
- {
- case RCC_SWPMI1CLKSOURCE_PCLK1:
- frequency = HAL_RCC_GetPCLK1Freq();
- break;
- case RCC_SWPMI1CLKSOURCE_HSI:
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- break;
- default:
- /* No clock source, frequency default init at 0 */
- break;
- }
-
- break;
- }
-
-#endif /* SWPMI1 */
-
-#if defined(OCTOSPI1) || defined(OCTOSPI2)
-
- case RCC_PERIPHCLK_OSPI:
- {
- /* Get the current OctoSPI clock source */
- srcclk = __HAL_RCC_GET_OSPI_SOURCE();
-
- switch(srcclk)
- {
- case RCC_OSPICLKSOURCE_SYSCLK:
- frequency = HAL_RCC_GetSysClockFreq();
- break;
- case RCC_OSPICLKSOURCE_MSI:
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
- {
- /*MSI frequency range in HZ*/
- frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];
- }
- break;
- case RCC_OSPICLKSOURCE_PLL:
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
- {
- if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))
- {
- /* f(PLL Source) * PLLN / PLLM */
- plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
- pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
- /* f(PLL48M1CLK) = f(VCO input) / PLLQ */
- frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U));
- }
- }
- break;
- default:
- /* No clock source, frequency default init at 0 */
- break;
- }
-
- break;
- }
-
-#endif /* OCTOSPI1 || OCTOSPI2 */
-
- default:
- break;
- }
- }
-
- return(frequency);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
- * @brief Extended Clock management functions
- *
-@verbatim
- ===============================================================================
- ##### Extended clock management functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the
- activation or deactivation of MSI PLL-mode, PLLSAI1, PLLSAI2, LSE CSS,
- Low speed clock output and clock after wake-up from STOP mode.
-@endverbatim
- * @{
- */
-
-#if defined(RCC_PLLSAI1_SUPPORT)
-
-/**
- * @brief Enable PLLSAI1.
- * @param PLLSAI1Init pointer to an RCC_PLLSAI1InitTypeDef structure that
- * contains the configuration information for the PLLSAI1
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init)
-{
- uint32_t tickstart;
- HAL_StatusTypeDef status = HAL_OK;
-
- /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
- assert_param(IS_RCC_PLLSAI1SOURCE(PLLSAI1Init->PLLSAI1Source));
- assert_param(IS_RCC_PLLSAI1M_VALUE(PLLSAI1Init->PLLSAI1M));
- assert_param(IS_RCC_PLLSAI1N_VALUE(PLLSAI1Init->PLLSAI1N));
- assert_param(IS_RCC_PLLSAI1P_VALUE(PLLSAI1Init->PLLSAI1P));
- assert_param(IS_RCC_PLLSAI1Q_VALUE(PLLSAI1Init->PLLSAI1Q));
- assert_param(IS_RCC_PLLSAI1R_VALUE(PLLSAI1Init->PLLSAI1R));
- assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1Init->PLLSAI1ClockOut));
-
- /* Disable the PLLSAI1 */
- __HAL_RCC_PLLSAI1_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLLSAI1 is ready to be updated */
- while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
- {
- if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
- {
- status = HAL_TIMEOUT;
- break;
- }
- }
-
- if(status == HAL_OK)
- {
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
- /* Configure the PLLSAI1 Multiplication factor N */
- /* Configure the PLLSAI1 Division factors M, P, Q and R */
- __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1M, PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R);
-#else
- /* Configure the PLLSAI1 Multiplication factor N */
- /* Configure the PLLSAI1 Division factors P, Q and R */
- __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R);
-#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
- /* Configure the PLLSAI1 Clock output(s) */
- __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1Init->PLLSAI1ClockOut);
-
- /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
- __HAL_RCC_PLLSAI1_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLLSAI1 is ready */
- while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
- {
- if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
- {
- status = HAL_TIMEOUT;
- break;
- }
- }
- }
-
- return status;
-}
-
-/**
- * @brief Disable PLLSAI1.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void)
-{
- uint32_t tickstart;
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Disable the PLLSAI1 */
- __HAL_RCC_PLLSAI1_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLLSAI1 is ready */
- while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
- {
- if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
- {
- status = HAL_TIMEOUT;
- break;
- }
- }
-
- /* Disable the PLLSAI1 Clock outputs */
- __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1CFGR_PLLSAI1PEN|RCC_PLLSAI1CFGR_PLLSAI1QEN|RCC_PLLSAI1CFGR_PLLSAI1REN);
-
- /* Reset PLL source to save power if no PLLs on */
-#if defined(RCC_PLLSAI2_SUPPORT)
- if(READ_BIT(RCC->CR, (RCC_CR_PLLRDY | RCC_CR_PLLSAI2RDY)) == 0U)
- {
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
- }
-#else
- if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
- {
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
- }
-#endif /* RCC_PLLSAI2_SUPPORT */
-
- return status;
-}
-
-#endif /* RCC_PLLSAI1_SUPPORT */
-
-#if defined(RCC_PLLSAI2_SUPPORT)
-
-/**
- * @brief Enable PLLSAI2.
- * @param PLLSAI2Init pointer to an RCC_PLLSAI2InitTypeDef structure that
- * contains the configuration information for the PLLSAI2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init)
-{
- uint32_t tickstart;
- HAL_StatusTypeDef status = HAL_OK;
-
- /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */
- assert_param(IS_RCC_PLLSAI2SOURCE(PLLSAI2Init->PLLSAI2Source));
- assert_param(IS_RCC_PLLSAI2M_VALUE(PLLSAI2Init->PLLSAI2M));
- assert_param(IS_RCC_PLLSAI2N_VALUE(PLLSAI2Init->PLLSAI2N));
- assert_param(IS_RCC_PLLSAI2P_VALUE(PLLSAI2Init->PLLSAI2P));
-#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
- assert_param(IS_RCC_PLLSAI2Q_VALUE(PLLSAI2Init->PLLSAI2Q));
-#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
- assert_param(IS_RCC_PLLSAI2R_VALUE(PLLSAI2Init->PLLSAI2R));
- assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PLLSAI2Init->PLLSAI2ClockOut));
-
- /* Disable the PLLSAI2 */
- __HAL_RCC_PLLSAI2_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLLSAI2 is ready to be updated */
- while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
- {
- if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
- {
- status = HAL_TIMEOUT;
- break;
- }
- }
-
- if(status == HAL_OK)
- {
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT)
- /* Configure the PLLSAI2 Multiplication factor N */
- /* Configure the PLLSAI2 Division factors M, P, Q and R */
- __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R);
-#elif defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
- /* Configure the PLLSAI2 Multiplication factor N */
- /* Configure the PLLSAI2 Division factors M, P and R */
- __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R);
-#elif defined(RCC_PLLSAI2Q_DIV_SUPPORT)
- /* Configure the PLLSAI2 Multiplication factor N */
- /* Configure the PLLSAI2 Division factors P, Q and R */
- __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R);
-#else
- /* Configure the PLLSAI2 Multiplication factor N */
- /* Configure the PLLSAI2 Division factors P and R */
- __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R);
-#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */
- /* Configure the PLLSAI2 Clock output(s) */
- __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PLLSAI2Init->PLLSAI2ClockOut);
-
- /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
- __HAL_RCC_PLLSAI2_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLLSAI2 is ready */
- while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
- {
- if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
- {
- status = HAL_TIMEOUT;
- break;
- }
- }
- }
-
- return status;
-}
-
-/**
- * @brief Disable PLLISAI2.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void)
-{
- uint32_t tickstart;
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Disable the PLLSAI2 */
- __HAL_RCC_PLLSAI2_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLLSAI2 is ready */
- while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
- {
- if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
- {
- status = HAL_TIMEOUT;
- break;
- }
- }
-
- /* Disable the PLLSAI2 Clock outputs */
-#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
- __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2QEN|RCC_PLLSAI2CFGR_PLLSAI2REN);
-#else
- __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2REN);
-#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */
-
- /* Reset PLL source to save power if no PLLs on */
- if(READ_BIT(RCC->CR, (RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY)) == 0U)
- {
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
- }
-
- return status;
-}
-
-#endif /* RCC_PLLSAI2_SUPPORT */
-
-/**
- * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
- * @param WakeUpClk Wakeup clock
- * This parameter can be one of the following values:
- * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI oscillator selection
- * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection
- * @note This function shall not be called after the Clock Security System on HSE has been
- * enabled.
- * @retval None
- */
-void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
-{
- assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
-
- __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
-}
-
-/**
- * @brief Configure the MSI range after standby mode.
- * @note After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
- * @param MSIRange MSI range
- * This parameter can be one of the following values:
- * @arg @ref RCC_MSIRANGE_4 Range 4 around 1 MHz
- * @arg @ref RCC_MSIRANGE_5 Range 5 around 2 MHz
- * @arg @ref RCC_MSIRANGE_6 Range 6 around 4 MHz (reset value)
- * @arg @ref RCC_MSIRANGE_7 Range 7 around 8 MHz
- * @retval None
- */
-void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange)
-{
- assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange));
-
- __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange);
-}
-
-/**
- * @brief Enable the LSE Clock Security System.
- * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
- * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
- * clock with HAL_RCCEx_PeriphCLKConfig().
- * @retval None
- */
-void HAL_RCCEx_EnableLSECSS(void)
-{
- SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
-}
-
-/**
- * @brief Disable the LSE Clock Security System.
- * @note LSE Clock Security System can only be disabled after a LSE failure detection.
- * @retval None
- */
-void HAL_RCCEx_DisableLSECSS(void)
-{
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
-
- /* Disable LSE CSS IT if any */
- __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
-}
-
-/**
- * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
- * @note LSE Clock Security System Interrupt is mapped on RTC EXTI line 19
- * @retval None
- */
-void HAL_RCCEx_EnableLSECSS_IT(void)
-{
- /* Enable LSE CSS */
- SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
-
- /* Enable LSE CSS IT */
- __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
-
- /* Enable IT on EXTI Line 19 */
- __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
- __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
-}
-
-/**
- * @brief Handle the RCC LSE Clock Security System interrupt request.
- * @retval None
- */
-void HAL_RCCEx_LSECSS_IRQHandler(void)
-{
- /* Check RCC LSE CSSF flag */
- if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
- {
- /* RCC LSE Clock Security System interrupt user callback */
- HAL_RCCEx_LSECSS_Callback();
-
- /* Clear RCC LSE CSS pending bit */
- __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
- }
-}
-
-/**
- * @brief RCCEx LSE Clock Security System interrupt callback.
- * @retval none
- */
-__weak void HAL_RCCEx_LSECSS_Callback(void)
-{
- /* NOTE : This function should not be modified, when the callback is needed,
- the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
- */
-}
-
-/**
- * @brief Select the Low Speed clock source to output on LSCO pin (PA2).
- * @param LSCOSource specifies the Low Speed clock source to output.
- * This parameter can be one of the following values:
- * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
- * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
- * @retval None
- */
-void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
-{
- GPIO_InitTypeDef GPIO_InitStruct;
- FlagStatus pwrclkchanged = RESET;
- FlagStatus backupchanged = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
-
- /* LSCO Pin Clock Enable */
- __LSCO_CLK_ENABLE();
-
- /* Configure the LSCO pin in analog mode */
- GPIO_InitStruct.Pin = LSCO_PIN;
- GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);
-
- /* Update LSCOSEL clock source in Backup Domain control register */
- if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- {
- __HAL_RCC_PWR_CLK_ENABLE();
- pwrclkchanged = SET;
- }
- if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- {
- HAL_PWR_EnableBkUpAccess();
- backupchanged = SET;
- }
-
- MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
-
- if(backupchanged == SET)
- {
- HAL_PWR_DisableBkUpAccess();
- }
- if(pwrclkchanged == SET)
- {
- __HAL_RCC_PWR_CLK_DISABLE();
- }
-}
-
-/**
- * @brief Disable the Low Speed clock output.
- * @retval None
- */
-void HAL_RCCEx_DisableLSCO(void)
-{
- FlagStatus pwrclkchanged = RESET;
- FlagStatus backupchanged = RESET;
-
- /* Update LSCOEN bit in Backup Domain control register */
- if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- {
- __HAL_RCC_PWR_CLK_ENABLE();
- pwrclkchanged = SET;
- }
- if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- {
- /* Enable access to the backup domain */
- HAL_PWR_EnableBkUpAccess();
- backupchanged = SET;
- }
-
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
-
- /* Restore previous configuration */
- if(backupchanged == SET)
- {
- /* Disable access to the backup domain */
- HAL_PWR_DisableBkUpAccess();
- }
- if(pwrclkchanged == SET)
- {
- __HAL_RCC_PWR_CLK_DISABLE();
- }
-}
-
-/**
- * @brief Enable the PLL-mode of the MSI.
- * @note Prior to enable the PLL-mode of the MSI for automatic hardware
- * calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
- * @retval None
- */
-void HAL_RCCEx_EnableMSIPLLMode(void)
-{
- SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
-}
-
-/**
- * @brief Disable the PLL-mode of the MSI.
- * @note PLL-mode of the MSI is automatically reset when LSE oscillator is disabled.
- * @retval None
- */
-void HAL_RCCEx_DisableMSIPLLMode(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
-}
-
-#if defined (OCTOSPI1) && defined (OCTOSPI2)
-/**
- * @brief Configure OCTOSPI instances DQS delays.
- * @param Delay1 OCTOSPI1 DQS delay
- * @param Delay2 OCTOSPI2 DQS delay
- * @note Delay parameters stand for unitary delays from 0 to 15. Actual delay is Delay1 or Delay2 + 1.
- * @retval None
- */
-void HAL_RCCEx_OCTOSPIDelayConfig(uint32_t Delay1, uint32_t Delay2)
-{
- assert_param(IS_RCC_OCTOSPIDELAY(Delay1));
- assert_param(IS_RCC_OCTOSPIDELAY(Delay2));
-
- MODIFY_REG(RCC->DLYCFGR, RCC_DLYCFGR_OCTOSPI1_DLY|RCC_DLYCFGR_OCTOSPI2_DLY, (Delay1 | (Delay2 << RCC_DLYCFGR_OCTOSPI2_DLY_Pos))) ;
-}
-#endif /* OCTOSPI1 && OCTOSPI2 */
-
-/**
- * @}
- */
-
-#if defined(CRS)
-
-/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
- * @brief Extended Clock Recovery System Control functions
- *
-@verbatim
- ===============================================================================
- ##### Extended Clock Recovery System Control functions #####
- ===============================================================================
- [..]
- For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
-
- (#) In System clock config, HSI48 needs to be enabled
-
- (#) Enable CRS clock in IP MSP init which will use CRS functions
-
- (#) Call CRS functions as follows:
- (##) Prepare synchronization configuration necessary for HSI48 calibration
- (+++) Default values can be set for frequency Error Measurement (reload and error limit)
- and also HSI48 oscillator smooth trimming.
- (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
- directly reload value with target and sychronization frequencies values
- (##) Call function HAL_RCCEx_CRSConfig which
- (+++) Resets CRS registers to their default values.
- (+++) Configures CRS registers with synchronization configuration
- (+++) Enables automatic calibration and frequency error counter feature
- Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
- periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
- provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
- precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
- should be used as SYNC signal.
-
- (##) A polling function is provided to wait for complete synchronization
- (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
- (+++) According to CRS status, user can decide to adjust again the calibration or continue
- application if synchronization is OK
-
- (#) User can retrieve information related to synchronization in calling function
- HAL_RCCEx_CRSGetSynchronizationInfo()
-
- (#) Regarding synchronization status and synchronization information, user can try a new calibration
- in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
- Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
- it means that the actual frequency is lower than the target (and so, that the TRIM value should be
- incremented), while when it is detected during the upcounting phase it means that the actual frequency
- is higher (and that the TRIM value should be decremented).
-
- (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
- through CRS Handler (CRS_IRQn/CRS_IRQHandler)
- (++) Call function HAL_RCCEx_CRSConfig()
- (++) Enable CRS_IRQn (thanks to NVIC functions)
- (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
- (++) Implement CRS status management in the following user callbacks called from
- HAL_RCCEx_CRS_IRQHandler():
- (+++) HAL_RCCEx_CRS_SyncOkCallback()
- (+++) HAL_RCCEx_CRS_SyncWarnCallback()
- (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
- (+++) HAL_RCCEx_CRS_ErrorCallback()
-
- (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
- This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start automatic synchronization for polling mode
- * @param pInit Pointer on RCC_CRSInitTypeDef structure
- * @retval None
- */
-void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
-{
- uint32_t value; /* no init needed */
-
- /* Check the parameters */
- assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
- assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
- assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
- assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
- assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
- assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
-
- /* CONFIGURATION */
-
- /* Before configuration, reset CRS registers to their default values*/
- __HAL_RCC_CRS_FORCE_RESET();
- __HAL_RCC_CRS_RELEASE_RESET();
-
- /* Set the SYNCDIV[2:0] bits according to Prescaler value */
- /* Set the SYNCSRC[1:0] bits according to Source value */
- /* Set the SYNCSPOL bit according to Polarity value */
- value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
- /* Set the RELOAD[15:0] bits according to ReloadValue value */
- value |= pInit->ReloadValue;
- /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
- value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
- WRITE_REG(CRS->CFGR, value);
-
- /* Adjust HSI48 oscillator smooth trimming */
- /* Set the TRIM[6:0] bits for STM32L412xx/L422xx or TRIM[5:0] bits otherwise
- according to RCC_CRS_HSI48CalibrationValue value */
- MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
-
- /* START AUTOMATIC SYNCHRONIZATION*/
-
- /* Enable Automatic trimming & Frequency error counter */
- SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
-}
-
-/**
- * @brief Generate the software synchronization event
- * @retval None
- */
-void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
-{
- SET_BIT(CRS->CR, CRS_CR_SWSYNC);
-}
-
-/**
- * @brief Return synchronization info
- * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
- * @retval None
- */
-void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
-{
- /* Check the parameter */
- assert_param(pSynchroInfo != (void *)NULL);
-
- /* Get the reload value */
- pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
-
- /* Get HSI48 oscillator smooth trimming */
- pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
-
- /* Get Frequency error capture */
- pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
-
- /* Get Frequency error direction */
- pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
-}
-
-/**
-* @brief Wait for CRS Synchronization status.
-* @param Timeout Duration of the timeout
-* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
-* frequency.
-* @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
-* @retval Combination of Synchronization status
-* This parameter can be a combination of the following values:
-* @arg @ref RCC_CRS_TIMEOUT
-* @arg @ref RCC_CRS_SYNCOK
-* @arg @ref RCC_CRS_SYNCWARN
-* @arg @ref RCC_CRS_SYNCERR
-* @arg @ref RCC_CRS_SYNCMISS
-* @arg @ref RCC_CRS_TRIMOVF
-*/
-uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
-{
- uint32_t crsstatus = RCC_CRS_NONE;
- uint32_t tickstart;
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait for CRS flag or timeout detection */
- do
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
- {
- crsstatus = RCC_CRS_TIMEOUT;
- }
- }
- /* Check CRS SYNCOK flag */
- if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
- {
- /* CRS SYNC event OK */
- crsstatus |= RCC_CRS_SYNCOK;
-
- /* Clear CRS SYNC event OK bit */
- __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
- }
-
- /* Check CRS SYNCWARN flag */
- if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
- {
- /* CRS SYNC warning */
- crsstatus |= RCC_CRS_SYNCWARN;
-
- /* Clear CRS SYNCWARN bit */
- __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
- }
-
- /* Check CRS TRIM overflow flag */
- if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
- {
- /* CRS SYNC Error */
- crsstatus |= RCC_CRS_TRIMOVF;
-
- /* Clear CRS Error bit */
- __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
- }
-
- /* Check CRS Error flag */
- if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
- {
- /* CRS SYNC Error */
- crsstatus |= RCC_CRS_SYNCERR;
-
- /* Clear CRS Error bit */
- __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
- }
-
- /* Check CRS SYNC Missed flag */
- if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
- {
- /* CRS SYNC Missed */
- crsstatus |= RCC_CRS_SYNCMISS;
-
- /* Clear CRS SYNC Missed bit */
- __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
- }
-
- /* Check CRS Expected SYNC flag */
- if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
- {
- /* frequency error counter reached a zero value */
- __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
- }
- } while(RCC_CRS_NONE == crsstatus);
-
- return crsstatus;
-}
-
-/**
- * @brief Handle the Clock Recovery System interrupt request.
- * @retval None
- */
-void HAL_RCCEx_CRS_IRQHandler(void)
-{
- uint32_t crserror = RCC_CRS_NONE;
- /* Get current IT flags and IT sources values */
- uint32_t itflags = READ_REG(CRS->ISR);
- uint32_t itsources = READ_REG(CRS->CR);
-
- /* Check CRS SYNCOK flag */
- if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
- {
- /* Clear CRS SYNC event OK flag */
- WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
-
- /* user callback */
- HAL_RCCEx_CRS_SyncOkCallback();
- }
- /* Check CRS SYNCWARN flag */
- else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
- {
- /* Clear CRS SYNCWARN flag */
- WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
-
- /* user callback */
- HAL_RCCEx_CRS_SyncWarnCallback();
- }
- /* Check CRS Expected SYNC flag */
- else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
- {
- /* frequency error counter reached a zero value */
- WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
-
- /* user callback */
- HAL_RCCEx_CRS_ExpectedSyncCallback();
- }
- /* Check CRS Error flags */
- else
- {
- if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
- {
- if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
- {
- crserror |= RCC_CRS_SYNCERR;
- }
- if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
- {
- crserror |= RCC_CRS_SYNCMISS;
- }
- if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
- {
- crserror |= RCC_CRS_TRIMOVF;
- }
-
- /* Clear CRS Error flags */
- WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
-
- /* user error callback */
- HAL_RCCEx_CRS_ErrorCallback(crserror);
- }
- }
-}
-
-/**
- * @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
- * @retval none
- */
-__weak void HAL_RCCEx_CRS_SyncOkCallback(void)
-{
- /* NOTE : This function should not be modified, when the callback is needed,
- the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
- * @retval none
- */
-__weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
-{
- /* NOTE : This function should not be modified, when the callback is needed,
- the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
- * @retval none
- */
-__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
-{
- /* NOTE : This function should not be modified, when the callback is needed,
- the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief RCCEx Clock Recovery System Error interrupt callback.
- * @param Error Combination of Error status.
- * This parameter can be a combination of the following values:
- * @arg @ref RCC_CRS_SYNCERR
- * @arg @ref RCC_CRS_SYNCMISS
- * @arg @ref RCC_CRS_TRIMOVF
- * @retval none
- */
-__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(Error);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-#endif /* CRS */
-
-/**
- * @}
- */
-
-/** @addtogroup RCCEx_Private_Functions
- * @{
- */
-
-#if defined(RCC_PLLSAI1_SUPPORT)
-
-/**
- * @brief Configure the parameters N & P & optionally M of PLLSAI1 and enable PLLSAI1 output clock(s).
- * @param PllSai1 pointer to an RCC_PLLSAI1InitTypeDef structure that
- * contains the configuration parameters N & P & optionally M as well as PLLSAI1 output clock(s)
- * @param Divider divider parameter to be updated
- *
- * @note PLLSAI1 is temporary disable to apply new parameters
- *
- * @retval HAL status
- */
-static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
-{
- uint32_t tickstart;
- HAL_StatusTypeDef status = HAL_OK;
-
- /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
- /* P, Q and R dividers are verified in each specific divider case below */
- assert_param(IS_RCC_PLLSAI1SOURCE(PllSai1->PLLSAI1Source));
- assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
- assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
- assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
-
- /* Check that PLLSAI1 clock source and divider M can be applied */
- if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
- {
- /* PLL clock source and divider M already set, check that no request for change */
- if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
- ||
- (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
-#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
- ||
- (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)
-#endif
- )
- {
- status = HAL_ERROR;
- }
- }
- else
- {
- /* Check PLLSAI1 clock source availability */
- switch(PllSai1->PLLSAI1Source)
- {
- case RCC_PLLSOURCE_MSI:
- if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
- {
- status = HAL_ERROR;
- }
- break;
- case RCC_PLLSOURCE_HSI:
- if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
- {
- status = HAL_ERROR;
- }
- break;
- case RCC_PLLSOURCE_HSE:
- if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
- {
- if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
- {
- status = HAL_ERROR;
- }
- }
- break;
- default:
- status = HAL_ERROR;
- break;
- }
-
- if(status == HAL_OK)
- {
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
- /* Set PLLSAI1 clock source */
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);
-#else
- /* Set PLLSAI1 clock source and divider M */
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);
-#endif
- }
- }
-
- if(status == HAL_OK)
- {
- /* Disable the PLLSAI1 */
- __HAL_RCC_PLLSAI1_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLLSAI1 is ready to be updated */
- while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
- {
- if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
- {
- status = HAL_TIMEOUT;
- break;
- }
- }
-
- if(status == HAL_OK)
- {
- if(Divider == DIVIDER_P_UPDATE)
- {
- assert_param(IS_RCC_PLLSAI1P_VALUE(PllSai1->PLLSAI1P));
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
-
- /* Configure the PLLSAI1 Division factor M, P and Multiplication factor N*/
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
- MODIFY_REG(RCC->PLLSAI1CFGR,
- RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV | RCC_PLLSAI1CFGR_PLLSAI1M,
- (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
- (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) |
- ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
-#else
- MODIFY_REG(RCC->PLLSAI1CFGR,
- RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | RCC_PLLSAI1CFGR_PLLSAI1M,
- (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
- ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) |
- ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
-#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
-
-#else
- /* Configure the PLLSAI1 Division factor P and Multiplication factor N*/
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
- MODIFY_REG(RCC->PLLSAI1CFGR,
- RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
- (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
- (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos));
-#else
- MODIFY_REG(RCC->PLLSAI1CFGR,
- RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P,
- (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
- ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));
-#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
-
-#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
- }
- else if(Divider == DIVIDER_Q_UPDATE)
- {
- assert_param(IS_RCC_PLLSAI1Q_VALUE(PllSai1->PLLSAI1Q));
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
- /* Configure the PLLSAI1 Division factor M, Q and Multiplication factor N*/
- MODIFY_REG(RCC->PLLSAI1CFGR,
- RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1M,
- (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
- (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |
- ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
-#else
- /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
- MODIFY_REG(RCC->PLLSAI1CFGR,
- RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q,
- (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
- (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos));
-#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
- }
- else
- {
- assert_param(IS_RCC_PLLSAI1R_VALUE(PllSai1->PLLSAI1R));
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
- /* Configure the PLLSAI1 Division factor M, R and Multiplication factor N*/
- MODIFY_REG(RCC->PLLSAI1CFGR,
- RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1M,
- (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
- (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |
- ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
-#else
- /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
- MODIFY_REG(RCC->PLLSAI1CFGR,
- RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R,
- (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
- (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));
-#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
- }
-
- /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
- __HAL_RCC_PLLSAI1_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLLSAI1 is ready */
- while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
- {
- if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
- {
- status = HAL_TIMEOUT;
- break;
- }
- }
-
- if(status == HAL_OK)
- {
- /* Configure the PLLSAI1 Clock output(s) */
- __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
- }
- }
- }
-
- return status;
-}
-
-#endif /* RCC_PLLSAI1_SUPPORT */
-
-#if defined(RCC_PLLSAI2_SUPPORT)
-
-/**
- * @brief Configure the parameters N & P & optionally M of PLLSAI2 and enable PLLSAI2 output clock(s).
- * @param PllSai2 pointer to an RCC_PLLSAI2InitTypeDef structure that
- * contains the configuration parameters N & P & optionally M as well as PLLSAI2 output clock(s)
- * @param Divider divider parameter to be updated
- *
- * @note PLLSAI2 is temporary disable to apply new parameters
- *
- * @retval HAL status
- */
-static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
-{
- uint32_t tickstart;
- HAL_StatusTypeDef status = HAL_OK;
-
- /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */
- /* P, Q and R dividers are verified in each specific divider case below */
- assert_param(IS_RCC_PLLSAI2SOURCE(PllSai2->PLLSAI2Source));
- assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));
- assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
- assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));
-
- /* Check that PLLSAI2 clock source and divider M can be applied */
- if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
- {
- /* PLL clock source and divider M already set, check that no request for change */
- if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)
- ||
- (PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)
-#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
- ||
- (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M)
-#endif
- )
- {
- status = HAL_ERROR;
- }
- }
- else
- {
- /* Check PLLSAI2 clock source availability */
- switch(PllSai2->PLLSAI2Source)
- {
- case RCC_PLLSOURCE_MSI:
- if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
- {
- status = HAL_ERROR;
- }
- break;
- case RCC_PLLSOURCE_HSI:
- if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
- {
- status = HAL_ERROR;
- }
- break;
- case RCC_PLLSOURCE_HSE:
- if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
- {
- if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
- {
- status = HAL_ERROR;
- }
- }
- break;
- default:
- status = HAL_ERROR;
- break;
- }
-
- if(status == HAL_OK)
- {
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
- /* Set PLLSAI2 clock source */
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source);
-#else
- /* Set PLLSAI2 clock source and divider M */
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos);
-#endif
- }
- }
-
- if(status == HAL_OK)
- {
- /* Disable the PLLSAI2 */
- __HAL_RCC_PLLSAI2_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLLSAI2 is ready to be updated */
- while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
- {
- if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
- {
- status = HAL_TIMEOUT;
- break;
- }
- }
-
- if(status == HAL_OK)
- {
- if(Divider == DIVIDER_P_UPDATE)
- {
- assert_param(IS_RCC_PLLSAI2P_VALUE(PllSai2->PLLSAI2P));
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
-
- /* Configure the PLLSAI2 Division factor M, P and Multiplication factor N*/
-#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
- MODIFY_REG(RCC->PLLSAI2CFGR,
- RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV | RCC_PLLSAI2CFGR_PLLSAI2M,
- (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
- (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) |
- ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
-#else
- MODIFY_REG(RCC->PLLSAI2CFGR,
- RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | RCC_PLLSAI2CFGR_PLLSAI2M,
- (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
- ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) |
- ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
-#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
-
-#else
- /* Configure the PLLSAI2 Division factor P and Multiplication factor N*/
-#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
- MODIFY_REG(RCC->PLLSAI2CFGR,
- RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
- (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
- (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos));
-#else
- MODIFY_REG(RCC->PLLSAI2CFGR,
- RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P,
- (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
- ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos));
-#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
-
-#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
- }
-#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
- else if(Divider == DIVIDER_Q_UPDATE)
- {
- assert_param(IS_RCC_PLLSAI2Q_VALUE(PllSai2->PLLSAI2Q));
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
- /* Configure the PLLSAI2 Division factor M, Q and Multiplication factor N*/
- MODIFY_REG(RCC->PLLSAI2CFGR,
- RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2M,
- (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
- (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) |
- ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
-#else
- /* Configure the PLLSAI2 Division factor Q and Multiplication factor N*/
- MODIFY_REG(RCC->PLLSAI2CFGR,
- RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q,
- (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
- (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos));
-#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
- }
-#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
- else
- {
- assert_param(IS_RCC_PLLSAI2R_VALUE(PllSai2->PLLSAI2R));
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
- /* Configure the PLLSAI2 Division factor M, R and Multiplication factor N*/
- MODIFY_REG(RCC->PLLSAI2CFGR,
- RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2M,
- (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
- (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) |
- ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
-#else
- /* Configure the PLLSAI2 Division factor R and Multiplication factor N*/
- MODIFY_REG(RCC->PLLSAI2CFGR,
- RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R,
- (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
- (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos));
-#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
- }
-
- /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
- __HAL_RCC_PLLSAI2_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLLSAI2 is ready */
- while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
- {
- if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
- {
- status = HAL_TIMEOUT;
- break;
- }
- }
-
- if(status == HAL_OK)
- {
- /* Configure the PLLSAI2 Clock output(s) */
- __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
- }
- }
- }
-
- return status;
-}
-
-#endif /* RCC_PLLSAI2_SUPPORT */
-
-#if defined(SAI1)
-
-static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t InputFrequency)
-{
- uint32_t frequency = 0U;
- uint32_t srcclk = 0U;
- uint32_t pllvco, plln; /* no init needed */
-#if defined(RCC_PLLP_SUPPORT)
- uint32_t pllp = 0U;
-#endif /* RCC_PLLP_SUPPORT */
-
- /* Handle SAIx */
- if(PeriphClk == RCC_PERIPHCLK_SAI1)
- {
- srcclk = __HAL_RCC_GET_SAI1_SOURCE();
- if(srcclk == RCC_SAI1CLKSOURCE_PIN)
- {
- frequency = EXTERNAL_SAI1_CLOCK_VALUE;
- }
- /* Else, PLL clock output to check below */
- }
-#if defined(SAI2)
- else
- {
- if(PeriphClk == RCC_PERIPHCLK_SAI2)
- {
- srcclk = __HAL_RCC_GET_SAI2_SOURCE();
- if(srcclk == RCC_SAI2CLKSOURCE_PIN)
- {
- frequency = EXTERNAL_SAI2_CLOCK_VALUE;
- }
- /* Else, PLL clock output to check below */
- }
- }
-#endif /* SAI2 */
-
- if(frequency == 0U)
- {
- pllvco = InputFrequency;
-
-#if defined(SAI2)
- if((srcclk == RCC_SAI1CLKSOURCE_PLL) || (srcclk == RCC_SAI2CLKSOURCE_PLL))
- {
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != 0U))
- {
- /* f(PLL Source) / PLLM */
- pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
- /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */
- plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
-#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
- pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
-#endif
- if(pllp == 0U)
- {
- if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)
- {
- pllp = 17U;
- }
- else
- {
- pllp = 7U;
- }
- }
- frequency = (pllvco * plln) / pllp;
- }
- }
- else if(srcclk == 0U) /* RCC_SAI1CLKSOURCE_PLLSAI1 || RCC_SAI2CLKSOURCE_PLLSAI1 */
- {
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && (__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != 0U))
- {
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
- /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */
- /* f(PLLSAI1 Source) / PLLSAI1M */
- pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));
-#else
- /* f(PLL Source) / PLLM */
- pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
-#endif
- /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */
- plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
- pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos;
-#endif
- if(pllp == 0U)
- {
- if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != 0U)
- {
- pllp = 17U;
- }
- else
- {
- pllp = 7U;
- }
- }
- frequency = (pllvco * plln) / pllp;
- }
- }
-#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
- else if((srcclk == RCC_SAI1CLKSOURCE_HSI) || (srcclk == RCC_SAI2CLKSOURCE_HSI))
- {
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- frequency = HSI_VALUE;
- }
- }
-#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
-
-#else
- if(srcclk == RCC_SAI1CLKSOURCE_PLL)
- {
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != 0U))
- {
- /* f(PLL Source) / PLLM */
- pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
- /* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */
- plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
-#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
- pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
-#endif
- if(pllp == 0U)
- {
- if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)
- {
- pllp = 17U;
- }
- else
- {
- pllp = 7U;
- }
- }
- frequency = (pllvco * plln) / pllp;
- }
- else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- /* HSI automatically selected as clock source if PLLs not enabled */
- frequency = HSI_VALUE;
- }
- else
- {
- /* No clock source, frequency default init at 0 */
- }
- }
- else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1)
- {
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && (__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != 0U))
- {
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
- /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */
- /* f(PLLSAI1 Source) / PLLSAI1M */
- pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));
-#else
- /* f(PLL Source) / PLLM */
- pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
-#endif
- /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */
- plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
-#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
- pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos;
-#endif
- if(pllp == 0U)
- {
- if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != 0U)
- {
- pllp = 17U;
- }
- else
- {
- pllp = 7U;
- }
- }
- frequency = (pllvco * plln) / pllp;
- }
- else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
- {
- /* HSI automatically selected as clock source if PLLs not enabled */
- frequency = HSI_VALUE;
- }
- else
- {
- /* No clock source, frequency default init at 0 */
- }
- }
-#endif /* SAI2 */
-
-#if defined(RCC_PLLSAI2_SUPPORT)
-
- else if((srcclk == RCC_SAI1CLKSOURCE_PLLSAI2) || (srcclk == RCC_SAI2CLKSOURCE_PLLSAI2))
- {
- if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI2RDY) && (__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != 0U))
- {
-#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
- /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */
- /* f(PLLSAI2 Source) / PLLSAI2M */
- pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U));
-#else
- /* f(PLL Source) / PLLM */
- pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
-#endif
- /* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */
- plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos;
-#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
- pllp = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos;
-#endif
- if(pllp == 0U)
- {
- if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != 0U)
- {
- pllp = 17U;
- }
- else
- {
- pllp = 7U;
- }
- }
- frequency = (pllvco * plln) / pllp;
- }
- }
-
-#endif /* RCC_PLLSAI2_SUPPORT */
-
- else
- {
- /* No clock source, frequency default init at 0 */
- }
- }
-
-
- return frequency;
-}
-
-#endif /* SAI1 */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c
deleted file mode 100644
index c945979..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c
+++ /dev/null
@@ -1,7888 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_tim.c
- * @author MCD Application Team
- * @brief TIM HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Timer (TIM) peripheral:
- * + TIM Time Base Initialization
- * + TIM Time Base Start
- * + TIM Time Base Start Interruption
- * + TIM Time Base Start DMA
- * + TIM Output Compare/PWM Initialization
- * + TIM Output Compare/PWM Channel Configuration
- * + TIM Output Compare/PWM Start
- * + TIM Output Compare/PWM Start Interruption
- * + TIM Output Compare/PWM Start DMA
- * + TIM Input Capture Initialization
- * + TIM Input Capture Channel Configuration
- * + TIM Input Capture Start
- * + TIM Input Capture Start Interruption
- * + TIM Input Capture Start DMA
- * + TIM One Pulse Initialization
- * + TIM One Pulse Channel Configuration
- * + TIM One Pulse Start
- * + TIM Encoder Interface Initialization
- * + TIM Encoder Interface Start
- * + TIM Encoder Interface Start Interruption
- * + TIM Encoder Interface Start DMA
- * + Commutation Event configuration with Interruption and DMA
- * + TIM OCRef clear configuration
- * + TIM External Clock configuration
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### TIMER Generic features #####
- ==============================================================================
- [..] The Timer features include:
- (#) 16-bit up, down, up/down auto-reload counter.
- (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
- counter clock frequency either by any factor between 1 and 65536.
- (#) Up to 4 independent channels for:
- (++) Input Capture
- (++) Output Compare
- (++) PWM generation (Edge and Center-aligned Mode)
- (++) One-pulse mode output
- (#) Synchronization circuit to control the timer with external signals and to interconnect
- several timers together.
- (#) Supports incremental encoder for positioning purposes
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Initialize the TIM low level resources by implementing the following functions
- depending on the selected feature:
- (++) Time Base : HAL_TIM_Base_MspInit()
- (++) Input Capture : HAL_TIM_IC_MspInit()
- (++) Output Compare : HAL_TIM_OC_MspInit()
- (++) PWM generation : HAL_TIM_PWM_MspInit()
- (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
- (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
-
- (#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
- (##) TIM pins configuration
- (+++) Enable the clock for the TIM GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE();
- (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
-
- (#) The external Clock can be configured, if needed (the default clock is the
- internal clock from the APBx), using the following function:
- HAL_TIM_ConfigClockSource, the clock configuration should be done before
- any start function.
-
- (#) Configure the TIM in the desired functioning mode using one of the
- Initialization function of this driver:
- (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
- (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
- Output Compare signal.
- (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
- PWM signal.
- (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
- external signal.
- (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
- in One Pulse Mode.
- (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
-
- (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
- (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
- (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
- (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
- (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
- (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
- (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
-
- (#) The DMA Burst is managed with the two following functions:
- HAL_TIM_DMABurst_WriteStart()
- HAL_TIM_DMABurst_ReadStart()
-
- *** Callback registration ***
- =============================================
-
- [..]
- The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
- allows the user to configure dynamically the driver callbacks.
-
- [..]
- Use Function HAL_TIM_RegisterCallback() to register a callback.
- HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
- the Callback ID and a pointer to the user callback function.
-
- [..]
- Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
- weak function.
- HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
- and the Callback ID.
-
- [..]
- These functions allow to register/unregister following callbacks:
- (+) Base_MspInitCallback : TIM Base Msp Init Callback.
- (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
- (+) IC_MspInitCallback : TIM IC Msp Init Callback.
- (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
- (+) OC_MspInitCallback : TIM OC Msp Init Callback.
- (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
- (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
- (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
- (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
- (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
- (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
- (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
- (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
- (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
- (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
- (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
- (+) TriggerCallback : TIM Trigger Callback.
- (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
- (+) IC_CaptureCallback : TIM Input Capture Callback.
- (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
- (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
- (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
- (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
- (+) ErrorCallback : TIM Error Callback.
- (+) CommutationCallback : TIM Commutation Callback.
- (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
- (+) BreakCallback : TIM Break Callback.
- (+) Break2Callback : TIM Break2 Callback.
-
- [..]
-By default, after the Init and when the state is HAL_TIM_STATE_RESET
-all interrupt callbacks are set to the corresponding weak functions:
- examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
-
- [..]
- Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
- functionalities in the Init / DeInit only when these callbacks are null
- (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
- keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
-
- [..]
- Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
- Exception done MspInit / MspDeInit that can be registered / unregistered
- in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
- thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
- In that case first register the MspInit/MspDeInit user callbacks
- using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
-
- [..]
- When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registration feature is not available and all callbacks
- are set to the corresponding weak functions.
-
- @endverbatim
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup TIM TIM
- * @brief TIM HAL module driver
- * @{
- */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup TIM_Private_Functions
- * @{
- */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef *sSlaveConfig);
-/**
- * @}
- */
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup TIM_Exported_Functions TIM Exported Functions
- * @{
- */
-
-/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
- * @brief Time Base functions
- *
-@verbatim
- ==============================================================================
- ##### Time Base functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM base.
- (+) De-initialize the TIM base.
- (+) Start the Time Base.
- (+) Stop the Time Base.
- (+) Start the Time Base and enable interrupt.
- (+) Stop the Time Base and disable interrupt.
- (+) Start the Time Base and enable DMA transfer.
- (+) Stop the Time Base and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Time base Unit according to the specified
- * parameters in the TIM_HandleTypeDef and initialize the associated handle.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
- * requires a timer reset to avoid unexpected direction
- * due to DIR bit readonly in center aligned mode.
- * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{
- /* Check the TIM handle allocation */
- if (htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy weak callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->Base_MspInitCallback == NULL)
- {
- htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->Base_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- HAL_TIM_Base_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Set the Time Base configuration */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Initialize the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM Base peripheral
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->Base_MspDeInitCallback == NULL)
- {
- htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->Base_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIM_Base_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Change the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Base MSP.
- * @param htim TIM Base handle
- * @retval None
- */
-__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_Base_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Base MSP.
- * @param htim TIM Base handle
- * @retval None
- */
-__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_Base_MspDeInit could be implemented in the user file
- */
-}
-
-
-/**
- * @brief Starts the TIM Base generation.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Check the TIM state */
- if (htim->State != HAL_TIM_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Base generation.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Base generation in interrupt mode.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Check the TIM state */
- if (htim->State != HAL_TIM_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Enable the TIM Update interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Base generation in interrupt mode.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Disable the TIM Update interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Base generation in DMA mode.
- * @param htim TIM Base handle
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
- /* Set the TIM state */
- if (htim->State == HAL_TIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if (htim->State == HAL_TIM_STATE_READY)
- {
- if ((pData == NULL) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- else
- {
- return HAL_ERROR;
- }
-
- /* Set the DMA Period elapsed callbacks */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
- htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
-
- /* Enable the TIM Update DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Base generation in DMA mode.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
-
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
- * @brief TIM Output Compare functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Output Compare functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM Output Compare.
- (+) De-initialize the TIM Output Compare.
- (+) Start the TIM Output Compare.
- (+) Stop the TIM Output Compare.
- (+) Start the TIM Output Compare and enable interrupt.
- (+) Stop the TIM Output Compare and disable interrupt.
- (+) Start the TIM Output Compare and enable DMA transfer.
- (+) Stop the TIM Output Compare and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Output Compare according to the specified
- * parameters in the TIM_HandleTypeDef and initializes the associated handle.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
- * requires a timer reset to avoid unexpected direction
- * due to DIR bit readonly in center aligned mode.
- * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
- * @param htim TIM Output Compare handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
-{
- /* Check the TIM handle allocation */
- if (htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy weak callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->OC_MspInitCallback == NULL)
- {
- htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->OC_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_OC_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the Output Compare */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Initialize the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM peripheral
- * @param htim TIM Output Compare handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->OC_MspDeInitCallback == NULL)
- {
- htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->OC_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_OC_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Change the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Output Compare MSP.
- * @param htim TIM Output Compare handle
- * @retval None
- */
-__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Output Compare MSP.
- * @param htim TIM Output Compare handle
- * @retval None
- */
-__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM channel state */
- if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in interrupt mode.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM channel state */
- if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in interrupt mode.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in DMA mode.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Set the TIM channel state */
- if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
- {
- if ((pData == NULL) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- return HAL_ERROR;
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
-
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
-
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in DMA mode.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
- * @brief TIM PWM functions
- *
-@verbatim
- ==============================================================================
- ##### TIM PWM functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM PWM.
- (+) De-initialize the TIM PWM.
- (+) Start the TIM PWM.
- (+) Stop the TIM PWM.
- (+) Start the TIM PWM and enable interrupt.
- (+) Stop the TIM PWM and disable interrupt.
- (+) Start the TIM PWM and enable DMA transfer.
- (+) Stop the TIM PWM and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM PWM Time Base according to the specified
- * parameters in the TIM_HandleTypeDef and initializes the associated handle.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
- * requires a timer reset to avoid unexpected direction
- * due to DIR bit readonly in center aligned mode.
- * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
- * @param htim TIM PWM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
-{
- /* Check the TIM handle allocation */
- if (htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy weak callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->PWM_MspInitCallback == NULL)
- {
- htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->PWM_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_PWM_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the PWM */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Initialize the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM peripheral
- * @param htim TIM PWM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->PWM_MspDeInitCallback == NULL)
- {
- htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->PWM_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_PWM_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Change the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM PWM MSP.
- * @param htim TIM PWM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM PWM MSP.
- * @param htim TIM PWM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the PWM signal generation.
- * @param htim TIM handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM channel state */
- if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation.
- * @param htim TIM PWM handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the PWM signal generation in interrupt mode.
- * @param htim TIM PWM handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM channel state */
- if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the PWM signal generation in interrupt mode.
- * @param htim TIM PWM handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Starts the TIM PWM signal generation in DMA mode.
- * @param htim TIM PWM handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Set the TIM channel state */
- if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
- {
- if ((pData == NULL) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- return HAL_ERROR;
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
-
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Output Capture/Compare 3 request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the TIM PWM signal generation in DMA mode.
- * @param htim TIM PWM handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
- * @brief TIM Input Capture functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Input Capture functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM Input Capture.
- (+) De-initialize the TIM Input Capture.
- (+) Start the TIM Input Capture.
- (+) Stop the TIM Input Capture.
- (+) Start the TIM Input Capture and enable interrupt.
- (+) Stop the TIM Input Capture and disable interrupt.
- (+) Start the TIM Input Capture and enable DMA transfer.
- (+) Stop the TIM Input Capture and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Input Capture Time base according to the specified
- * parameters in the TIM_HandleTypeDef and initializes the associated handle.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
- * requires a timer reset to avoid unexpected direction
- * due to DIR bit readonly in center aligned mode.
- * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
- * @param htim TIM Input Capture handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
-{
- /* Check the TIM handle allocation */
- if (htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy weak callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->IC_MspInitCallback == NULL)
- {
- htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->IC_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_IC_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the input capture */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Initialize the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM peripheral
- * @param htim TIM Input Capture handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->IC_MspDeInitCallback == NULL)
- {
- htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->IC_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_IC_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Change the TIM channels state */
- TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Input Capture MSP.
- * @param htim TIM Input Capture handle
- * @retval None
- */
-__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_IC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Input Capture MSP.
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_IC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Input Capture measurement.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpsmcr;
- HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
- HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM channel state */
- if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Input Capture measurement.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Input Capture measurement in interrupt mode.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
- HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM channel state */
- if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the TIM Input Capture measurement in interrupt mode.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Starts the TIM Input Capture measurement in DMA mode.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData The destination Buffer address.
- * @param Length The length of data to be transferred from TIM peripheral to memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
- HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
- /* Set the TIM channel state */
- if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
- {
- if ((pData == NULL) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- return HAL_ERROR;
- }
-
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the TIM Input Capture measurement in DMA mode.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
- * @brief TIM One Pulse functions
- *
-@verbatim
- ==============================================================================
- ##### TIM One Pulse functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM One Pulse.
- (+) De-initialize the TIM One Pulse.
- (+) Start the TIM One Pulse.
- (+) Stop the TIM One Pulse.
- (+) Start the TIM One Pulse and enable interrupt.
- (+) Stop the TIM One Pulse and disable interrupt.
- (+) Start the TIM One Pulse and enable DMA transfer.
- (+) Stop the TIM One Pulse and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM One Pulse Time Base according to the specified
- * parameters in the TIM_HandleTypeDef and initializes the associated handle.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
- * requires a timer reset to avoid unexpected direction
- * due to DIR bit readonly in center aligned mode.
- * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
- * @note When the timer instance is initialized in One Pulse mode, timer
- * channels 1 and channel 2 are reserved and cannot be used for other
- * purpose.
- * @param htim TIM One Pulse handle
- * @param OnePulseMode Select the One pulse mode.
- * This parameter can be one of the following values:
- * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
- * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
-{
- /* Check the TIM handle allocation */
- if (htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_OPM_MODE(OnePulseMode));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy weak callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->OnePulse_MspInitCallback == NULL)
- {
- htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->OnePulse_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_OnePulse_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Configure the Time base in the One Pulse Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Reset the OPM Bit */
- htim->Instance->CR1 &= ~TIM_CR1_OPM;
-
- /* Configure the OPM Mode */
- htim->Instance->CR1 |= OnePulseMode;
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Initialize the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM One Pulse
- * @param htim TIM One Pulse handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->OnePulse_MspDeInitCallback == NULL)
- {
- htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->OnePulse_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIM_OnePulse_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM One Pulse MSP.
- * @param htim TIM One Pulse handle
- * @retval None
- */
-__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OnePulse_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM One Pulse MSP.
- * @param htim TIM One Pulse handle
- * @retval None
- */
-__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM One Pulse signal generation.
- * @note Though OutputChannel parameter is deprecated and ignored by the function
- * it has been kept to avoid HAL_TIM API compatibility break.
- * @note The pulse output channel is determined when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
- * @param htim TIM One Pulse handle
- * @param OutputChannel See note above
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
- No need to enable the counter, it's enabled automatically by hardware
- (the counter starts in response to a stimulus and generate a pulse */
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation.
- * @note Though OutputChannel parameter is deprecated and ignored by the function
- * it has been kept to avoid HAL_TIM API compatibility break.
- * @note The pulse output channel is determined when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
- * @param htim TIM One Pulse handle
- * @param OutputChannel See note above
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Disable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM One Pulse signal generation in interrupt mode.
- * @note Though OutputChannel parameter is deprecated and ignored by the function
- * it has been kept to avoid HAL_TIM API compatibility break.
- * @note The pulse output channel is determined when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
- * @param htim TIM One Pulse handle
- * @param OutputChannel See note above
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
- No need to enable the counter, it's enabled automatically by hardware
- (the counter starts in response to a stimulus and generate a pulse */
-
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation in interrupt mode.
- * @note Though OutputChannel parameter is deprecated and ignored by the function
- * it has been kept to avoid HAL_TIM API compatibility break.
- * @note The pulse output channel is determined when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
- * @param htim TIM One Pulse handle
- * @param OutputChannel See note above
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
- /* Disable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
- * @brief TIM Encoder functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Encoder functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM Encoder.
- (+) De-initialize the TIM Encoder.
- (+) Start the TIM Encoder.
- (+) Stop the TIM Encoder.
- (+) Start the TIM Encoder and enable interrupt.
- (+) Stop the TIM Encoder and disable interrupt.
- (+) Start the TIM Encoder and enable DMA transfer.
- (+) Stop the TIM Encoder and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
- * requires a timer reset to avoid unexpected direction
- * due to DIR bit readonly in center aligned mode.
- * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
- * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
- * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
- * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
- * @note When the timer instance is initialized in Encoder mode, timer
- * channels 1 and channel 2 are reserved and cannot be used for other
- * purpose.
- * @param htim TIM Encoder Interface handle
- * @param sConfig TIM Encoder Interface configuration structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
-{
- uint32_t tmpsmcr;
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Check the TIM handle allocation */
- if (htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
- assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
- assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
- assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
- assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy weak callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->Encoder_MspInitCallback == NULL)
- {
- htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->Encoder_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_Encoder_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Reset the SMS and ECE bits */
- htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
-
- /* Configure the Time base in the Encoder Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = htim->Instance->CCMR1;
-
- /* Get the TIMx CCER register value */
- tmpccer = htim->Instance->CCER;
-
- /* Set the encoder Mode */
- tmpsmcr |= sConfig->EncoderMode;
-
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
- tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
-
- /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
- tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
- tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
- tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
- tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
-
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
- tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
- tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
-
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
-
- /* Write to TIMx CCMR1 */
- htim->Instance->CCMR1 = tmpccmr1;
-
- /* Write to TIMx CCER */
- htim->Instance->CCER = tmpccer;
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-
-/**
- * @brief DeInitializes the TIM Encoder interface
- * @param htim TIM Encoder Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->Encoder_MspDeInitCallback == NULL)
- {
- htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->Encoder_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIM_Encoder_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Encoder Interface MSP.
- * @param htim TIM Encoder Interface handle
- * @retval None
- */
-__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_Encoder_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Encoder Interface MSP.
- * @param htim TIM Encoder Interface handle
- * @retval None
- */
-__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Encoder Interface.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- /* Set the TIM channel(s) state */
- if (Channel == TIM_CHANNEL_1)
- {
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else if (Channel == TIM_CHANNEL_2)
- {
- if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
-
- /* Enable the encoder interface channels */
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- break;
- }
-
- default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- break;
- }
- }
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Encoder Interface.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- break;
- }
-
- default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- break;
- }
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel(s) state */
- if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
- {
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Encoder Interface in interrupt mode.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- /* Set the TIM channel(s) state */
- if (Channel == TIM_CHANNEL_1)
- {
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else if (Channel == TIM_CHANNEL_2)
- {
- if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
-
- /* Enable the encoder interface channels */
- /* Enable the capture compare Interrupts 1 and/or 2 */
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Encoder Interface in interrupt mode.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- if (Channel == TIM_CHANNEL_1)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts 1 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- else if (Channel == TIM_CHANNEL_2)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts 2 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- else
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts 1 and 2 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel(s) state */
- if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
- {
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Encoder Interface in DMA mode.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @param pData1 The destination Buffer address for IC1.
- * @param pData2 The destination Buffer address for IC2.
- * @param Length The length of data to be transferred from TIM peripheral to memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
- uint32_t *pData2, uint16_t Length)
-{
- HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- /* Set the TIM channel(s) state */
- if (Channel == TIM_CHANNEL_1)
- {
- if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
- {
- if ((pData1 == NULL) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- return HAL_ERROR;
- }
- }
- else if (Channel == TIM_CHANNEL_2)
- {
- if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
- {
- if ((pData2 == NULL) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- return HAL_ERROR;
- }
- }
- else
- {
- if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
- {
- if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- return HAL_ERROR;
- }
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- break;
- }
-
- default:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
-
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
-
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- break;
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Encoder Interface in DMA mode.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- if (Channel == TIM_CHANNEL_1)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the capture compare DMA Request 1 */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- }
- else if (Channel == TIM_CHANNEL_2)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare DMA Request 2 */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- }
- else
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare DMA Request 1 and 2 */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel(s) state */
- if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
- {
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- * @brief TIM IRQ handler management
- *
-@verbatim
- ==============================================================================
- ##### IRQ handler management #####
- ==============================================================================
- [..]
- This section provides Timer IRQ handler function.
-
-@endverbatim
- * @{
- */
-/**
- * @brief This function handles TIM interrupts requests.
- * @param htim TIM handle
- * @retval None
- */
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
-{
- /* Capture compare 1 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
- {
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
- /* Input capture event */
- if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- /* Output compare event */
- else
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- }
- /* Capture compare 2 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- /* Input capture event */
- if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- /* Output compare event */
- else
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* Capture compare 3 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- /* Input capture event */
- if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- /* Output compare event */
- else
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* Capture compare 4 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- /* Input capture event */
- if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- /* Output compare event */
- else
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* TIM Update event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PeriodElapsedCallback(htim);
-#else
- HAL_TIM_PeriodElapsedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Break input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->BreakCallback(htim);
-#else
- HAL_TIMEx_BreakCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Break2 input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
- {
- __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->Break2Callback(htim);
-#else
- HAL_TIMEx_Break2Callback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Trigger detection event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->TriggerCallback(htim);
-#else
- HAL_TIM_TriggerCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM commutation event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->CommutationCallback(htim);
-#else
- HAL_TIMEx_CommutCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
- * @brief TIM Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
- (+) Configure External Clock source.
- (+) Configure Complementary channels, break features and dead time.
- (+) Configure Master and the Slave synchronization.
- (+) Configure the DMA Burst Mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the TIM Output Compare Channels according to the specified
- * parameters in the TIM_OC_InitTypeDef.
- * @param htim TIM Output Compare handle
- * @param sConfig TIM Output Compare configuration structure
- * @param Channel TIM Channels to configure
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_OC_InitTypeDef *sConfig,
- uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
- assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 1 in Output Compare */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 2 in Output Compare */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 3 in Output Compare */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 4 in Output Compare */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
- break;
- }
-
- case TIM_CHANNEL_5:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 5 in Output Compare */
- TIM_OC5_SetConfig(htim->Instance, sConfig);
- break;
- }
-
- case TIM_CHANNEL_6:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 6 in Output Compare */
- TIM_OC6_SetConfig(htim->Instance, sConfig);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- __HAL_UNLOCK(htim);
-
- return status;
-}
-
-/**
- * @brief Initializes the TIM Input Capture Channels according to the specified
- * parameters in the TIM_IC_InitTypeDef.
- * @param htim TIM IC handle
- * @param sConfig TIM Input Capture configuration structure
- * @param Channel TIM Channel to configure
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
- assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- if (Channel == TIM_CHANNEL_1)
- {
- /* TI1 Configuration */
- TIM_TI1_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
- /* Set the IC1PSC value */
- htim->Instance->CCMR1 |= sConfig->ICPrescaler;
- }
- else if (Channel == TIM_CHANNEL_2)
- {
- /* TI2 Configuration */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_TI2_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC2PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
- /* Set the IC2PSC value */
- htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
- }
- else if (Channel == TIM_CHANNEL_3)
- {
- /* TI3 Configuration */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- TIM_TI3_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC3PSC Bits */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
-
- /* Set the IC3PSC value */
- htim->Instance->CCMR2 |= sConfig->ICPrescaler;
- }
- else if (Channel == TIM_CHANNEL_4)
- {
- /* TI4 Configuration */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- TIM_TI4_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC4PSC Bits */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
-
- /* Set the IC4PSC value */
- htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
- }
- else
- {
- status = HAL_ERROR;
- }
-
- __HAL_UNLOCK(htim);
-
- return status;
-}
-
-/**
- * @brief Initializes the TIM PWM channels according to the specified
- * parameters in the TIM_OC_InitTypeDef.
- * @param htim TIM PWM handle
- * @param sConfig TIM PWM configuration structure
- * @param Channel TIM Channels to be configured
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_OC_InitTypeDef *sConfig,
- uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
- assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Configure the Channel 1 in PWM mode */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel1 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
- htim->Instance->CCMR1 |= sConfig->OCFastMode;
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Configure the Channel 2 in PWM mode */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel2 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
- htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Configure the Channel 3 in PWM mode */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel3 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode;
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Configure the Channel 4 in PWM mode */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel4 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
- break;
- }
-
- case TIM_CHANNEL_5:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
-
- /* Configure the Channel 5 in PWM mode */
- TIM_OC5_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel5*/
- htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
- htim->Instance->CCMR3 |= sConfig->OCFastMode;
- break;
- }
-
- case TIM_CHANNEL_6:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
-
- /* Configure the Channel 6 in PWM mode */
- TIM_OC6_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel6 */
- htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
- htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- __HAL_UNLOCK(htim);
-
- return status;
-}
-
-/**
- * @brief Initializes the TIM One Pulse Channels according to the specified
- * parameters in the TIM_OnePulse_InitTypeDef.
- * @param htim TIM One Pulse handle
- * @param sConfig TIM One Pulse configuration structure
- * @param OutputChannel TIM output channel to configure
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @param InputChannel TIM input Channel to configure
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @note To output a waveform with a minimum delay user can enable the fast
- * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
- * output is forced in response to the edge detection on TIx input,
- * without taking in account the comparison.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
- uint32_t OutputChannel, uint32_t InputChannel)
-{
- HAL_StatusTypeDef status = HAL_OK;
- TIM_OC_InitTypeDef temp1;
-
- /* Check the parameters */
- assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
- assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
-
- if (OutputChannel != InputChannel)
- {
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Extract the Output compare configuration from sConfig structure */
- temp1.OCMode = sConfig->OCMode;
- temp1.Pulse = sConfig->Pulse;
- temp1.OCPolarity = sConfig->OCPolarity;
- temp1.OCNPolarity = sConfig->OCNPolarity;
- temp1.OCIdleState = sConfig->OCIdleState;
- temp1.OCNIdleState = sConfig->OCNIdleState;
-
- switch (OutputChannel)
- {
- case TIM_CHANNEL_1:
- {
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- TIM_OC1_SetConfig(htim->Instance, &temp1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_OC2_SetConfig(htim->Instance, &temp1);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- switch (InputChannel)
- {
- case TIM_CHANNEL_1:
- {
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
-
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
- /* Select the Trigger source */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI1FP1;
-
- /* Select the Slave Mode */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
-
- /* Reset the IC2PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
- /* Select the Trigger source */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI2FP2;
-
- /* Select the Slave Mode */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return status;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
- * @param htim TIM handle
- * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
- * This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_OR1
- * @arg TIM_DMABASE_CCMR3
- * @arg TIM_DMABASE_CCR5
- * @arg TIM_DMABASE_CCR6
- * @arg TIM_DMABASE_OR2
- * @arg TIM_DMABASE_OR3
- * @param BurstRequestSrc TIM DMA Request sources
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer The Buffer address.
- * @param BurstLength DMA Burst length. This parameter can be one value
- * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
- * @note This function should be used only when BurstLength is equal to DMA data transfer length.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
-{
- HAL_StatusTypeDef status;
-
- status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
- ((BurstLength) >> 8U) + 1U);
-
-
-
- return status;
-}
-
-/**
- * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
- * @param htim TIM handle
- * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
- * This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_OR1
- * @arg TIM_DMABASE_CCMR3
- * @arg TIM_DMABASE_CCR5
- * @arg TIM_DMABASE_CCR6
- * @arg TIM_DMABASE_OR2
- * @arg TIM_DMABASE_OR3
- * @param BurstRequestSrc TIM DMA Request sources
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer The Buffer address.
- * @param BurstLength DMA Burst length. This parameter can be one value
- * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
- * @param DataLength Data length. This parameter can be one value
- * between 1 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
- uint32_t BurstLength, uint32_t DataLength)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
- assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
- assert_param(IS_TIM_DMA_LENGTH(BurstLength));
- assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
-
- if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
- {
- if ((BurstBuffer == NULL) && (BurstLength > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
- }
- }
- else
- {
- /* nothing to do */
- }
-
- switch (BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- /* Set the DMA Period elapsed callbacks */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
- htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC1:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC2:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC3:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC4:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
- htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_COM:
- {
- /* Set the DMA commutation callbacks */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_TRIGGER:
- {
- /* Set the DMA trigger callbacks */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Configure the DMA Burst Mode */
- htim->Instance->DCR = (BurstBaseAddress | BurstLength);
- /* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the TIM DMA Burst mode
- * @param htim TIM handle
- * @param BurstRequestSrc TIM DMA Request sources to disable
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
- /* Abort the DMA transfer (at least disable the DMA channel) */
- switch (BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
- break;
- }
- case TIM_DMA_CC1:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
- case TIM_DMA_CC2:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
- case TIM_DMA_CC3:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
- case TIM_DMA_CC4:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
- break;
- }
- case TIM_DMA_COM:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
- break;
- }
- case TIM_DMA_TRIGGER:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
- break;
- }
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
- * @param htim TIM handle
- * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
- * This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_OR1
- * @arg TIM_DMABASE_CCMR3
- * @arg TIM_DMABASE_CCR5
- * @arg TIM_DMABASE_CCR6
- * @arg TIM_DMABASE_OR2
- * @arg TIM_DMABASE_OR3
- * @param BurstRequestSrc TIM DMA Request sources
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer The Buffer address.
- * @param BurstLength DMA Burst length. This parameter can be one value
- * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
- * @note This function should be used only when BurstLength is equal to DMA data transfer length.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
-{
- HAL_StatusTypeDef status;
-
- status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
- ((BurstLength) >> 8U) + 1U);
-
-
- return status;
-}
-
-/**
- * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
- * @param htim TIM handle
- * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
- * This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_OR1
- * @arg TIM_DMABASE_CCMR3
- * @arg TIM_DMABASE_CCR5
- * @arg TIM_DMABASE_CCR6
- * @arg TIM_DMABASE_OR2
- * @arg TIM_DMABASE_OR3
- * @param BurstRequestSrc TIM DMA Request sources
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer The Buffer address.
- * @param BurstLength DMA Burst length. This parameter can be one value
- * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
- * @param DataLength Data length. This parameter can be one value
- * between 1 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
- uint32_t BurstLength, uint32_t DataLength)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
- assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
- assert_param(IS_TIM_DMA_LENGTH(BurstLength));
- assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
-
- if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
- {
- if ((BurstBuffer == NULL) && (BurstLength > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
- }
- }
- else
- {
- /* nothing to do */
- }
- switch (BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- /* Set the DMA Period elapsed callbacks */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
- htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC1:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC2:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC3:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_CC4:
- {
- /* Set the DMA capture callbacks */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_COM:
- {
- /* Set the DMA commutation callbacks */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- case TIM_DMA_TRIGGER:
- {
- /* Set the DMA trigger callbacks */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- break;
- }
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Configure the DMA Burst Mode */
- htim->Instance->DCR = (BurstBaseAddress | BurstLength);
-
- /* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stop the DMA burst reading
- * @param htim TIM handle
- * @param BurstRequestSrc TIM DMA Request sources to disable.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
- /* Abort the DMA transfer (at least disable the DMA channel) */
- switch (BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
- break;
- }
- case TIM_DMA_CC1:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
- case TIM_DMA_CC2:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
- case TIM_DMA_CC3:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
- case TIM_DMA_CC4:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
- break;
- }
- case TIM_DMA_COM:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
- break;
- }
- case TIM_DMA_TRIGGER:
- {
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
- break;
- }
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Generate a software event
- * @param htim TIM handle
- * @param EventSource specifies the event source.
- * This parameter can be one of the following values:
- * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
- * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
- * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
- * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
- * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EVENTSOURCE_COM: Timer COM event source
- * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
- * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
- * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
- * @note Basic timers can only generate an update event.
- * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
- * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
- * only for timer instances supporting break input(s).
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_EVENT_SOURCE(EventSource));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- /* Change the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Set the event sources */
- htim->Instance->EGR = EventSource;
-
- /* Change the TIM state */
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Configures the OCRef clear feature
- * @param htim TIM handle
- * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
- * contains the OCREF clear feature and parameters for the TIM peripheral.
- * @param Channel specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @arg TIM_CHANNEL_4: TIM Channel 4
- * @arg TIM_CHANNEL_5: TIM Channel 5
- * @arg TIM_CHANNEL_6: TIM Channel 6
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
- TIM_ClearInputConfigTypeDef *sClearInputConfig,
- uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- switch (sClearInputConfig->ClearInputSource)
- {
- case TIM_CLEARINPUTSOURCE_NONE:
- {
- /* Clear the OCREF clear selection bit and the the ETR Bits */
- CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
- break;
- }
- case TIM_CLEARINPUTSOURCE_OCREFCLR:
- {
- /* Clear the OCREF clear selection bit */
- CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
- break;
- }
-
- case TIM_CLEARINPUTSOURCE_ETR:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
- assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
- assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-
- /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
- if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
- {
- htim->State = HAL_TIM_STATE_READY;
- __HAL_UNLOCK(htim);
- return HAL_ERROR;
- }
-
- TIM_ETR_SetConfig(htim->Instance,
- sClearInputConfig->ClearInputPrescaler,
- sClearInputConfig->ClearInputPolarity,
- sClearInputConfig->ClearInputFilter);
-
- /* Set the OCREF clear selection bit */
- SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 1 */
- SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 1 */
- CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
- }
- break;
- }
- case TIM_CHANNEL_2:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 2 */
- SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 2 */
- CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
- }
- break;
- }
- case TIM_CHANNEL_3:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 3 */
- SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 3 */
- CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
- }
- break;
- }
- case TIM_CHANNEL_4:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 4 */
- SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 4 */
- CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
- }
- break;
- }
- case TIM_CHANNEL_5:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 5 */
- SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 5 */
- CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
- }
- break;
- }
- case TIM_CHANNEL_6:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 6 */
- SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 6 */
- CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
- }
- break;
- }
- default:
- break;
- }
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return status;
-}
-
-/**
- * @brief Configures the clock source to be used
- * @param htim TIM handle
- * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
- * contains the clock source information for the TIM peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Check the parameters */
- assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-
- /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
- tmpsmcr = htim->Instance->SMCR;
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- htim->Instance->SMCR = tmpsmcr;
-
- switch (sClockSourceConfig->ClockSource)
- {
- case TIM_CLOCKSOURCE_INTERNAL:
- {
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- break;
- }
-
- case TIM_CLOCKSOURCE_ETRMODE1:
- {
- /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
-
- /* Check ETR input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETR_SetConfig(htim->Instance,
- sClockSourceConfig->ClockPrescaler,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
-
- /* Select the External clock mode1 and the ETRF trigger */
- tmpsmcr = htim->Instance->SMCR;
- tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
- break;
- }
-
- case TIM_CLOCKSOURCE_ETRMODE2:
- {
- /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
-
- /* Check ETR input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETR_SetConfig(htim->Instance,
- sClockSourceConfig->ClockPrescaler,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- /* Enable the External clock mode2 */
- htim->Instance->SMCR |= TIM_SMCR_ECE;
- break;
- }
-
- case TIM_CLOCKSOURCE_TI1:
- {
- /* Check whether or not the timer instance supports external clock mode 1 */
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- /* Check TI1 input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- TIM_TI1_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
- break;
- }
-
- case TIM_CLOCKSOURCE_TI2:
- {
- /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- /* Check TI2 input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- TIM_TI2_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
- break;
- }
-
- case TIM_CLOCKSOURCE_TI1ED:
- {
- /* Check whether or not the timer instance supports external clock mode 1 */
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- /* Check TI1 input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- TIM_TI1_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
- break;
- }
-
- case TIM_CLOCKSOURCE_ITR0:
- case TIM_CLOCKSOURCE_ITR1:
- case TIM_CLOCKSOURCE_ITR2:
- case TIM_CLOCKSOURCE_ITR3:
- {
- /* Check whether or not the timer instance supports internal trigger input */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return status;
-}
-
-/**
- * @brief Selects the signal connected to the TI1 input: direct from CH1_input
- * or a XOR combination between CH1_input, CH2_input & CH3_input
- * @param htim TIM handle.
- * @param TI1_Selection Indicate whether or not channel 1 is connected to the
- * output of a XOR gate.
- * This parameter can be one of the following values:
- * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
- * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
- * pins are connected to the TI1 input (XOR combination)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
-{
- uint32_t tmpcr2;
-
- /* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = htim->Instance->CR2;
-
- /* Reset the TI1 selection */
- tmpcr2 &= ~TIM_CR2_TI1S;
-
- /* Set the TI1 selection */
- tmpcr2 |= TI1_Selection;
-
- /* Write to TIMxCR2 */
- htim->Instance->CR2 = tmpcr2;
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the TIM in Slave mode
- * @param htim TIM handle.
- * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
- * contains the selected trigger (internal trigger input, filtered
- * timer input or external trigger input) and the Slave mode
- * (Disable, Reset, Gated, Trigger, External clock mode 1).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
-{
- /* Check the parameters */
- assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
- assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
- {
- htim->State = HAL_TIM_STATE_READY;
- __HAL_UNLOCK(htim);
- return HAL_ERROR;
- }
-
- /* Disable Trigger Interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
-
- /* Disable Trigger DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the TIM in Slave mode in interrupt mode
- * @param htim TIM handle.
- * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
- * contains the selected trigger (internal trigger input, filtered
- * timer input or external trigger input) and the Slave mode
- * (Disable, Reset, Gated, Trigger, External clock mode 1).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef *sSlaveConfig)
-{
- /* Check the parameters */
- assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
- assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
- {
- htim->State = HAL_TIM_STATE_READY;
- __HAL_UNLOCK(htim);
- return HAL_ERROR;
- }
-
- /* Enable Trigger Interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
-
- /* Disable Trigger DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read the captured value from Capture Compare unit
- * @param htim TIM handle.
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval Captured value
- */
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpreg = 0U;
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Return the capture 1 value */
- tmpreg = htim->Instance->CCR1;
-
- break;
- }
- case TIM_CHANNEL_2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Return the capture 2 value */
- tmpreg = htim->Instance->CCR2;
-
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Return the capture 3 value */
- tmpreg = htim->Instance->CCR3;
-
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Return the capture 4 value */
- tmpreg = htim->Instance->CCR4;
-
- break;
- }
-
- default:
- break;
- }
-
- return tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- * @brief TIM Callbacks functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Callbacks functions #####
- ==============================================================================
- [..]
- This section provides TIM callback functions:
- (+) TIM Period elapsed callback
- (+) TIM Output Compare callback
- (+) TIM Input capture callback
- (+) TIM Trigger callback
- (+) TIM Error callback
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Period elapsed callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Period elapsed half complete callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Output Compare callback in non-blocking mode
- * @param htim TIM OC handle
- * @retval None
- */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Input Capture callback in non-blocking mode
- * @param htim TIM IC handle
- * @retval None
- */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_IC_CaptureCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Input Capture half complete callback in non-blocking mode
- * @param htim TIM IC handle
- * @retval None
- */
-__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief PWM Pulse finished callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief PWM Pulse finished half complete callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Hall Trigger detection callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_TriggerCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Hall Trigger detection half complete callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Timer error callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_ErrorCallback could be implemented in the user file
- */
-}
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-/**
- * @brief Register a User TIM callback to be used instead of the weak predefined callback
- * @param htim tim handle
- * @param CallbackID ID of the callback to be registered
- * This parameter can be one of the following values:
- * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
- * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
- * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
- * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
- * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
- * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
- * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
- * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
- * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
- * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
- * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
- * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
- * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
- * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
- * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
- * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
- * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
- * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
- * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
- * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
- * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
- * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
- * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
- * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
- * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
- * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
- * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
- * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
- * @param pCallback pointer to the callback function
- * @retval status
- */
-HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
- pTIM_CallbackTypeDef pCallback)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if (pCallback == NULL)
- {
- return HAL_ERROR;
- }
- /* Process locked */
- __HAL_LOCK(htim);
-
- if (htim->State == HAL_TIM_STATE_READY)
- {
- switch (CallbackID)
- {
- case HAL_TIM_BASE_MSPINIT_CB_ID :
- htim->Base_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_BASE_MSPDEINIT_CB_ID :
- htim->Base_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_IC_MSPINIT_CB_ID :
- htim->IC_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_IC_MSPDEINIT_CB_ID :
- htim->IC_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_OC_MSPINIT_CB_ID :
- htim->OC_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_OC_MSPDEINIT_CB_ID :
- htim->OC_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_PWM_MSPINIT_CB_ID :
- htim->PWM_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_PWM_MSPDEINIT_CB_ID :
- htim->PWM_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
- htim->OnePulse_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
- htim->OnePulse_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_ENCODER_MSPINIT_CB_ID :
- htim->Encoder_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
- htim->Encoder_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
- htim->HallSensor_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
- htim->HallSensor_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_PERIOD_ELAPSED_CB_ID :
- htim->PeriodElapsedCallback = pCallback;
- break;
-
- case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
- htim->PeriodElapsedHalfCpltCallback = pCallback;
- break;
-
- case HAL_TIM_TRIGGER_CB_ID :
- htim->TriggerCallback = pCallback;
- break;
-
- case HAL_TIM_TRIGGER_HALF_CB_ID :
- htim->TriggerHalfCpltCallback = pCallback;
- break;
-
- case HAL_TIM_IC_CAPTURE_CB_ID :
- htim->IC_CaptureCallback = pCallback;
- break;
-
- case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
- htim->IC_CaptureHalfCpltCallback = pCallback;
- break;
-
- case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
- htim->OC_DelayElapsedCallback = pCallback;
- break;
-
- case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
- htim->PWM_PulseFinishedCallback = pCallback;
- break;
-
- case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
- htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
- break;
-
- case HAL_TIM_ERROR_CB_ID :
- htim->ErrorCallback = pCallback;
- break;
-
- case HAL_TIM_COMMUTATION_CB_ID :
- htim->CommutationCallback = pCallback;
- break;
-
- case HAL_TIM_COMMUTATION_HALF_CB_ID :
- htim->CommutationHalfCpltCallback = pCallback;
- break;
-
- case HAL_TIM_BREAK_CB_ID :
- htim->BreakCallback = pCallback;
- break;
-
- case HAL_TIM_BREAK2_CB_ID :
- htim->Break2Callback = pCallback;
- break;
-
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else if (htim->State == HAL_TIM_STATE_RESET)
- {
- switch (CallbackID)
- {
- case HAL_TIM_BASE_MSPINIT_CB_ID :
- htim->Base_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_BASE_MSPDEINIT_CB_ID :
- htim->Base_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_IC_MSPINIT_CB_ID :
- htim->IC_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_IC_MSPDEINIT_CB_ID :
- htim->IC_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_OC_MSPINIT_CB_ID :
- htim->OC_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_OC_MSPDEINIT_CB_ID :
- htim->OC_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_PWM_MSPINIT_CB_ID :
- htim->PWM_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_PWM_MSPDEINIT_CB_ID :
- htim->PWM_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
- htim->OnePulse_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
- htim->OnePulse_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_ENCODER_MSPINIT_CB_ID :
- htim->Encoder_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
- htim->Encoder_MspDeInitCallback = pCallback;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
- htim->HallSensor_MspInitCallback = pCallback;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
- htim->HallSensor_MspDeInitCallback = pCallback;
- break;
-
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return status;
-}
-
-/**
- * @brief Unregister a TIM callback
- * TIM callback is redirected to the weak predefined callback
- * @param htim tim handle
- * @param CallbackID ID of the callback to be unregistered
- * This parameter can be one of the following values:
- * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
- * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
- * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
- * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
- * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
- * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
- * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
- * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
- * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
- * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
- * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
- * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
- * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
- * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
- * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
- * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
- * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
- * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
- * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
- * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
- * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
- * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
- * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
- * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
- * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
- * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
- * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
- * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
- * @retval status
- */
-HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(htim);
-
- if (htim->State == HAL_TIM_STATE_READY)
- {
- switch (CallbackID)
- {
- case HAL_TIM_BASE_MSPINIT_CB_ID :
- /* Legacy weak Base MspInit Callback */
- htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
- break;
-
- case HAL_TIM_BASE_MSPDEINIT_CB_ID :
- /* Legacy weak Base Msp DeInit Callback */
- htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
- break;
-
- case HAL_TIM_IC_MSPINIT_CB_ID :
- /* Legacy weak IC Msp Init Callback */
- htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
- break;
-
- case HAL_TIM_IC_MSPDEINIT_CB_ID :
- /* Legacy weak IC Msp DeInit Callback */
- htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
- break;
-
- case HAL_TIM_OC_MSPINIT_CB_ID :
- /* Legacy weak OC Msp Init Callback */
- htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
- break;
-
- case HAL_TIM_OC_MSPDEINIT_CB_ID :
- /* Legacy weak OC Msp DeInit Callback */
- htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
- break;
-
- case HAL_TIM_PWM_MSPINIT_CB_ID :
- /* Legacy weak PWM Msp Init Callback */
- htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
- break;
-
- case HAL_TIM_PWM_MSPDEINIT_CB_ID :
- /* Legacy weak PWM Msp DeInit Callback */
- htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
- /* Legacy weak One Pulse Msp Init Callback */
- htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
- /* Legacy weak One Pulse Msp DeInit Callback */
- htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
- break;
-
- case HAL_TIM_ENCODER_MSPINIT_CB_ID :
- /* Legacy weak Encoder Msp Init Callback */
- htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
- break;
-
- case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
- /* Legacy weak Encoder Msp DeInit Callback */
- htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
- /* Legacy weak Hall Sensor Msp Init Callback */
- htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
- /* Legacy weak Hall Sensor Msp DeInit Callback */
- htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
- break;
-
- case HAL_TIM_PERIOD_ELAPSED_CB_ID :
- /* Legacy weak Period Elapsed Callback */
- htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
- break;
-
- case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
- /* Legacy weak Period Elapsed half complete Callback */
- htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
- break;
-
- case HAL_TIM_TRIGGER_CB_ID :
- /* Legacy weak Trigger Callback */
- htim->TriggerCallback = HAL_TIM_TriggerCallback;
- break;
-
- case HAL_TIM_TRIGGER_HALF_CB_ID :
- /* Legacy weak Trigger half complete Callback */
- htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
- break;
-
- case HAL_TIM_IC_CAPTURE_CB_ID :
- /* Legacy weak IC Capture Callback */
- htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
- break;
-
- case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
- /* Legacy weak IC Capture half complete Callback */
- htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
- break;
-
- case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
- /* Legacy weak OC Delay Elapsed Callback */
- htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
- break;
-
- case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
- /* Legacy weak PWM Pulse Finished Callback */
- htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
- break;
-
- case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
- /* Legacy weak PWM Pulse Finished half complete Callback */
- htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
- break;
-
- case HAL_TIM_ERROR_CB_ID :
- /* Legacy weak Error Callback */
- htim->ErrorCallback = HAL_TIM_ErrorCallback;
- break;
-
- case HAL_TIM_COMMUTATION_CB_ID :
- /* Legacy weak Commutation Callback */
- htim->CommutationCallback = HAL_TIMEx_CommutCallback;
- break;
-
- case HAL_TIM_COMMUTATION_HALF_CB_ID :
- /* Legacy weak Commutation half complete Callback */
- htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
- break;
-
- case HAL_TIM_BREAK_CB_ID :
- /* Legacy weak Break Callback */
- htim->BreakCallback = HAL_TIMEx_BreakCallback;
- break;
-
- case HAL_TIM_BREAK2_CB_ID :
- /* Legacy weak Break2 Callback */
- htim->Break2Callback = HAL_TIMEx_Break2Callback;
- break;
-
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else if (htim->State == HAL_TIM_STATE_RESET)
- {
- switch (CallbackID)
- {
- case HAL_TIM_BASE_MSPINIT_CB_ID :
- /* Legacy weak Base MspInit Callback */
- htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
- break;
-
- case HAL_TIM_BASE_MSPDEINIT_CB_ID :
- /* Legacy weak Base Msp DeInit Callback */
- htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
- break;
-
- case HAL_TIM_IC_MSPINIT_CB_ID :
- /* Legacy weak IC Msp Init Callback */
- htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
- break;
-
- case HAL_TIM_IC_MSPDEINIT_CB_ID :
- /* Legacy weak IC Msp DeInit Callback */
- htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
- break;
-
- case HAL_TIM_OC_MSPINIT_CB_ID :
- /* Legacy weak OC Msp Init Callback */
- htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
- break;
-
- case HAL_TIM_OC_MSPDEINIT_CB_ID :
- /* Legacy weak OC Msp DeInit Callback */
- htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
- break;
-
- case HAL_TIM_PWM_MSPINIT_CB_ID :
- /* Legacy weak PWM Msp Init Callback */
- htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
- break;
-
- case HAL_TIM_PWM_MSPDEINIT_CB_ID :
- /* Legacy weak PWM Msp DeInit Callback */
- htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
- /* Legacy weak One Pulse Msp Init Callback */
- htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
- break;
-
- case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
- /* Legacy weak One Pulse Msp DeInit Callback */
- htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
- break;
-
- case HAL_TIM_ENCODER_MSPINIT_CB_ID :
- /* Legacy weak Encoder Msp Init Callback */
- htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
- break;
-
- case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
- /* Legacy weak Encoder Msp DeInit Callback */
- htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
- /* Legacy weak Hall Sensor Msp Init Callback */
- htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
- break;
-
- case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
- /* Legacy weak Hall Sensor Msp DeInit Callback */
- htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
- break;
-
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return status;
-}
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
- * @brief TIM Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the TIM Base handle state.
- * @param htim TIM Base handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM OC handle state.
- * @param htim TIM Output Compare handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM PWM handle state.
- * @param htim TIM handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM Input Capture handle state.
- * @param htim TIM IC handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM One Pulse Mode handle state.
- * @param htim TIM OPM handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM Encoder Mode handle state.
- * @param htim TIM Encoder Interface handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM Encoder Mode handle state.
- * @param htim TIM handle
- * @retval Active channel
- */
-HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
-{
- return htim->Channel;
-}
-
-/**
- * @brief Return actual state of the TIM channel.
- * @param htim TIM handle
- * @param Channel TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @arg TIM_CHANNEL_4: TIM Channel 4
- * @arg TIM_CHANNEL_5: TIM Channel 5
- * @arg TIM_CHANNEL_6: TIM Channel 6
- * @retval TIM Channel state
- */
-HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_TIM_ChannelStateTypeDef channel_state;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
-
- return channel_state;
-}
-
-/**
- * @brief Return actual state of a DMA burst operation.
- * @param htim TIM handle
- * @retval DMA burst state
- */
-HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-
- return htim->DMABurstState;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Private_Functions TIM Private Functions
- * @{
- */
-
-/**
- * @brief TIM DMA error callback
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIM_DMAError(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- }
- else
- {
- htim->State = HAL_TIM_STATE_READY;
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->ErrorCallback(htim);
-#else
- HAL_TIM_ErrorCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA Delay Pulse complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else
- {
- /* nothing to do */
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA Delay Pulse half complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- }
- else
- {
- /* nothing to do */
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PWM_PulseFinishedHalfCpltCallback(htim);
-#else
- HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA Capture complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else
- {
- /* nothing to do */
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA Capture half complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- }
- else
- {
- /* nothing to do */
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureHalfCpltCallback(htim);
-#else
- HAL_TIM_IC_CaptureHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA Period Elapse complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
- {
- htim->State = HAL_TIM_STATE_READY;
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PeriodElapsedCallback(htim);
-#else
- HAL_TIM_PeriodElapsedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief TIM DMA Period Elapse half complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PeriodElapsedHalfCpltCallback(htim);
-#else
- HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief TIM DMA Trigger callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
- {
- htim->State = HAL_TIM_STATE_READY;
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->TriggerCallback(htim);
-#else
- HAL_TIM_TriggerCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief TIM DMA Trigger half complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->TriggerHalfCpltCallback(htim);
-#else
- HAL_TIM_TriggerHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief Time Base configuration
- * @param TIMx TIM peripheral
- * @param Structure TIM Base configuration structure
- * @retval None
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
-{
- uint32_t tmpcr1;
- tmpcr1 = TIMx->CR1;
-
- /* Set TIM Time Base Unit parameters ---------------------------------------*/
- if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
- {
- /* Select the Counter Mode */
- tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
- tmpcr1 |= Structure->CounterMode;
- }
-
- if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
- {
- /* Set the clock division */
- tmpcr1 &= ~TIM_CR1_CKD;
- tmpcr1 |= (uint32_t)Structure->ClockDivision;
- }
-
- /* Set the auto-reload preload */
- MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
-
- TIMx->CR1 = tmpcr1;
-
- /* Set the Autoreload value */
- TIMx->ARR = (uint32_t)Structure->Period ;
-
- /* Set the Prescaler value */
- TIMx->PSC = Structure->Prescaler;
-
- if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = Structure->RepetitionCounter;
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter (only for advanced timer) value immediately */
- TIMx->EGR = TIM_EGR_UG;
-}
-
-/**
- * @brief Timer Output Compare 1 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
- * @retval None
- */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~TIM_CCMR1_OC1M;
- tmpccmrx &= ~TIM_CCMR1_CC1S;
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC1P;
- /* Set the Output Compare Polarity */
- tmpccer |= OC_Config->OCPolarity;
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC1NP;
- /* Set the Output N Polarity */
- tmpccer |= OC_Config->OCNPolarity;
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC1NE;
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS1;
- tmpcr2 &= ~TIM_CR2_OIS1N;
- /* Set the Output Idle state */
- tmpcr2 |= OC_Config->OCIdleState;
- /* Set the Output N Idle state */
- tmpcr2 |= OC_Config->OCNIdleState;
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Timer Output Compare 2 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
- * @retval None
- */
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR1_OC2M;
- tmpccmrx &= ~TIM_CCMR1_CC2S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC2P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 4U);
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC2NP;
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 4U);
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC2NE;
-
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS2;
- tmpcr2 &= ~TIM_CR2_OIS2N;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 2U);
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 2U);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Timer Output Compare 3 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
- * @retval None
- */
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 3: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC3E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC3M;
- tmpccmrx &= ~TIM_CCMR2_CC3S;
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC3P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 8U);
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC3NP;
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 8U);
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC3NE;
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS3;
- tmpcr2 &= ~TIM_CR2_OIS3N;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 4U);
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 4U);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Timer Output Compare 4 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
- * @retval None
- */
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= ~TIM_CCER_CC4E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC4M;
- tmpccmrx &= ~TIM_CCMR2_CC4S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC4P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 12U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS4;
-
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 6U);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Timer Output Compare 5 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
- * @retval None
- */
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the output: Reset the CCxE Bit */
- TIMx->CCER &= ~TIM_CCER_CC5E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR3;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~(TIM_CCMR3_OC5M);
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC5P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 16U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS5;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 8U);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR3 */
- TIMx->CCMR3 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR5 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Timer Output Compare 6 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
- * @retval None
- */
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the output: Reset the CCxE Bit */
- TIMx->CCER &= ~TIM_CCER_CC6E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR3;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~(TIM_CCMR3_OC6M);
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint32_t)~TIM_CCER_CC6P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 20U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS6;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 10U);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR3 */
- TIMx->CCMR3 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR6 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Slave Timer configuration function
- * @param htim TIM handle
- * @param sSlaveConfig Slave timer configuration
- * @retval None
- */
-static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef *sSlaveConfig)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* Reset the Trigger Selection Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- /* Set the Input Trigger source */
- tmpsmcr |= sSlaveConfig->InputTrigger;
-
- /* Reset the slave mode Bits */
- tmpsmcr &= ~TIM_SMCR_SMS;
- /* Set the slave mode */
- tmpsmcr |= sSlaveConfig->SlaveMode;
-
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
-
- /* Configure the trigger prescaler, filter, and polarity */
- switch (sSlaveConfig->InputTrigger)
- {
- case TIM_TS_ETRF:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
- /* Configure the ETR Trigger source */
- TIM_ETR_SetConfig(htim->Instance,
- sSlaveConfig->TriggerPrescaler,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- break;
- }
-
- case TIM_TS_TI1F_ED:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
- {
- return HAL_ERROR;
- }
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- tmpccer = htim->Instance->CCER;
- htim->Instance->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = htim->Instance->CCMR1;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
-
- /* Write to TIMx CCMR1 and CCER registers */
- htim->Instance->CCMR1 = tmpccmr1;
- htim->Instance->CCER = tmpccer;
- break;
- }
-
- case TIM_TS_TI1FP1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Configure TI1 Filter and Polarity */
- TIM_TI1_ConfigInputStage(htim->Instance,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- break;
- }
-
- case TIM_TS_TI2FP2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Configure TI2 Filter and Polarity */
- TIM_TI2_ConfigInputStage(htim->Instance,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- break;
- }
-
- case TIM_TS_ITR0:
- case TIM_TS_ITR1:
- case TIM_TS_ITR2:
- case TIM_TS_ITR3:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- return status;
-}
-
-/**
- * @brief Configure the TI1 as Input.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICSelection specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
- * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
- * protected against un-initialized filter and polarity values.
- */
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
- {
- tmpccmr1 &= ~TIM_CCMR1_CC1S;
- tmpccmr1 |= TIM_ICSelection;
- }
- else
- {
- tmpccmr1 |= TIM_CCMR1_CC1S_0;
- }
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the Polarity and Filter for TI1.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- tmpccer = TIMx->CCER;
- TIMx->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= (TIM_ICFilter << 4U);
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= TIM_ICPolarity;
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI2 as Input.
- * @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICSelection specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
- * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
- * protected against un-initialized filter and polarity values.
- */
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- tmpccmr1 &= ~TIM_CCMR1_CC2S;
- tmpccmr1 |= (TIM_ICSelection << 8U);
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the Polarity and Filter for TI2.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= (TIM_ICFilter << 12U);
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (TIM_ICPolarity << 4U);
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI3 as Input.
- * @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICSelection specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
- * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
- * protected against un-initialized filter and polarity values.
- */
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr2;
- uint32_t tmpccer;
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= ~TIM_CCER_CC3E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- tmpccmr2 &= ~TIM_CCMR2_CC3S;
- tmpccmr2 |= TIM_ICSelection;
-
- /* Set the filter */
- tmpccmr2 &= ~TIM_CCMR2_IC3F;
- tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
-
- /* Select the Polarity and set the CC3E Bit */
- tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
- tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI4 as Input.
- * @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICSelection specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
- * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
- * protected against un-initialized filter and polarity values.
- * @retval None
- */
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr2;
- uint32_t tmpccer;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= ~TIM_CCER_CC4E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- tmpccmr2 &= ~TIM_CCMR2_CC4S;
- tmpccmr2 |= (TIM_ICSelection << 8U);
-
- /* Set the filter */
- tmpccmr2 &= ~TIM_CCMR2_IC4F;
- tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
-
- /* Select the Polarity and set the CC4E Bit */
- tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
- tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer ;
-}
-
-/**
- * @brief Selects the Input Trigger source
- * @param TIMx to select the TIM peripheral
- * @param InputTriggerSource The Input Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @retval None
- */
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
-{
- uint32_t tmpsmcr;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Reset the TS Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- /* Set the Input Trigger source and the slave mode*/
- tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-/**
- * @brief Configures the TIMx External Trigger (ETR).
- * @param TIMx to select the TIM peripheral
- * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
- * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
- * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
- * @param ExtTRGFilter External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
-{
- uint32_t tmpsmcr;
-
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the ETR Bits */
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx to select the TIM peripheral
- * @param Channel specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @arg TIM_CHANNEL_4: TIM Channel 4
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @param ChannelState specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
- * @retval None
- */
-void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
-{
- uint32_t tmp;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_TIM_CHANNELS(Channel));
-
- tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= ~tmp;
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
-}
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-/**
- * @brief Reset interrupt callbacks to the legacy weak callbacks.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-void TIM_ResetCallback(TIM_HandleTypeDef *htim)
-{
- /* Reset the TIM callback to the legacy weak callbacks */
- htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
- htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
- htim->TriggerCallback = HAL_TIM_TriggerCallback;
- htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
- htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
- htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
- htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
- htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
- htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
- htim->ErrorCallback = HAL_TIM_ErrorCallback;
- htim->CommutationCallback = HAL_TIMEx_CommutCallback;
- htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
- htim->BreakCallback = HAL_TIMEx_BreakCallback;
- htim->Break2Callback = HAL_TIMEx_Break2Callback;
-}
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c
deleted file mode 100644
index 6f231f7..0000000
--- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c
+++ /dev/null
@@ -1,2838 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32l4xx_hal_tim_ex.c
- * @author MCD Application Team
- * @brief TIM HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Timer Extended peripheral:
- * + Time Hall Sensor Interface Initialization
- * + Time Hall Sensor Interface Start
- * + Time Complementary signal break and dead time configuration
- * + Time Master and Slave synchronization configuration
- * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
- * + Time OCRef clear configuration
- * + Timer remapping capabilities configuration
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
- ==============================================================================
- ##### TIMER Extended features #####
- ==============================================================================
- [..]
- The Timer Extended features include:
- (#) Complementary outputs with programmable dead-time for :
- (++) Output Compare
- (++) PWM generation (Edge and Center-aligned Mode)
- (++) One-pulse mode output
- (#) Synchronization circuit to control the timer with external signals and to
- interconnect several timers together.
- (#) Break input to put the timer output signals in reset state or in a known state.
- (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
- positioning purposes
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Initialize the TIM low level resources by implementing the following functions
- depending on the selected feature:
- (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
-
- (#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
- (##) TIM pins configuration
- (+++) Enable the clock for the TIM GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE();
- (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
-
- (#) The external Clock can be configured, if needed (the default clock is the
- internal clock from the APBx), using the following function:
- HAL_TIM_ConfigClockSource, the clock configuration should be done before
- any start function.
-
- (#) Configure the TIM in the desired functioning mode using one of the
- initialization function of this driver:
- (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
- Timer Hall Sensor Interface and the commutation event with the corresponding
- Interrupt and DMA request if needed (Note that One Timer is used to interface
- with the Hall sensor Interface and another Timer should be used to use
- the commutation event).
-
- (#) Activate the TIM peripheral using one of the start functions:
- (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
- HAL_TIMEx_OCN_Start_IT()
- (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
- HAL_TIMEx_PWMN_Start_IT()
- (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
- (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
- HAL_TIMEx_HallSensor_Start_IT().
-
- @endverbatim
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
-
-/** @addtogroup STM32L4xx_HAL_Driver
- * @{
- */
-
-/** @defgroup TIMEx TIMEx
- * @brief TIM Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
-static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
- * @{
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
- * @brief Timer Hall Sensor functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Hall Sensor functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure TIM HAL Sensor.
- (+) De-initialize TIM HAL Sensor.
- (+) Start the Hall Sensor Interface.
- (+) Stop the Hall Sensor Interface.
- (+) Start the Hall Sensor Interface and enable interrupts.
- (+) Stop the Hall Sensor Interface and disable interrupts.
- (+) Start the Hall Sensor Interface and enable DMA transfers.
- (+) Stop the Hall Sensor Interface and disable DMA transfers.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
- * @note When the timer instance is initialized in Hall Sensor Interface mode,
- * timer channels 1 and channel 2 are reserved and cannot be used for
- * other purpose.
- * @param htim TIM Hall Sensor Interface handle
- * @param sConfig TIM Hall Sensor configuration structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
-{
- TIM_OC_InitTypeDef OC_Config;
-
- /* Check the TIM handle allocation */
- if (htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy week callbacks */
- TIM_ResetCallback(htim);
-
- if (htim->HallSensor_MspInitCallback == NULL)
- {
- htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->HallSensor_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIMEx_HallSensor_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Configure the Time base in the Encoder Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
- TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
-
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
- /* Set the IC1PSC value */
- htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
-
- /* Enable the Hall sensor interface (XOR function of the three inputs) */
- htim->Instance->CR2 |= TIM_CR2_TI1S;
-
- /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI1F_ED;
-
- /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
-
- /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
- OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
- OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
- OC_Config.OCMode = TIM_OCMODE_PWM2;
- OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
- OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
- OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
- OC_Config.Pulse = sConfig->Commutation_Delay;
-
- TIM_OC2_SetConfig(htim->Instance, &OC_Config);
-
- /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
- register to 101 */
- htim->Instance->CR2 &= ~TIM_CR2_MMS;
- htim->Instance->CR2 |= TIM_TRGO_OC2REF;
-
- /* Initialize the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
- /* Initialize the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM Hall Sensor interface
- * @param htim TIM Hall Sensor Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if (htim->HallSensor_MspDeInitCallback == NULL)
- {
- htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
- }
- /* DeInit the low level hardware */
- htim->HallSensor_MspDeInitCallback(htim);
-#else
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIMEx_HallSensor_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
- /* Change the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Hall Sensor MSP.
- * @param htim TIM Hall Sensor Interface handle
- * @retval None
- */
-__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Hall Sensor MSP.
- * @param htim TIM Hall Sensor Interface handle
- * @retval None
- */
-__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Hall Sensor Interface.
- * @param htim TIM Hall Sensor Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
-{
- uint32_t tmpsmcr;
- HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
-
- /* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
- TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Hall sensor Interface.
- * @param htim TIM Hall Sensor Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1, 2 and 3
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
- TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
- * @param htim TIM Hall Sensor Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
-{
- uint32_t tmpsmcr;
- HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
-
- /* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the capture compare Interrupts 1 event */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
- /* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
- TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
- * @param htim TIM Hall Sensor Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
- TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts event */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Hall Sensor Interface in DMA mode.
- * @param htim TIM Hall Sensor Interface handle
- * @param pData The destination Buffer address.
- * @param Length The length of data to be transferred from TIM peripheral to memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
- uint32_t tmpsmcr;
- HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
-
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
-
- /* Set the TIM channel state */
- if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
- {
- if ((pData == NULL) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- return HAL_ERROR;
- }
-
- /* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
- TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Set the DMA Input Capture 1 Callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel for Capture 1*/
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the capture compare 1 Interrupt */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Hall Sensor Interface in DMA mode.
- * @param htim TIM Hall Sensor Interface handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
- TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-
- /* Disable the capture compare Interrupts 1 event */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
- * @brief Timer Complementary Output Compare functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Complementary Output Compare functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Start the Complementary Output Compare/PWM.
- (+) Stop the Complementary Output Compare/PWM.
- (+) Start the Complementary Output Compare/PWM and enable interrupts.
- (+) Stop the Complementary Output Compare/PWM and disable interrupts.
- (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
- (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the TIM Output Compare signal generation on the complementary
- * output.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM complementary channel state */
- if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation on the complementary
- * output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in interrupt mode
- * on the complementary output.
- * @param htim TIM OC handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM complementary channel state */
- if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Enable the TIM Break interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in interrupt mode
- * on the complementary output.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpccer;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the TIM Break interrupt (only if no more channel is active) */
- tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
- {
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
- }
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in DMA mode
- * on the complementary output.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Set the TIM complementary channel state */
- if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
- {
- if ((pData == NULL) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- return HAL_ERROR;
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in DMA mode
- * on the complementary output.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Output Compare DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Output Compare DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Output Compare DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
- * @brief Timer Complementary PWM functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Complementary PWM functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Start the Complementary PWM.
- (+) Stop the Complementary PWM.
- (+) Start the Complementary PWM and enable interrupts.
- (+) Stop the Complementary PWM and disable interrupts.
- (+) Start the Complementary PWM and enable DMA transfers.
- (+) Stop the Complementary PWM and disable DMA transfers.
- (+) Start the Complementary Input Capture measurement.
- (+) Stop the Complementary Input Capture.
- (+) Start the Complementary Input Capture and enable interrupts.
- (+) Stop the Complementary Input Capture and disable interrupts.
- (+) Start the Complementary Input Capture and enable DMA transfers.
- (+) Stop the Complementary Input Capture and disable DMA transfers.
- (+) Start the Complementary One Pulse generation.
- (+) Stop the Complementary One Pulse.
- (+) Start the Complementary One Pulse and enable interrupts.
- (+) Stop the Complementary One Pulse and disable interrupts.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the PWM signal generation on the complementary output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM complementary channel state */
- if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation on the complementary output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the PWM signal generation in interrupt mode on the
- * complementary output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Check the TIM complementary channel state */
- if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Enable the TIM Break interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the PWM signal generation in interrupt mode on the
- * complementary output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpccer;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the TIM Break interrupt (only if no more channel is active) */
- tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
- {
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
- }
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Starts the TIM PWM signal generation in DMA mode on the
- * complementary output
- * @param htim TIM handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Set the TIM complementary channel state */
- if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
- {
- if ((pData == NULL) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- }
- }
- else
- {
- return HAL_ERROR;
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
- htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
- Length) != HAL_OK)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- /* Enable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
- * output
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
- break;
- }
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
- break;
- }
-
- default:
- status = HAL_ERROR;
- break;
- }
-
- if (status == HAL_OK)
- {
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
- * @brief Timer Complementary One Pulse functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Complementary One Pulse functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Start the Complementary One Pulse generation.
- (+) Stop the Complementary One Pulse.
- (+) Start the Complementary One Pulse and enable interrupts.
- (+) Stop the Complementary One Pulse and disable interrupts.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the TIM One Pulse signal generation on the complementary
- * output.
- * @note OutputChannel must match the pulse output channel chosen when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
- * @param htim TIM One Pulse handle
- * @param OutputChannel pulse output channel to enable
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
- HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the complementary One Pulse output channel and the Input Capture channel */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation on the complementary
- * output.
- * @note OutputChannel must match the pulse output channel chosen when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
- * @param htim TIM One Pulse handle
- * @param OutputChannel pulse output channel to disable
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Disable the complementary One Pulse output channel and the Input Capture channel */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
- * complementary channel.
- * @note OutputChannel must match the pulse output channel chosen when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
- * @param htim TIM One Pulse handle
- * @param OutputChannel pulse output channel to enable
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
- HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- {
- return HAL_ERROR;
- }
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
- /* Enable the complementary One Pulse output channel and the Input Capture channel */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
- * complementary channel.
- * @note OutputChannel must match the pulse output channel chosen when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
- * @param htim TIM One Pulse handle
- * @param OutputChannel pulse output channel to disable
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
- /* Disable the complementary One Pulse output channel and the Input Capture channel */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
-
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channels state */
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Configure the commutation event in case of use of the Hall sensor interface.
- (+) Configure Output channels for OC and PWM mode.
-
- (+) Configure Complementary channels, break features and dead time.
- (+) Configure Master synchronization.
- (+) Configure timer remapping capabilities.
- (+) Enable or disable channel grouping.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure the TIM commutation event sequence.
- * @note This function is mandatory to use the commutation event in order to
- * update the configuration at each commutation detection on the TRGI input of the Timer,
- * the typical use of this feature is with the use of another Timer(interface Timer)
- * configured in Hall sensor interface, this interface Timer will generate the
- * commutation at its TRGO output (connected to Timer used in this function) each time
- * the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim TIM handle
- * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource the Commutation Event source
- * This parameter can be one of the following values:
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
- uint32_t CommutationSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
- assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
- __HAL_LOCK(htim);
-
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
- {
- /* Select the Input trigger */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= InputTrigger;
- }
-
- /* Select the Capture Compare preload feature */
- htim->Instance->CR2 |= TIM_CR2_CCPC;
- /* Select the Commutation event source */
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;
- htim->Instance->CR2 |= CommutationSource;
-
- /* Disable Commutation Interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
-
- /* Disable Commutation DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the TIM commutation event sequence with interrupt.
- * @note This function is mandatory to use the commutation event in order to
- * update the configuration at each commutation detection on the TRGI input of the Timer,
- * the typical use of this feature is with the use of another Timer(interface Timer)
- * configured in Hall sensor interface, this interface Timer will generate the
- * commutation at its TRGO output (connected to Timer used in this function) each time
- * the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim TIM handle
- * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource the Commutation Event source
- * This parameter can be one of the following values:
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
- uint32_t CommutationSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
- assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
- __HAL_LOCK(htim);
-
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
- {
- /* Select the Input trigger */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= InputTrigger;
- }
-
- /* Select the Capture Compare preload feature */
- htim->Instance->CR2 |= TIM_CR2_CCPC;
- /* Select the Commutation event source */
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;
- htim->Instance->CR2 |= CommutationSource;
-
- /* Disable Commutation DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
-
- /* Enable the Commutation Interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the TIM commutation event sequence with DMA.
- * @note This function is mandatory to use the commutation event in order to
- * update the configuration at each commutation detection on the TRGI input of the Timer,
- * the typical use of this feature is with the use of another Timer(interface Timer)
- * configured in Hall sensor interface, this interface Timer will generate the
- * commutation at its TRGO output (connected to Timer used in this function) each time
- * the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
- * @param htim TIM handle
- * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource the Commutation Event source
- * This parameter can be one of the following values:
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
- uint32_t CommutationSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
- assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
- __HAL_LOCK(htim);
-
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
- {
- /* Select the Input trigger */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= InputTrigger;
- }
-
- /* Select the Capture Compare preload feature */
- htim->Instance->CR2 |= TIM_CR2_CCPC;
- /* Select the Commutation event source */
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;
- htim->Instance->CR2 |= CommutationSource;
-
- /* Enable the Commutation DMA Request */
- /* Set the DMA Commutation Callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
-
- /* Disable Commutation Interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
-
- /* Enable the Commutation DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the TIM in master mode.
- * @param htim TIM handle.
- * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
- * contains the selected trigger output (TRGO) and the Master/Slave
- * mode.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
- TIM_MasterConfigTypeDef *sMasterConfig)
-{
- uint32_t tmpcr2;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
- assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- /* Change the handler state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = htim->Instance->CR2;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
- if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
- {
- /* Check the parameters */
- assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
-
- /* Clear the MMS2 bits */
- tmpcr2 &= ~TIM_CR2_MMS2;
- /* Select the TRGO2 source*/
- tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
- }
-
- /* Reset the MMS Bits */
- tmpcr2 &= ~TIM_CR2_MMS;
- /* Select the TRGO source */
- tmpcr2 |= sMasterConfig->MasterOutputTrigger;
-
- /* Update TIMx CR2 */
- htim->Instance->CR2 = tmpcr2;
-
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- /* Reset the MSM Bit */
- tmpsmcr &= ~TIM_SMCR_MSM;
- /* Set master mode */
- tmpsmcr |= sMasterConfig->MasterSlaveMode;
-
- /* Update TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
- }
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
- * and the AOE(automatic output enable).
- * @param htim TIM handle
- * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
- * contains the BDTR Register configuration information for the TIM peripheral.
- * @note Interrupts can be generated when an active level is detected on the
- * break input, the break 2 input or the system break input. Break
- * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
- TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
-{
- /* Keep this variable initialized to 0 as it is used to configure BDTR register */
- uint32_t tmpbdtr = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
- assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
- assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
- assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
- assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
- assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
- assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
- assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
- assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
-
- /* Set the BDTR bits */
- MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
- MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
- MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
-
- if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
- {
- /* Check the parameters */
- assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
- assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
- assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
-
- /* Set the BREAK2 input related BDTR bits */
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
- }
-
- /* Set TIMx_BDTR */
- htim->Instance->BDTR = tmpbdtr;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the break input source.
- * @param htim TIM handle.
- * @param BreakInput Break input to configure
- * This parameter can be one of the following values:
- * @arg TIM_BREAKINPUT_BRK: Timer break input
- * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
- * @param sBreakInputConfig Break input source configuration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
- uint32_t BreakInput,
- TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
-
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmporx;
- uint32_t bkin_enable_mask;
- uint32_t bkin_polarity_mask;
- uint32_t bkin_enable_bitpos;
- uint32_t bkin_polarity_bitpos;
-
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
- assert_param(IS_TIM_BREAKINPUT(BreakInput));
- assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
- assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
-#if defined(DFSDM1_Channel0)
- if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
- {
- assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
- }
-#else
- assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
-#endif /* DFSDM1_Channel0 */
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- switch (sBreakInputConfig->Source)
- {
- case TIM_BREAKINPUTSOURCE_BKIN:
- {
- bkin_enable_mask = TIM1_OR2_BKINE;
- bkin_enable_bitpos = TIM1_OR2_BKINE_Pos;
- bkin_polarity_mask = TIM1_OR2_BKINP;
- bkin_polarity_bitpos = TIM1_OR2_BKINP_Pos;
- break;
- }
- case TIM_BREAKINPUTSOURCE_COMP1:
- {
- bkin_enable_mask = TIM1_OR2_BKCMP1E;
- bkin_enable_bitpos = TIM1_OR2_BKCMP1E_Pos;
- bkin_polarity_mask = TIM1_OR2_BKCMP1P;
- bkin_polarity_bitpos = TIM1_OR2_BKCMP1P_Pos;
- break;
- }
- case TIM_BREAKINPUTSOURCE_COMP2:
- {
- bkin_enable_mask = TIM1_OR2_BKCMP2E;
- bkin_enable_bitpos = TIM1_OR2_BKCMP2E_Pos;
- bkin_polarity_mask = TIM1_OR2_BKCMP2P;
- bkin_polarity_bitpos = TIM1_OR2_BKCMP2P_Pos;
- break;
- }
-#if defined(DFSDM1_Channel0)
- case TIM_BREAKINPUTSOURCE_DFSDM1:
- {
- bkin_enable_mask = TIM1_OR2_BKDF1BK0E;
- bkin_enable_bitpos = TIM1_OR2_BKDF1BK0E_Pos;
- bkin_polarity_mask = 0U;
- bkin_polarity_bitpos = 0U;
- break;
- }
-#endif /* DFSDM1_Channel0 */
-
- default:
- {
- bkin_enable_mask = 0U;
- bkin_polarity_mask = 0U;
- bkin_enable_bitpos = 0U;
- bkin_polarity_bitpos = 0U;
- break;
- }
- }
-
- switch (BreakInput)
- {
- case TIM_BREAKINPUT_BRK:
- {
- /* Get the TIMx_OR2 register value */
- tmporx = htim->Instance->OR2;
-
- /* Enable the break input */
- tmporx &= ~bkin_enable_mask;
- tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
-
- /* Set the break input polarity */
-#if defined(DFSDM1_Channel0)
- if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
-#endif /* DFSDM1_Channel0 */
- {
- tmporx &= ~bkin_polarity_mask;
- tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
- }
-
- /* Set TIMx_OR2 */
- htim->Instance->OR2 = tmporx;
- break;
- }
- case TIM_BREAKINPUT_BRK2:
- {
- /* Get the TIMx_OR3 register value */
- tmporx = htim->Instance->OR3;
-
- /* Enable the break input */
- tmporx &= ~bkin_enable_mask;
- tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
-
- /* Set the break input polarity */
-#if defined(DFSDM1_Channel0)
- if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
-#endif /* DFSDM1_Channel0 */
- {
- tmporx &= ~bkin_polarity_mask;
- tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
- }
-
- /* Set TIMx_OR3 */
- htim->Instance->OR3 = tmporx;
- break;
- }
- default:
- status = HAL_ERROR;
- break;
- }
-
- __HAL_UNLOCK(htim);
-
- return status;
-}
-
-/**
- * @brief Configures the TIMx Remapping input capabilities.
- * @param htim TIM handle.
- * @param Remap specifies the TIM remapping source.
- @if STM32L422xx
- * For TIM1, the parameter is a combination of 2 fields (field1 | field2):
- *
- * field1 can have the following values:
- * @arg TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
- * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
- * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
- * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
- *
- * field2 can have the following values:
- * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
- * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
- *
- @endif
-@if STM32L486xx
- * For TIM1, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4):
- *
- * field1 can have the following values:
- * @arg TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
- * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
- * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
- * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
- *
- * field2 can have the following values:
- * @arg TIM_TIM1_ETR_ADC3_NONE: TIM1_ETR is not connected to any ADC3 AWD (analog watchdog)
- * @arg TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1
- * @arg TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2
- * @arg TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3
- *
- * field3 can have the following values:
- * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
- * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
- *
- * field4 can have the following values:
- * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output
- * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output
- * @note When field4 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 and field2 values are not significant
- @endif
- @if STM32L443xx
- * For TIM1, the parameter is a combination of 3 fields (field1 | field2 | field3):
- *
- * field1 can have the following values:
- * @arg TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
- * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
- * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
- * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
- *
- * field2 can have the following values:
- * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
- * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
- *
- * field3 can have the following values:
- * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output
- * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output
- *
- * @note When field3 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 values is not significant
- *
- @endif
- @if STM32L486xx
- * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
- *
- * field1 can have the following values:
- * @arg TIM_TIM2_ITR1_TIM8_TRGO: TIM2_ITR1 is connected to TIM8_TRGO
- * @arg TIM_TIM2_ITR1_OTG_FS_SOF: TIM2_ITR1 is connected to OTG_FS SOF
- *
- * field2 can have the following values:
- * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO
- * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
- * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output
- * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output
- *
- * field3 can have the following values:
- * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
- * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
- * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output
- * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
- @endif
- @if STM32L422xx
- * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
- *
- * field1 can have the following values:
- * @arg TIM_TIM2_ITR1_NONE: No internal trigger on TIM2_ITR1
- * @arg TIM_TIM2_ITR1_USB_SOF: TIM2_ITR1 is connected to USB SOF
- *
- * field2 can have the following values:
- * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO
- * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
- * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output
- *
- * field3 can have the following values:
- * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
- * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
- *
- @endif
- @if STM32L443xx
- * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
- *
- * field1 can have the following values:
- * @arg TIM_TIM2_ITR1_NONE: No internal trigger on TIM2_ITR1
- * @arg TIM_TIM2_ITR1_USB_SOF: TIM2_ITR1 is connected to USB SOF
- *
- * field2 can have the following values:
- * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO
- * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
- * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output
- * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output
- *
- * field3 can have the following values:
- * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
- * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
- * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output
- * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
- *
- @endif
- @if STM32L486xx
- * For TIM3, the parameter is a combination 2 fields(field1 | field2):
- *
- * field1 can have the following values:
- * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
- * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output
- * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output
- * @arg TIM_TIM3_TI1_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
- *
- * field2 can have the following values:
- * @arg TIM_TIM3_ETR_GPIO: TIM3_ETR is connected to GPIO
- * @arg TIM_TIM3_ETR_COMP1: TIM3_ETR is connected to COMP1 output
- *
- @endif
- @if STM32L486xx
- * For TIM8, the parameter is a combination of 3 fields (field1 | field2 | field3):
- *
- * field1 can have the following values:
- * @arg TIM_TIM8_ETR_ADC2_NONE: TIM8_ETR is not connected to any ADC2 AWD (analog watchdog)
- * @arg TIM_TIM8_ETR_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
- * @arg TIM_TIM8_ETR_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
- * @arg TIM_TIM8_ETR_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
- *
- * field2 can have the following values:
- * @arg TIM_TIM8_ETR_ADC3_NONE: TIM8_ETR is not connected to any ADC3 AWD (analog watchdog)
- * @arg TIM_TIM8_ETR_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
- * @arg TIM_TIM8_ETR_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
- * @arg TIM_TIM8_ETR_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
- *
- * field3 can have the following values:
- * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
- * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
- *
- * field4 can have the following values:
- * @arg TIM_TIM8_ETR_COMP1: TIM8_ETR is connected to COMP1 output
- * @arg TIM_TIM8_ETR_COMP2: TIM8_ETR is connected to COMP2 output
- * @note When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant
- *
- @endif
- @if STM32L422xx
- * For TIM15, the parameter is a combination of 2 fields (field1 | field2):
- *
- * field1 can have the following values:
- * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
- * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE
- *
- * field2 can have the following values:
- * @arg TIM_TIM15_ENCODERMODE_NONE: No redirection
- * @arg TIM_TIM15_ENCODERMODE_TIM2: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
- *
- @endif
- @if STM32L443xx
- * For TIM15, the parameter is a combination of 2 fields (field1 | field2):
- *
- * field1 can have the following values:
- * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
- * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE
- *
- * field2 can have the following values:
- * @arg TIM_TIM15_ENCODERMODE_NONE: No redirection
- * @arg TIM_TIM15_ENCODERMODE_TIM2: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
- * @arg TIM_TIM15_ENCODERMODE_TIM3: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
- * @arg TIM_TIM15_ENCODERMODE_TIM4: TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
- *
- @endif
- @if STM32L486xx
- * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
- * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
- * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
- * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
- *
- @endif
- @if STM32L422xx
- * For TIM16, the parameter can have the following values:
- * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
- * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
- * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
- * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
- * @arg TIM_TIM16_TI1_MSI: TIM16 TI1 is connected to MSI (constraints: MSI clock < 1/4 TIM APB clock)
- * @arg TIM_TIM16_TI1_HSE_32: TIM16 TI1 is connected to HSE div 32 (note that HSE div 32 must be selected as RTC clock source)
- * @arg TIM_TIM16_TI1_MCO: TIM16 TI1 is connected to MCO
- *
- @endif
- @if STM32L443xx
- * For TIM16, the parameter can have the following values:
- * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
- * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
- * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
- * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
- * @arg TIM_TIM16_TI1_MSI: TIM16 TI1 is connected to MSI (constraints: MSI clock < 1/4 TIM APB clock)
- * @arg TIM_TIM16_TI1_HSE_32: TIM16 TI1 is connected to HSE div 32 (note that HSE div 32 must be selected as RTC clock source)
- * @arg TIM_TIM16_TI1_MCO: TIM16 TI1 is connected to MCO
- *
- @endif
- @if STM32L486xx
- * For TIM17, the parameter can have the following values:
- * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
- * @arg TIM_TIM17_TI1_MSI: TIM17 TI1 is connected to MSI (constraints: MSI clock < 1/4 TIM APB clock)
- * @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32
- * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO
- @endif
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
-{
- uint32_t tmpor1;
- uint32_t tmpor2;
-
- /* Check parameters */
- assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
- assert_param(IS_TIM_REMAP(Remap));
-
- __HAL_LOCK(htim);
-
- /* Set ETR_SEL bit field (if required) */
- if (IS_TIM_ETRSEL_INSTANCE(htim->Instance))
- {
- tmpor2 = htim->Instance->OR2;
- tmpor2 &= ~TIM1_OR2_ETRSEL_Msk;
- tmpor2 |= (Remap & TIM1_OR2_ETRSEL_Msk);
-
- /* Set TIMx_OR2 */
- htim->Instance->OR2 = tmpor2;
- }
-
- /* Set other remapping capabilities */
- tmpor1 = Remap;
- tmpor1 &= ~TIM1_OR2_ETRSEL_Msk;
-
- /* Set TIMx_OR1 */
- htim->Instance->OR1 = tmpor1;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Group channel 5 and channel 1, 2 or 3
- * @param htim TIM handle.
- * @param Channels specifies the reference signal(s) the OC5REF is combined with.
- * This parameter can be any combination of the following values:
- * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
- * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
- * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
- * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
-{
- /* Check parameters */
- assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_GROUPCH5(Channels));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Clear GC5Cx bit fields */
- htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
-
- /* Set GC5Cx bit fields */
- htim->Instance->CCR5 |= Channels;
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
- * @brief Extended Callbacks functions
- *
-@verbatim
- ==============================================================================
- ##### Extended Callbacks functions #####
- ==============================================================================
- [..]
- This section provides Extended TIM callback functions:
- (+) Timer Commutation callback
- (+) Timer Break callback
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Hall commutation changed callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_CommutCallback could be implemented in the user file
- */
-}
-/**
- * @brief Hall commutation changed half complete callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Hall Break detection callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_BreakCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Hall Break2 detection callback in non blocking mode
- * @param htim: TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_Break2Callback could be implemented in the user file
- */
-}
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
- * @brief Extended Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Extended Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the TIM Hall Sensor interface handle state.
- * @param htim TIM Hall Sensor handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return actual state of the TIM complementary channel.
- * @param htim TIM handle
- * @param ChannelN TIM Complementary channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @retval TIM Complementary channel state
- */
-HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
-{
- HAL_TIM_ChannelStateTypeDef channel_state;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
-
- channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
-
- return channel_state;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
- * @{
- */
-
-/**
- * @brief TIM DMA Commutation callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->CommutationCallback(htim);
-#else
- HAL_TIMEx_CommutCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
- * @brief TIM DMA Commutation half complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->CommutationHalfCpltCallback(htim);
-#else
- HAL_TIMEx_CommutHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-
-/**
- * @brief TIM DMA Delay Pulse complete callback (complementary channel).
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
- else
- {
- /* nothing to do */
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA error callback (complementary channel)
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
- }
- else
- {
- /* nothing to do */
- }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->ErrorCallback(htim);
-#else
- HAL_TIM_ErrorCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel xN.
- * @param TIMx to select the TIM peripheral
- * @param Channel specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
- * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
- * @retval None
- */
-static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
-{
- uint32_t tmp;
-
- tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
-
- /* Reset the CCxNE Bit */
- TIMx->CCER &= ~tmp;
-
- /* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
-}
-/**
- * @}
- */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma.c
new file mode 100644
index 0000000..5d18638
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma.c
@@ -0,0 +1,400 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_dma.c
+ * @author MCD Application Team
+ * @brief DMA LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_dma.h"
+#include "stm32l4xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup DMA_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
+ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
+ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
+
+#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
+ ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
+
+#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
+
+#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
+
+#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
+ ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
+ ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
+
+#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
+ ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
+ ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
+
+#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
+
+#if defined(DMAMUX1)
+#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= 93U)
+#else
+#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) (((__VALUE__) == LL_DMA_REQUEST_0) || \
+ ((__VALUE__) == LL_DMA_REQUEST_1) || \
+ ((__VALUE__) == LL_DMA_REQUEST_2) || \
+ ((__VALUE__) == LL_DMA_REQUEST_3) || \
+ ((__VALUE__) == LL_DMA_REQUEST_4) || \
+ ((__VALUE__) == LL_DMA_REQUEST_5) || \
+ ((__VALUE__) == LL_DMA_REQUEST_6) || \
+ ((__VALUE__) == LL_DMA_REQUEST_7))
+#endif /* DMAMUX1 */
+
+#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
+
+#if defined (DMA2)
+#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
+ (((INSTANCE) == DMA2) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_7))))
+#else
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
+ (((INSTANCE) == DMA2) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5))))
+#endif
+#else
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_7))))
+#endif
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DMA_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the DMA registers to their default reset values.
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @arg @ref LL_DMA_CHANNEL_ALL
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DMA registers are de-initialized
+ * - ERROR: DMA registers are not de-initialized
+ */
+ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ ErrorStatus status = SUCCESS;
+ DMA_Channel_TypeDef *tmp;
+
+ /* Check the DMA Instance DMAx and Channel parameters*/
+ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));
+
+ if (Channel == LL_DMA_CHANNEL_ALL)
+ {
+ if (DMAx == DMA1)
+ {
+ /* Force reset of DMA clock */
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
+
+ /* Release reset of DMA clock */
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
+ }
+#if defined(DMA2)
+ else if (DMAx == DMA2)
+ {
+ /* Force reset of DMA clock */
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
+
+ /* Release reset of DMA clock */
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
+ }
+#endif
+ else
+ {
+ status = ERROR;
+ }
+ }
+ else
+ {
+ tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
+
+ /* Disable the selected DMAx_Channely */
+ CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
+
+ /* Reset DMAx_Channely control register */
+ WRITE_REG(tmp->CCR, 0U);
+
+ /* Reset DMAx_Channely remaining bytes register */
+ WRITE_REG(tmp->CNDTR, 0U);
+
+ /* Reset DMAx_Channely peripheral address register */
+ WRITE_REG(tmp->CPAR, 0U);
+
+ /* Reset DMAx_Channely memory 0 address register */
+ WRITE_REG(tmp->CMAR, 0U);
+
+#if defined(DMAMUX1)
+ /* Reset Request register field for DMAx Channel */
+ LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQ_MEM2MEM);
+#else
+ /* Reset Request register field for DMAx Channel */
+ LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0);
+#endif /* DMAMUX1 */
+
+ if (Channel == LL_DMA_CHANNEL_1)
+ {
+ /* Reset interrupt pending bits for DMAx Channel1 */
+ LL_DMA_ClearFlag_GI1(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_2)
+ {
+ /* Reset interrupt pending bits for DMAx Channel2 */
+ LL_DMA_ClearFlag_GI2(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_3)
+ {
+ /* Reset interrupt pending bits for DMAx Channel3 */
+ LL_DMA_ClearFlag_GI3(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_4)
+ {
+ /* Reset interrupt pending bits for DMAx Channel4 */
+ LL_DMA_ClearFlag_GI4(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_5)
+ {
+ /* Reset interrupt pending bits for DMAx Channel5 */
+ LL_DMA_ClearFlag_GI5(DMAx);
+ }
+
+ else if (Channel == LL_DMA_CHANNEL_6)
+ {
+ /* Reset interrupt pending bits for DMAx Channel6 */
+ LL_DMA_ClearFlag_GI6(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_7)
+ {
+ /* Reset interrupt pending bits for DMAx Channel7 */
+ LL_DMA_ClearFlag_GI7(DMAx);
+ }
+ else
+ {
+ status = ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
+ * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
+ * @arg @ref __LL_DMA_GET_INSTANCE
+ * @arg @ref __LL_DMA_GET_CHANNEL
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DMA registers are initialized
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+ /* Check the DMA Instance DMAx and Channel parameters*/
+ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
+
+ /* Check the DMA parameters from DMA_InitStruct */
+ assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
+ assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
+ assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
+ assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
+ assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
+ assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
+ assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
+ assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
+ assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
+
+ /*---------------------------- DMAx CCR Configuration ------------------------
+ * Configure DMAx_Channely: data transfer direction, data transfer mode,
+ * peripheral and memory increment mode,
+ * data size alignment and priority level with parameters :
+ * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
+ * - Mode: DMA_CCR_CIRC bit
+ * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
+ * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
+ * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
+ * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
+ * - Priority: DMA_CCR_PL[1:0] bits
+ */
+ LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
+ DMA_InitStruct->Mode | \
+ DMA_InitStruct->PeriphOrM2MSrcIncMode | \
+ DMA_InitStruct->MemoryOrM2MDstIncMode | \
+ DMA_InitStruct->PeriphOrM2MSrcDataSize | \
+ DMA_InitStruct->MemoryOrM2MDstDataSize | \
+ DMA_InitStruct->Priority);
+
+ /*-------------------------- DMAx CMAR Configuration -------------------------
+ * Configure the memory or destination base address with parameter :
+ * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
+ */
+ LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
+
+ /*-------------------------- DMAx CPAR Configuration -------------------------
+ * Configure the peripheral or source base address with parameter :
+ * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
+ */
+ LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
+
+ /*--------------------------- DMAx CNDTR Configuration -----------------------
+ * Configure the peripheral base address with parameter :
+ * - NbData: DMA_CNDTR_NDT[15:0] bits
+ */
+ LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
+
+#if defined(DMAMUX1)
+ /*--------------------------- DMAMUXx CCR Configuration ----------------------
+ * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter :
+ * - PeriphRequest: DMA_CxCR[7:0] bits
+ */
+ LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
+#else
+ /*--------------------------- DMAx CSELR Configuration -----------------------
+ * Configure the DMA request for DMA instance on Channel x with parameter :
+ * - PeriphRequest: DMA_CSELR[31:0] bits
+ */
+ LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
+#endif /* DMAMUX1 */
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
+ * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
+ * @retval None
+ */
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+ /* Set DMA_InitStruct fields to default values */
+ DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
+ DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
+ DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
+ DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
+ DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
+ DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
+ DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
+ DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
+ DMA_InitStruct->NbData = 0x00000000U;
+#if defined(DMAMUX1)
+ DMA_InitStruct->PeriphRequest = LL_DMAMUX_REQ_MEM2MEM;
+#else
+ DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0;
+#endif /* DMAMUX1 */
+ DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c
new file mode 100644
index 0000000..8d28066
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c
@@ -0,0 +1,288 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_exti.c
+ * @author MCD Application Team
+ * @brief EXTI LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_exti.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
+#define IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
+
+#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
+ || ((__VALUE__) == LL_EXTI_MODE_EVENT) \
+ || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
+
+
+#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup EXTI_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the EXTI registers to their default reset values.
+ * @retval An ErrorStatus enumeration value:
+ * - 0x00: EXTI registers are de-initialized
+ */
+uint32_t LL_EXTI_DeInit(void)
+{
+ /* Interrupt mask register set to default reset values */
+ LL_EXTI_WriteReg(IMR1, 0xFF820000U);
+ /* Event mask register set to default reset values */
+ LL_EXTI_WriteReg(EMR1, 0x00000000U);
+ /* Rising Trigger selection register set to default reset values */
+ LL_EXTI_WriteReg(RTSR1, 0x00000000U);
+ /* Falling Trigger selection register set to default reset values */
+ LL_EXTI_WriteReg(FTSR1, 0x00000000U);
+ /* Software interrupt event register set to default reset values */
+ LL_EXTI_WriteReg(SWIER1, 0x00000000U);
+ /* Pending register clear */
+ LL_EXTI_WriteReg(PR1, 0x007DFFFFU);
+
+ /* Interrupt mask register 2 set to default reset values */
+#if defined(LL_EXTI_LINE_40)
+ LL_EXTI_WriteReg(IMR2, 0x00000187U);
+#else
+ LL_EXTI_WriteReg(IMR2, 0x00000087U);
+#endif
+ /* Event mask register 2 set to default reset values */
+ LL_EXTI_WriteReg(EMR2, 0x00000000U);
+ /* Rising Trigger selection register 2 set to default reset values */
+ LL_EXTI_WriteReg(RTSR2, 0x00000000U);
+ /* Falling Trigger selection register 2 set to default reset values */
+ LL_EXTI_WriteReg(FTSR2, 0x00000000U);
+ /* Software interrupt event register 2 set to default reset values */
+ LL_EXTI_WriteReg(SWIER2, 0x00000000U);
+ /* Pending register 2 clear */
+ LL_EXTI_WriteReg(PR2, 0x00000078U);
+
+ return 0x00u;
+}
+
+/**
+ * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
+ * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - 0x00: EXTI registers are initialized
+ * - any other value : wrong configuration
+ */
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+ uint32_t status = 0x00u;
+
+ /* Check the parameters */
+ assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
+ assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
+ assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
+
+ /* ENABLE LineCommand */
+ if (EXTI_InitStruct->LineCommand != DISABLE)
+ {
+ assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
+
+ /* Configure EXTI Lines in range from 0 to 31 */
+ if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
+ {
+ switch (EXTI_InitStruct->Mode)
+ {
+ case LL_EXTI_MODE_IT:
+ /* First Disable Event on provided Lines */
+ LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable IT on provided Lines */
+ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_MODE_EVENT:
+ /* First Disable IT on provided Lines */
+ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Event on provided Lines */
+ LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_MODE_IT_EVENT:
+ /* Directly Enable IT & Event on provided Lines */
+ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ default:
+ status = 0x01u;
+ break;
+ }
+ if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+ {
+ switch (EXTI_InitStruct->Trigger)
+ {
+ case LL_EXTI_TRIGGER_RISING:
+ /* First Disable Falling Trigger on provided Lines */
+ LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Rising Trigger on provided Lines */
+ LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_TRIGGER_FALLING:
+ /* First Disable Rising Trigger on provided Lines */
+ LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Falling Trigger on provided Lines */
+ LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_TRIGGER_RISING_FALLING:
+ LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ default:
+ status |= 0x02u;
+ break;
+ }
+ }
+ }
+ /* Configure EXTI Lines in range from 32 to 63 */
+ if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
+ {
+ switch (EXTI_InitStruct->Mode)
+ {
+ case LL_EXTI_MODE_IT:
+ /* First Disable Event on provided Lines */
+ LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+ /* Then Enable IT on provided Lines */
+ LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ case LL_EXTI_MODE_EVENT:
+ /* First Disable IT on provided Lines */
+ LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+ /* Then Enable Event on provided Lines */
+ LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ case LL_EXTI_MODE_IT_EVENT:
+ /* Directly Enable IT & Event on provided Lines */
+ LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
+ LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ default:
+ status |= 0x04u;
+ break;
+ }
+ if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+ {
+ switch (EXTI_InitStruct->Trigger)
+ {
+ case LL_EXTI_TRIGGER_RISING:
+ /* First Disable Falling Trigger on provided Lines */
+ LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ /* Then Enable IT on provided Lines */
+ LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ case LL_EXTI_TRIGGER_FALLING:
+ /* First Disable Rising Trigger on provided Lines */
+ LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ /* Then Enable Falling Trigger on provided Lines */
+ LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ case LL_EXTI_TRIGGER_RISING_FALLING:
+ LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ }
+ }
+ }
+ /* DISABLE LineCommand */
+ else
+ {
+ /* De-configure EXTI Lines in range from 0 to 31 */
+ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ /* De-configure EXTI Lines in range from 32 to 63 */
+ LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+ LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
+ * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
+ * @retval None
+ */
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+ EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
+ EXTI_InitStruct->Line_32_63 = LL_EXTI_LINE_NONE;
+ EXTI_InitStruct->LineCommand = DISABLE;
+ EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
+ EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (EXTI) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_gpio.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_gpio.c
new file mode 100644
index 0000000..c3dd30c
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_gpio.c
@@ -0,0 +1,293 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_gpio.c
+ * @author MCD Application Team
+ * @brief GPIO LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_gpio.h"
+#include "stm32l4xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI)
+
+/** @addtogroup GPIO_LL
+ * @{
+ */
+/** MISRA C:2012 deviation rule has been granted for following rules:
+ * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
+ * range of the shift operator in following API :
+ * LL_GPIO_Init
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
+
+#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
+ ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
+ ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
+ ((__VALUE__) == LL_GPIO_MODE_ANALOG))
+
+#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
+ ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
+
+#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\
+ ((__VALUE__) == LL_GPIO_PULL_UP) ||\
+ ((__VALUE__) == LL_GPIO_PULL_DOWN))
+
+#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_1 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_2 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_3 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_4 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_5 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_6 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_7 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_8 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_9 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_10 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_11 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_12 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_13 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_14 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_15 ))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize GPIO registers (Registers restored to their default values).
+ * @param GPIOx GPIO Port
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: GPIO registers are de-initialized
+ * - ERROR: Wrong GPIO Port
+ */
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ /* Force and Release reset on clock of GPIOx Port */
+ if (GPIOx == GPIOA)
+ {
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA);
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA);
+ }
+ else if (GPIOx == GPIOB)
+ {
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB);
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB);
+ }
+ else if (GPIOx == GPIOC)
+ {
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC);
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC);
+ }
+#if defined(GPIOD)
+ else if (GPIOx == GPIOD)
+ {
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD);
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD);
+ }
+#endif /* GPIOD */
+#if defined(GPIOE)
+ else if (GPIOx == GPIOE)
+ {
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE);
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE);
+ }
+#endif /* GPIOE */
+#if defined(GPIOF)
+ else if (GPIOx == GPIOF)
+ {
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOF);
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOF);
+ }
+#endif /* GPIOF */
+#if defined(GPIOG)
+ else if (GPIOx == GPIOG)
+ {
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOG);
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOG);
+ }
+#endif /* GPIOG */
+#if defined(GPIOH)
+ else if (GPIOx == GPIOH)
+ {
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH);
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH);
+ }
+#endif /* GPIOH */
+#if defined(GPIOI)
+ else if (GPIOx == GPIOI)
+ {
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOI);
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOI);
+ }
+#endif /* GPIOI */
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
+ * @param GPIOx GPIO Port
+ * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
+ * that contains the configuration information for the specified GPIO peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+ uint32_t pinpos;
+ uint32_t currentpin;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
+ assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
+ assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
+
+ /* ------------------------- Configure the port pins ---------------- */
+ /* Initialize pinpos on first pin set */
+ pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
+
+ /* Configure the port pins */
+ while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u)
+ {
+ /* Get current io position */
+ currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos);
+
+ if (currentpin != 0x00u)
+ {
+ if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+ {
+ /* Check Speed mode parameters */
+ assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
+
+ /* Speed mode configuration */
+ LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+
+ /* Check Output mode parameters */
+ assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+ /* Output mode configuration*/
+ LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
+ }
+
+ /* Pull-up Pull down resistor configuration*/
+ LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
+
+ if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
+ {
+ /* Check Alternate parameter */
+ assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
+
+ /* Speed mode configuration */
+ if (currentpin < LL_GPIO_PIN_8)
+ {
+ LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+ }
+ else
+ {
+ LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+ }
+ }
+
+ /* Pin Mode configuration */
+ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
+ }
+ pinpos++;
+ }
+
+ return (SUCCESS);
+}
+
+/**
+ * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
+ * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
+ GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG;
+ GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ GPIO_InitStruct->Pull = LL_GPIO_PULL_NO;
+ GPIO_InitStruct->Alternate = LL_GPIO_AF_0;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_pwr.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_pwr.c
new file mode 100644
index 0000000..8907e5d
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_pwr.c
@@ -0,0 +1,82 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_pwr.c
+ * @author MCD Application Team
+ * @brief PWR LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_pwr.h"
+#include "stm32l4xx_ll_bus.h"
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup PWR_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the PWR registers to their default reset values.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: PWR registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_PWR_DeInit(void)
+{
+ /* Force reset of PWR clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
+
+ /* Release reset of PWR clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
+
+ return SUCCESS;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined(PWR) */
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c
new file mode 100644
index 0000000..f7f6d08
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c
@@ -0,0 +1,2039 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_rcc.c
+ * @author MCD Application Team
+ * @brief RCC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_rcc.h"
+#ifdef USE_FULL_ASSERT
+ #include "stm32_assert.h"
+#else
+ #define assert_param(expr) ((void)0U)
+#endif
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @addtogroup RCC_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_LL_Private_Macros
+ * @{
+ */
+#if defined(RCC_CCIPR_USART3SEL)
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
+#else
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
+
+#endif /* RCC_CCIPR_USART3SEL */
+#if defined(RCC_CCIPR_UART4SEL) && defined(RCC_CCIPR_UART5SEL)
+#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
+#elif defined(RCC_CCIPR_UART4SEL)
+#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
+#elif defined(RCC_CCIPR_UART5SEL)
+#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)
+#endif /* RCC_CCIPR_UART4SEL && RCC_CCIPR_UART5SEL*/
+
+#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
+
+#if defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL) && defined(RCC_CCIPR2_I2C4SEL)
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
+#elif defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL)
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
+
+#elif !defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL)
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
+
+#else
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
+
+#endif /* RCC_CCIPR_I2C2SEL && RCC_CCIPR_I2C3SEL && RCC_CCIPR2_I2C4SEL */
+#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE))
+
+#if defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI2SEL)
+#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
+#elif defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL)
+#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)
+#endif /* RCC_CCIPR_SAI2SEL RCC_CCIPR2_SAI2SEL ||*/
+
+#if defined(SDMMC1)
+#if defined(RCC_CCIPR2_SDMMCSEL)
+#define IS_LL_RCC_SDMMC_KERNELCLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_KERNELCLKSOURCE))
+#endif /* RCC_CCIPR2_SDMMCSEL */
+
+#define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
+#endif /* SDMMC1 */
+
+#define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
+
+#if defined(USB_OTG_FS) || defined(USB)
+#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
+#endif /* USB_OTG_FS || USB */
+
+#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
+
+#if defined(SWPMI1)
+#define IS_LL_RCC_SWPMI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SWPMI1_CLKSOURCE))
+#endif /* SWPMI1 */
+
+#if defined(DFSDM1_Channel0)
+#define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
+#if defined(RCC_CCIPR2_DFSDM1SEL)
+#define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
+#endif /* RCC_CCIPR2_DFSDM1SEL */
+#endif /* DFSDM1_Channel0 */
+
+#if defined(DSI)
+#define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
+#endif /* DSI */
+
+#if defined(LTDC)
+#define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
+#endif /* LTDC */
+
+#if defined(OCTOSPI1)
+#define IS_LL_RCC_OCTOSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_OCTOSPI_CLKSOURCE))
+#endif /* OCTOSPI */
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCC_LL_Private_Functions RCC Private functions
+ * @{
+ */
+static uint32_t RCC_GetSystemClockFreq(void);
+static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
+static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_PLL_GetFreqDomain_SYS(void);
+#if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI1SEL) || defined(RCC_CCIPR2_SAI2SEL)
+static uint32_t RCC_PLL_GetFreqDomain_SAI(void);
+#endif
+static uint32_t RCC_PLL_GetFreqDomain_48M(void);
+#if defined(RCC_PLLSAI1_SUPPORT)
+static uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void);
+static uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void);
+static uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void);
+#endif /* RCC_PLLSAI1_SUPPORT */
+#if defined(RCC_PLLSAI2_SUPPORT)
+static uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void);
+#if defined(LTDC)
+static uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void);
+#else
+static uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void);
+#endif /* LTDC */
+#if defined(DSI)
+static uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void);
+#endif /* DSI */
+#endif /*RCC_PLLSAI2_SUPPORT*/
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Reset the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - MSI ON and used as system clock source
+ * - HSE, HSI, PLL, PLLSAI1 and PLLSAI2 OFF
+ * - AHB, APB1 and APB2 prescaler set to 1.
+ * - CSS, MCO OFF
+ * - All interrupts disabled
+ * @note This function doesn't modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RCC registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_RCC_DeInit(void)
+{
+ __IO uint32_t vl_mask;
+
+ /* Set MSION bit */
+ LL_RCC_MSI_Enable();
+
+ /* Insure MSIRDY bit is set before writing default MSIRANGE value */
+ while (LL_RCC_MSI_IsReady() == 0U)
+ {
+ }
+
+ /* Set MSIRANGE default value */
+ LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
+
+ /* Set MSITRIM bits to the reset value*/
+ LL_RCC_MSI_SetCalibTrimming(0);
+
+ /* Set HSITRIM bits to the reset value*/
+#if defined(RCC_ICSCR_HSITRIM_6)
+ LL_RCC_HSI_SetCalibTrimming(0x40U);
+#else
+ LL_RCC_HSI_SetCalibTrimming(0x10U);
+#endif /* RCC_ICSCR_HSITRIM_6 */
+
+ /* Reset CFGR register */
+ LL_RCC_WriteReg(CFGR, 0x00000000U);
+
+ /* Read CR register */
+ vl_mask = LL_RCC_ReadReg(CR);
+
+ /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLON bits */
+ CLEAR_BIT(vl_mask,
+ (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON | RCC_CR_HSEON | RCC_CR_PLLON));
+
+#if defined(RCC_PLLSAI1_SUPPORT)
+ /* Reset PLLSAI1ON bit */
+ CLEAR_BIT(vl_mask, RCC_CR_PLLSAI1ON);
+#endif /*RCC_PLLSAI1_SUPPORT*/
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+ /* Reset PLLSAI2ON bit */
+ CLEAR_BIT(vl_mask, RCC_CR_PLLSAI2ON);
+#endif /*RCC_PLLSAI2_SUPPORT*/
+
+ /* Write new value in CR register */
+ LL_RCC_WriteReg(CR, vl_mask);
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+ /* Wait for PLLRDY, PLLSAI1RDY and PLLSAI2RDY bits to be reset */
+ while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U)
+ {
+ }
+#elif defined(RCC_PLLSAI1_SUPPORT)
+ /* Wait for PLLRDY and PLLSAI1RDY to be reset */
+ while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U)
+ {
+ }
+#else
+ /* Wait for PLLRDY bit to be reset */
+ while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
+ {
+ }
+#endif
+
+ /* Reset PLLCFGR register */
+ LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos);
+
+#if defined(RCC_PLLSAI1_SUPPORT)
+ /* Reset PLLSAI1CFGR register */
+ LL_RCC_WriteReg(PLLSAI1CFGR, 16U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
+#endif /*RCC_PLLSAI1_SUPPORT*/
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+ /* Reset PLLSAI2CFGR register */
+ LL_RCC_WriteReg(PLLSAI2CFGR, 16U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
+#endif /*RCC_PLLSAI2_SUPPORT*/
+
+ /* Reset HSEBYP bit */
+ LL_RCC_HSE_DisableBypass();
+
+ /* Disable all interrupts */
+ LL_RCC_WriteReg(CIER, 0x00000000U);
+
+ /* Clear all interrupt flags */
+ vl_mask = RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \
+ RCC_CICR_CSSC | RCC_CICR_LSECSSC;
+#if defined(RCC_HSI48_SUPPORT)
+ vl_mask |= RCC_CICR_HSI48RDYC;
+#endif
+#if defined(RCC_PLLSAI1_SUPPORT)
+ vl_mask |= RCC_CICR_PLLSAI1RDYC;
+#endif
+#if defined(RCC_PLLSAI2_SUPPORT)
+ vl_mask |= RCC_CICR_PLLSAI2RDYC;
+#endif
+ LL_RCC_WriteReg(CICR, vl_mask);
+
+ /* Clear reset flags */
+ LL_RCC_ClearResetFlags();
+
+ return SUCCESS;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_LL_EF_Get_Freq
+ * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
+ * and different peripheral clocks available on the device.
+ * @note If SYSCLK source is MSI, function returns values based on MSI_VALUE(*)
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
+ * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
+ * or HSI_VALUE(**) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+ * @note (*) MSI_VALUE is a constant defined in this file (default value
+ * 4 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * @note (**) HSI_VALUE is a constant defined in this file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * @note (***) HSE_VALUE is a constant defined in this file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ * @note The result of this function could be incorrect when using fractional
+ * value for HSE crystal.
+ * @note This function can be used by the user application to compute the
+ * baud-rate for the communication peripherals or configure other parameters.
+ * @{
+ */
+
+/**
+ * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
+ * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
+ * must be called to update structure fields. Otherwise, any
+ * configuration based on this function will be incorrect.
+ * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
+ * @retval None
+ */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
+{
+ /* Get SYSCLK frequency */
+ RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
+
+ /* HCLK clock frequency */
+ RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
+
+ /* PCLK1 clock frequency */
+ RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+ /* PCLK2 clock frequency */
+ RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
+}
+
+/**
+ * @brief Return USARTx clock frequency
+ * @param USARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE
+ * @arg @ref LL_RCC_USART2_CLKSOURCE
+ * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval USART clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+ */
+uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
+{
+ uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
+
+ if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
+ {
+ /* USART1CLK clock frequency */
+ switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+ {
+ case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
+ usart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() != 0U)
+ {
+ usart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() != 0U)
+ {
+ usart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
+ usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ break;
+ }
+ }
+ else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
+ {
+ /* USART2CLK clock frequency */
+ switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+ {
+ case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
+ usart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() != 0U)
+ {
+ usart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() != 0U)
+ {
+ usart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
+ usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ break;
+ }
+ }
+ else
+ {
+#if defined(RCC_CCIPR_USART3SEL)
+ if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
+ {
+ /* USART3CLK clock frequency */
+ switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+ {
+ case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
+ usart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() != 0U)
+ {
+ usart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() != 0U)
+ {
+ usart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
+ usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ break;
+ }
+ }
+#endif /* RCC_CCIPR_USART3SEL */
+ }
+ return usart_frequency;
+}
+
+#if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
+/**
+ * @brief Return UARTx clock frequency
+ * @param UARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_UART4_CLKSOURCE
+ * @arg @ref LL_RCC_UART5_CLKSOURCE
+ * @retval UART clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+ */
+uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
+{
+ uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
+
+#if defined(RCC_CCIPR_UART4SEL)
+ if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
+ {
+ /* UART4CLK clock frequency */
+ switch (LL_RCC_GetUARTClockSource(UARTxSource))
+ {
+ case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
+ uart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() != 0U)
+ {
+ uart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() != 0U)
+ {
+ uart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
+ uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ break;
+ }
+ }
+#endif /* RCC_CCIPR_UART4SEL */
+
+#if defined(RCC_CCIPR_UART5SEL)
+ if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
+ {
+ /* UART5CLK clock frequency */
+ switch (LL_RCC_GetUARTClockSource(UARTxSource))
+ {
+ case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
+ uart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() != 0U)
+ {
+ uart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() != 0U)
+ {
+ uart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
+ uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ break;
+ }
+ }
+#endif /* RCC_CCIPR_UART5SEL */
+
+ return uart_frequency;
+}
+#endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
+
+/**
+ * @brief Return I2Cx clock frequency
+ * @param I2CxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE
+ * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval I2C clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
+ */
+uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
+{
+ uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
+
+ if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
+ {
+ /* I2C1 CLK clock frequency */
+ switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ {
+ case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
+ i2c_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() != 0U)
+ {
+ i2c_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
+ i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ break;
+ }
+ }
+#if defined(RCC_CCIPR_I2C2SEL)
+ else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
+ {
+ /* I2C2 CLK clock frequency */
+ switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ {
+ case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
+ i2c_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() != 0U)
+ {
+ i2c_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */
+ i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ break;
+ }
+ }
+#endif /*RCC_CCIPR_I2C2SEL*/
+ else
+ {
+ if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
+ {
+ /* I2C3 CLK clock frequency */
+ switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ {
+ case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
+ i2c_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() != 0U)
+ {
+ i2c_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */
+ i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ break;
+ }
+ }
+#if defined(RCC_CCIPR2_I2C4SEL)
+ else
+ {
+ if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
+ {
+ /* I2C4 CLK clock frequency */
+ switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ {
+ case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
+ i2c_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() != 0U)
+ {
+ i2c_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */
+ i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ break;
+ }
+ }
+ }
+#endif /*RCC_CCIPR2_I2C4SEL*/
+ }
+
+ return i2c_frequency;
+}
+
+
+/**
+ * @brief Return LPUARTx clock frequency
+ * @param LPUARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE
+ * @retval LPUART clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+ */
+uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
+{
+ uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
+
+ /* LPUART1CLK clock frequency */
+ switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
+ {
+ case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
+ lpuart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() != 0U)
+ {
+ lpuart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() != 0U)
+ {
+ lpuart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */
+ lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ break;
+ }
+
+ return lpuart_frequency;
+}
+
+/**
+ * @brief Return LPTIMx clock frequency
+ * @param LPTIMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+ * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
+ * @retval LPTIM clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
+ */
+uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
+{
+ uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
+
+ if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
+ {
+ /* LPTIM1CLK clock frequency */
+ switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
+ {
+ case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
+ if (LL_RCC_LSI_IsReady() != 0U)
+ {
+#if defined(RCC_CSR_LSIPREDIV)
+ if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128)
+ {
+ lptim_frequency = LSI_VALUE / 128U;
+ }
+ else
+#endif /* RCC_CSR_LSIPREDIV */
+ {
+ lptim_frequency = LSI_VALUE;
+ }
+ }
+ break;
+
+ case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() != 0U)
+ {
+ lptim_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() != 0U)
+ {
+ lptim_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
+ lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ break;
+ }
+ }
+ else
+ {
+ if (LPTIMxSource == LL_RCC_LPTIM2_CLKSOURCE)
+ {
+ /* LPTIM2CLK clock frequency */
+ switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
+ {
+ case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */
+ if (LL_RCC_LSI_IsReady() != 0U)
+ {
+#if defined(RCC_CSR_LSIPREDIV)
+ if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128)
+ {
+ lptim_frequency = LSI_VALUE / 128U;
+ }
+ else
+#endif /* RCC_CSR_LSIPREDIV */
+ {
+ lptim_frequency = LSI_VALUE;
+ }
+ }
+ break;
+
+ case LL_RCC_LPTIM2_CLKSOURCE_HSI: /* LPTIM2 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() != 0U)
+ {
+ lptim_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() != 0U)
+ {
+ lptim_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is PCLK1 */
+ lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ break;
+ }
+ }
+ }
+
+ return lptim_frequency;
+}
+
+#if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI1SEL) || defined(RCC_CCIPR2_SAI2SEL)
+/**
+ * @brief Return SAIx clock frequency
+ * @param SAIxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE
+ * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval SAI clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
+
+ */
+uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
+{
+ uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
+
+ if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
+ {
+ /* SAI1CLK clock frequency */
+ switch (LL_RCC_GetSAIClockSource(SAIxSource))
+ {
+ case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */
+ if (LL_RCC_PLLSAI1_IsReady() != 0U)
+ {
+ if (LL_RCC_PLLSAI1_IsEnabledDomain_SAI() != 0U)
+ {
+ sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
+ }
+ }
+ break;
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+ case LL_RCC_SAI1_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI1 clock source */
+ if (LL_RCC_PLLSAI2_IsReady() != 0U)
+ {
+ if (LL_RCC_PLLSAI2_IsEnabledDomain_SAI() != 0U)
+ {
+ sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
+ }
+ }
+ break;
+
+#endif /* RCC_PLLSAI2_SUPPORT */
+ case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
+ if (LL_RCC_PLL_IsReady() != 0U)
+ {
+ if (LL_RCC_PLL_IsEnabledDomain_SAI() != 0U)
+ {
+ sai_frequency = RCC_PLL_GetFreqDomain_SAI();
+ }
+ }
+ break;
+
+ case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
+ sai_frequency = EXTERNAL_SAI1_CLOCK_VALUE;
+ break;
+
+ default:
+ break;
+ }
+ }
+ else
+ {
+#if defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI2SEL)
+ if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
+ {
+ /* SAI2CLK clock frequency */
+ switch (LL_RCC_GetSAIClockSource(SAIxSource))
+ {
+ case LL_RCC_SAI2_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI2 clock source */
+ if (LL_RCC_PLLSAI1_IsReady() != 0U)
+ {
+ if (LL_RCC_PLLSAI1_IsEnabledDomain_SAI() != 0U)
+ {
+ sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
+ }
+ }
+ break;
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+ case LL_RCC_SAI2_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI2 clock source */
+ if (LL_RCC_PLLSAI2_IsReady() != 0U)
+ {
+ if (LL_RCC_PLLSAI2_IsEnabledDomain_SAI() != 0U)
+ {
+ sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
+ }
+ }
+ break;
+
+#endif /* RCC_PLLSAI2_SUPPORT */
+ case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */
+ if (LL_RCC_PLL_IsReady() != 0U)
+ {
+ if (LL_RCC_PLL_IsEnabledDomain_SAI() != 0U)
+ {
+ sai_frequency = RCC_PLL_GetFreqDomain_SAI();
+ }
+ }
+ break;
+
+ case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */
+ sai_frequency = EXTERNAL_SAI2_CLOCK_VALUE;
+ break;
+
+ default:
+ break;
+ }
+ }
+#endif /* RCC_CCIPR_SAI2SEL || RCC_CCIPR2_SAI2SEL */
+ }
+
+ return sai_frequency;
+}
+#endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR_SAI2SEL || RCC_CCIPR2_SAI1SEL || RCC_CCIPR2_SAI2SEL*/
+
+#if defined(SDMMC1)
+#if defined(RCC_CCIPR2_SDMMCSEL)
+/**
+ * @brief Return SDMMCx kernel clock frequency
+ * @param SDMMCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE
+ * @retval SDMMC clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
+ */
+uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource)
+{
+ uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_SDMMC_KERNELCLKSOURCE(SDMMCxSource));
+
+ /* SDMMC1CLK kernel clock frequency */
+ switch (LL_RCC_GetSDMMCKernelClockSource(SDMMCxSource))
+ {
+ case LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK: /* 48MHz clock from internal multiplexor used as SDMMC1 clock source */
+ sdmmc_frequency = LL_RCC_GetSDMMCClockFreq(LL_RCC_SDMMC1_CLKSOURCE);
+ break;
+
+ case LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP: /* PLL "P" output (PLLSAI3CLK) clock used as SDMMC1 clock source */
+ if (LL_RCC_PLL_IsReady() != 0U)
+ {
+ if (LL_RCC_PLL_IsEnabledDomain_SAI() != 0U)
+ {
+ sdmmc_frequency = RCC_PLL_GetFreqDomain_SAI();
+ }
+ }
+ break;
+
+ default:
+ sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+ break;
+ }
+
+ return sdmmc_frequency;
+}
+#endif
+
+/**
+ * @brief Return SDMMCx clock frequency
+ * @param SDMMCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
+ * @retval SDMMC clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
+ */
+uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
+{
+ uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
+
+ /* SDMMC1CLK clock frequency */
+ switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
+ {
+#if defined(LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1)
+ case LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SDMMC1 clock source */
+ if (LL_RCC_PLLSAI1_IsReady() != 0U)
+ {
+ if (LL_RCC_PLLSAI1_IsEnabledDomain_48M() != 0U)
+ {
+ sdmmc_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
+ }
+ }
+ break;
+#endif
+
+ case LL_RCC_SDMMC1_CLKSOURCE_PLL: /* PLL clock used as SDMMC1 clock source */
+ if (LL_RCC_PLL_IsReady() != 0U)
+ {
+ if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
+ {
+ sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
+ }
+ }
+ break;
+
+#if defined(LL_RCC_SDMMC1_CLKSOURCE_MSI)
+ case LL_RCC_SDMMC1_CLKSOURCE_MSI: /* MSI clock used as SDMMC1 clock source */
+ if (LL_RCC_MSI_IsReady() != 0U)
+ {
+ sdmmc_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ }
+ break;
+#endif
+
+#if defined(RCC_HSI48_SUPPORT)
+ case LL_RCC_SDMMC1_CLKSOURCE_HSI48: /* HSI48 used as SDMMC1 clock source */
+ if (LL_RCC_HSI48_IsReady() != 0U)
+ {
+ sdmmc_frequency = HSI48_VALUE;
+ }
+ break;
+#else
+ case LL_RCC_SDMMC1_CLKSOURCE_NONE: /* No clock used as SDMMC1 clock source */
+#endif
+ default:
+ sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+ break;
+ }
+
+ return sdmmc_frequency;
+}
+#endif /* SDMMC1 */
+
+/**
+ * @brief Return RNGx clock frequency
+ * @param RNGxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RNG_CLKSOURCE
+ * @retval RNG clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
+ */
+uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
+{
+ uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
+
+ /* RNGCLK clock frequency */
+ switch (LL_RCC_GetRNGClockSource(RNGxSource))
+ {
+#if defined(RCC_PLLSAI1_SUPPORT)
+ case LL_RCC_RNG_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as RNG clock source */
+ if (LL_RCC_PLLSAI1_IsReady() != 0U)
+ {
+ if (LL_RCC_PLLSAI1_IsEnabledDomain_48M() !=0U)
+ {
+ rng_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
+ }
+ }
+ break;
+#endif /* RCC_PLLSAI1_SUPPORT */
+
+ case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
+ if (LL_RCC_PLL_IsReady() != 0U)
+ {
+ if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
+ {
+ rng_frequency = RCC_PLL_GetFreqDomain_48M();
+ }
+ }
+ break;
+
+ case LL_RCC_RNG_CLKSOURCE_MSI: /* MSI clock used as RNG clock source */
+ if (LL_RCC_MSI_IsReady() != 0U)
+ {
+ rng_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ }
+ break;
+
+
+#if defined(RCC_HSI48_SUPPORT)
+ case LL_RCC_RNG_CLKSOURCE_HSI48: /* HSI48 used as RNG clock source */
+ if (LL_RCC_HSI48_IsReady() != 0U)
+ {
+ rng_frequency = HSI48_VALUE;
+ }
+ break;
+#else
+ case LL_RCC_RNG_CLKSOURCE_NONE: /* No clock used as RNG clock source */
+#endif
+ default:
+ rng_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+ break;
+
+ }
+
+ return rng_frequency;
+}
+
+
+#if defined(USB_OTG_FS)||defined(USB)
+/**
+ * @brief Return USBx clock frequency
+ * @param USBxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE
+ * @retval USB clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
+ */
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
+{
+ uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
+
+ /* USBCLK clock frequency */
+ switch (LL_RCC_GetUSBClockSource(USBxSource))
+ {
+#if defined(RCC_PLLSAI1_SUPPORT)
+ case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */
+ if (LL_RCC_PLLSAI1_IsReady() != 0U)
+ {
+ if (LL_RCC_PLLSAI1_IsEnabledDomain_48M() != 0U)
+ {
+ usb_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
+ }
+ }
+ break;
+#endif /* RCC_PLLSAI1_SUPPORT */
+
+ case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
+ if (LL_RCC_PLL_IsReady() != 0U)
+ {
+ if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
+ {
+ usb_frequency = RCC_PLL_GetFreqDomain_48M();
+ }
+ }
+ break;
+
+ case LL_RCC_USB_CLKSOURCE_MSI: /* MSI clock used as USB clock source */
+ if (LL_RCC_MSI_IsReady() != 0U)
+ {
+ usb_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ }
+ break;
+
+#if defined(RCC_HSI48_SUPPORT)
+ case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 used as USB clock source */
+ if (LL_RCC_HSI48_IsReady() != 0U)
+ {
+ usb_frequency = HSI48_VALUE;
+ }
+ break;
+#else
+ case LL_RCC_USB_CLKSOURCE_NONE: /* No clock used as USB clock source */
+#endif
+ default:
+ usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+ break;
+ }
+
+ return usb_frequency;
+}
+#endif /* USB_OTG_FS || USB */
+
+/**
+ * @brief Return ADCx clock frequency
+ * @param ADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSOURCE
+ * @retval ADC clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
+ */
+uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
+{
+ uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
+
+ /* ADCCLK clock frequency */
+ switch (LL_RCC_GetADCClockSource(ADCxSource))
+ {
+#if defined(RCC_PLLSAI1_SUPPORT)
+ case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */
+ if (LL_RCC_PLLSAI1_IsReady() != 0U)
+ {
+ if (LL_RCC_PLLSAI1_IsEnabledDomain_ADC() != 0U)
+ {
+ adc_frequency = RCC_PLLSAI1_GetFreqDomain_ADC();
+ }
+ }
+ break;
+#endif /* RCC_PLLSAI1_SUPPORT */
+
+#if defined(RCC_PLLSAI2_SUPPORT) && defined(LL_RCC_ADC_CLKSOURCE_PLLSAI2)
+ case LL_RCC_ADC_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as ADC clock source */
+ if (LL_RCC_PLLSAI2_IsReady() != 0U)
+ {
+ if (LL_RCC_PLLSAI2_IsEnabledDomain_ADC() != 0U)
+ {
+ adc_frequency = RCC_PLLSAI2_GetFreqDomain_ADC();
+ }
+ }
+ break;
+#endif /* RCC_PLLSAI2_SUPPORT && LL_RCC_ADC_CLKSOURCE_PLLSAI2 */
+
+ case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */
+ adc_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_ADC_CLKSOURCE_NONE: /* No clock used as ADC clock source */
+ default:
+ adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+ break;
+ }
+
+ return adc_frequency;
+}
+
+#if defined(SWPMI1)
+/**
+ * @brief Return SWPMIx clock frequency
+ * @param SWPMIxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SWPMI1_CLKSOURCE
+ * @retval SWPMI clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) is not ready
+ */
+uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource)
+{
+ uint32_t swpmi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_SWPMI_CLKSOURCE(SWPMIxSource));
+
+ /* SWPMI1CLK clock frequency */
+ switch (LL_RCC_GetSWPMIClockSource(SWPMIxSource))
+ {
+ case LL_RCC_SWPMI1_CLKSOURCE_HSI: /* SWPMI1 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady())
+ {
+ swpmi_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_SWPMI1_CLKSOURCE_PCLK1: /* SWPMI1 Clock is PCLK1 */
+ swpmi_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ break;
+ }
+
+ return swpmi_frequency;
+}
+#endif /* SWPMI1 */
+
+#if defined(DFSDM1_Channel0)
+/**
+ * @brief Return DFSDMx clock frequency
+ * @param DFSDMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
+ * @retval DFSDM clock frequency (in Hz)
+ */
+uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
+{
+ uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
+
+ /* DFSDM1CLK clock frequency */
+ switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
+ {
+ case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */
+ dfsdm_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */
+ dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+
+ default:
+ break;
+ }
+
+ return dfsdm_frequency;
+}
+
+#if defined(RCC_CCIPR2_DFSDM1SEL)
+/**
+ * @brief Return DFSDMx Audio clock frequency
+ * @param DFSDMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
+ * @retval DFSDM clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+ */
+uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
+{
+ uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
+
+ /* DFSDM1CLK clock frequency */
+ switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
+ {
+ case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1: /* SAI1 clock used as DFSDM1 audio clock */
+ dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE);
+ break;
+
+ case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI: /* MSI clock used as DFSDM1 audio clock */
+ if (LL_RCC_MSI_IsReady() != 0U)
+ {
+ dfsdm_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ }
+ break;
+
+ case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI: /* HSI clock used as DFSDM1 audio clock */
+ default:
+ if (LL_RCC_HSI_IsReady() != 0U)
+ {
+ dfsdm_frequency = HSI_VALUE;
+ }
+ break;
+ }
+
+ return dfsdm_frequency;
+}
+#endif /* RCC_CCIPR2_DFSDM1SEL */
+#endif /* DFSDM1_Channel0 */
+
+#if defined(DSI)
+/**
+ * @brief Return DSI clock frequency
+ * @param DSIxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_DSI_CLKSOURCE
+ * @retval DSI clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
+ */
+uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
+{
+ uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
+
+ /* DSICLK clock frequency */
+ switch (LL_RCC_GetDSIClockSource(DSIxSource))
+ {
+ case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLLSAI2 Osc. */
+ if (LL_RCC_PLLSAI2_IsReady() != 0U)
+ {
+ if (LL_RCC_PLLSAI2_IsEnabledDomain_DSI() != 0U)
+ {
+ dsi_frequency = RCC_PLLSAI2_GetFreqDomain_DSI();
+ }
+ }
+ break;
+
+ case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */
+ default:
+ dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+ break;
+ }
+
+ return dsi_frequency;
+}
+#endif /* DSI */
+
+#if defined(LTDC)
+/**
+ * @brief Return LTDC clock frequency
+ * @param LTDCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LTDC_CLKSOURCE
+ * @retval LTDC clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
+ */
+uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
+{
+ uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
+
+ if (LL_RCC_PLLSAI2_IsReady() != 0U)
+ {
+ if (LL_RCC_PLLSAI2_IsEnabledDomain_LTDC() != 0U)
+ {
+ ltdc_frequency = RCC_PLLSAI2_GetFreqDomain_LTDC();
+ }
+ }
+
+ return ltdc_frequency;
+}
+#endif /* LTDC */
+
+#if defined(OCTOSPI1)
+/**
+ * @brief Return OCTOSPI clock frequency
+ * @param OCTOSPIxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
+ * @retval OCTOSPI clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
+ */
+uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource)
+{
+ uint32_t octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_OCTOSPI_CLKSOURCE(OCTOSPIxSource));
+
+ /* OCTOSPI clock frequency */
+ switch (LL_RCC_GetOCTOSPIClockSource(OCTOSPIxSource))
+ {
+ case LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK: /* OCTOSPI clock is SYSCLK */
+ octospi_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_OCTOSPI_CLKSOURCE_MSI: /* MSI clock used as OCTOSPI clock */
+ if (LL_RCC_MSI_IsReady() != 0U)
+ {
+ octospi_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ }
+ break;
+
+ case LL_RCC_OCTOSPI_CLKSOURCE_PLL: /* PLL clock used as OCTOSPI source */
+ if (LL_RCC_PLL_IsReady() != 0U)
+ {
+ if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
+ {
+ octospi_frequency = RCC_PLL_GetFreqDomain_48M();
+ }
+ }
+ break;
+
+ default:
+ octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ break;
+ }
+
+ return octospi_frequency;
+}
+#endif /* OCTOSPI1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_LL_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Return SYSTEM clock frequency
+ * @retval SYSTEM clock frequency (in Hz)
+ */
+static uint32_t RCC_GetSystemClockFreq(void)
+{
+ uint32_t frequency;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (LL_RCC_GetSysClkSource())
+ {
+ case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
+ frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
+ frequency = HSI_VALUE;
+ break;
+
+ case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
+ frequency = HSE_VALUE;
+ break;
+
+ case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
+ frequency = RCC_PLL_GetFreqDomain_SYS();
+ break;
+
+ default:
+ frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+ }
+
+ return frequency;
+}
+
+/**
+ * @brief Return HCLK clock frequency
+ * @param SYSCLK_Frequency SYSCLK clock frequency
+ * @retval HCLK clock frequency (in Hz)
+ */
+static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+{
+ /* HCLK clock frequency */
+ return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
+}
+
+/**
+ * @brief Return PCLK1 clock frequency
+ * @param HCLK_Frequency HCLK clock frequency
+ * @retval PCLK1 clock frequency (in Hz)
+ */
+static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+{
+ /* PCLK1 clock frequency */
+ return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
+}
+
+/**
+ * @brief Return PCLK2 clock frequency
+ * @param HCLK_Frequency HCLK clock frequency
+ * @retval PCLK2 clock frequency (in Hz)
+ */
+static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
+{
+ /* PCLK2 clock frequency */
+ return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
+}
+
+/**
+ * @brief Return PLL clock frequency used for system domain
+ * @retval PLL clock frequency (in Hz)
+ */
+static uint32_t RCC_PLL_GetFreqDomain_SYS(void)
+{
+ uint32_t pllinputfreq, pllsource;
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ pllinputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+ }
+ return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
+}
+
+#if defined(SAI1)
+/**
+ * @brief Return PLL clock frequency used for SAI domain
+ * @retval PLL clock frequency (in Hz)
+ */
+static uint32_t RCC_PLL_GetFreqDomain_SAI(void)
+{
+ uint32_t pllinputfreq, pllsource;
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE / PLLM) * PLLN
+ SAI Domain clock = PLL_VCO / PLLP
+ */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ pllinputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+ }
+ return __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
+}
+#endif /* SAI1 */
+
+/**
+ * @brief Return PLL clock frequency used for 48 MHz domain
+ * @retval PLL clock frequency (in Hz)
+ */
+static uint32_t RCC_PLL_GetFreqDomain_48M(void)
+{
+ uint32_t pllinputfreq, pllsource;
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+ 48M Domain clock = PLL_VCO / PLLQ
+ */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ pllinputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+ }
+ return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
+}
+#if defined(DSI)
+/**
+ * @brief Return PLL clock frequency used for DSI clock
+ * @retval PLL clock frequency (in Hz)
+ */
+static uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void)
+{
+ uint32_t pllinputfreq, pllsource;
+
+ /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */
+ /* DSICLK = PLLSAI2_VCO / PLLSAI2R */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
+ pllinputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+ }
+
+ return __LL_RCC_CALC_PLLSAI2_DSI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),
+ LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR());
+}
+#endif /* DSI */
+
+#if defined(RCC_PLLSAI1_SUPPORT)
+/**
+ * @brief Return PLLSAI1 clock frequency used for SAI domain
+ * @retval PLLSAI1 clock frequency (in Hz)
+ */
+static uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void)
+{
+ uint32_t pllinputfreq, pllsource;
+
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
+ /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */
+#else
+ /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
+#endif
+ /* SAI Domain clock = PLLSAI1_VCO / PLLSAI1P */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
+ pllinputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+ }
+ return __LL_RCC_CALC_PLLSAI1_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetP());
+}
+
+/**
+ * @brief Return PLLSAI1 clock frequency used for 48Mhz domain
+ * @retval PLLSAI1 clock frequency (in Hz)
+ */
+static uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void)
+{
+ uint32_t pllinputfreq, pllsource;
+
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
+ /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */
+#else
+ /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
+#endif
+ /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1Q */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
+ pllinputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+ }
+ return __LL_RCC_CALC_PLLSAI1_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ());
+}
+
+/**
+ * @brief Return PLLSAI1 clock frequency used for ADC domain
+ * @retval PLLSAI1 clock frequency (in Hz)
+ */
+static uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void)
+{
+ uint32_t pllinputfreq, pllsource;
+
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
+ /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */
+#else
+ /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
+#endif
+ /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1R */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
+ pllinputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+ }
+ return __LL_RCC_CALC_PLLSAI1_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR());
+}
+#endif /* RCC_PLLSAI1_SUPPORT */
+
+#if defined(RCC_PLLSAI2_SUPPORT)
+/**
+ * @brief Return PLLSAI2 clock frequency used for SAI domain
+ * @retval PLLSAI2 clock frequency (in Hz)
+ */
+static uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void)
+{
+ uint32_t pllinputfreq, pllsource;
+
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
+ /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */
+#else
+ /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */
+#endif
+ /* SAI Domain clock = PLLSAI2_VCO / PLLSAI2P */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
+ pllinputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+ }
+#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
+ return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),
+ LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP());
+#else
+ return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP());
+#endif
+}
+
+#if defined(LTDC)
+/**
+ * @brief Return PLLSAI2 clock frequency used for LTDC domain
+ * @retval PLLSAI2 clock frequency (in Hz)
+ */
+static uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void)
+{
+ uint32_t pllinputfreq, pllsource;
+
+ /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */
+ /* LTDC Domain clock = (PLLSAI2_VCO / PLLSAI2R) / PLLSAI2DIVR */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
+ pllinputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+ }
+
+ return __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),
+ LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR(), LL_RCC_PLLSAI2_GetDIVR());
+}
+
+#else
+
+ /**
+ * @brief Return PLLSAI2 clock frequency used for ADC domain
+ * @retval PLLSAI2 clock frequency (in Hz)
+ */
+static uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void)
+{
+ uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+ /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */
+ /* 48M Domain clock = PLLSAI2_VCO / PLLSAI2R */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
+ pllinputfreq = HSI_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ default:
+ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
+ ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
+ LL_RCC_MSI_GetRange() :
+ LL_RCC_MSI_GetRangeAfterStandby()));
+ break;
+ }
+ return __LL_RCC_CALC_PLLSAI2_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR());
+}
+#endif /* LTDC */
+
+#endif /*RCC_PLLSAI2_SUPPORT*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RCC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_spi.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_spi.c
new file mode 100644
index 0000000..89cc53f
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_spi.c
@@ -0,0 +1,295 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_spi.c
+ * @author MCD Application Team
+ * @brief SPI LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_spi.h"
+#include "stm32l4xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined (SPI1) || defined (SPI2) || defined (SPI3)
+
+/** @addtogroup SPI_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Constants SPI Private Constants
+ * @{
+ */
+/* SPI registers Masks */
+#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
+ SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
+ SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
+ SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
+ SPI_CR1_BIDIMODE)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Macros SPI Private Macros
+ * @{
+ */
+#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
+ || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
+ || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
+ || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
+
+#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
+ || ((__VALUE__) == LL_SPI_MODE_SLAVE))
+
+#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
+
+#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
+ || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
+
+#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
+ || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
+
+#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
+ || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
+ || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
+
+#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
+
+#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
+ || ((__VALUE__) == LL_SPI_MSB_FIRST))
+
+#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
+ || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
+
+#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SPI_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the SPI registers to their default reset values.
+ * @param SPIx SPI Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are de-initialized
+ * - ERROR: SPI registers are not de-initialized
+ */
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+#if defined(SPI1)
+ if (SPIx == SPI1)
+ {
+ /* Force reset of SPI clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+ /* Release reset of SPI clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+ status = SUCCESS;
+ }
+#endif /* SPI1 */
+#if defined(SPI2)
+ if (SPIx == SPI2)
+ {
+ /* Force reset of SPI clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+ /* Release reset of SPI clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+ status = SUCCESS;
+ }
+#endif /* SPI2 */
+#if defined(SPI3)
+ if (SPIx == SPI3)
+ {
+ /* Force reset of SPI clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+ /* Release reset of SPI clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+ status = SUCCESS;
+ }
+#endif /* SPI3 */
+
+ return status;
+}
+
+/**
+ * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
+ * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+ * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @param SPIx SPI Instance
+ * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
+ */
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the SPI Instance SPIx*/
+ assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+ /* Check the SPI parameters from SPI_InitStruct*/
+ assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
+ assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
+ assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
+ assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
+ assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
+ assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
+ assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
+ assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
+ assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
+
+ if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
+ {
+ /*---------------------------- SPIx CR1 Configuration ------------------------
+ * Configure SPIx CR1 with parameters:
+ * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
+ * - Master/Slave Mode: SPI_CR1_MSTR bit
+ * - ClockPolarity: SPI_CR1_CPOL bit
+ * - ClockPhase: SPI_CR1_CPHA bit
+ * - NSS management: SPI_CR1_SSM bit
+ * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
+ * - BitOrder: SPI_CR1_LSBFIRST bit
+ * - CRCCalculation: SPI_CR1_CRCEN bit
+ */
+ MODIFY_REG(SPIx->CR1,
+ SPI_CR1_CLEAR_MASK,
+ SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
+ SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
+ SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
+ SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
+
+ /*---------------------------- SPIx CR2 Configuration ------------------------
+ * Configure SPIx CR2 with parameters:
+ * - DataWidth: DS[3:0] bits
+ * - NSS management: SSOE bit
+ */
+ MODIFY_REG(SPIx->CR2,
+ SPI_CR2_DS | SPI_CR2_SSOE,
+ SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
+
+ /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
+ if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
+ {
+ LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
+ }
+
+ /*---------------------------- SPIx CRCPR Configuration ----------------------
+ * Configure SPIx CRCPR with parameters:
+ * - CRCPoly: CRCPOLY[15:0] bits
+ */
+ if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
+ {
+ assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
+ LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
+ }
+ status = SUCCESS;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
+ * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+ /* Set SPI_InitStruct fields to default values */
+ SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
+ SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
+ SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
+ SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
+ SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
+ SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
+ SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
+ SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
+ SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ SPI_InitStruct->CRCPoly = 7U;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c
new file mode 100644
index 0000000..eb87565
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c
@@ -0,0 +1,1360 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_tim.c
+ * @author MCD Application Team
+ * @brief TIM LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_tim.h"
+#include "stm32l4xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
+
+/** @addtogroup TIM_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup TIM_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
+
+#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
+
+#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
+ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
+ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
+
+#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
+
+#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
+ || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
+
+#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
+ || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
+
+#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
+
+#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
+
+#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
+
+#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
+
+#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
+
+#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
+
+#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
+
+#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
+
+#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
+ || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
+
+#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
+ || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
+
+#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
+ || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
+
+#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
+ || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
+
+#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
+ || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup TIM_LL_Private_Functions TIM Private Functions
+ * @{
+ */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TIM_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Set TIMx registers to their reset values.
+ * @param TIMx Timer instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: invalid TIMx instance
+ */
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
+{
+ ErrorStatus result = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(TIMx));
+
+ if (TIMx == TIM1)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
+ }
+ else if (TIMx == TIM2)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
+ }
+#if defined(TIM3)
+ else if (TIMx == TIM3)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
+ }
+#endif /* TIM3 */
+#if defined(TIM4)
+ else if (TIMx == TIM4)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
+ }
+#endif /* TIM4 */
+#if defined(TIM5)
+ else if (TIMx == TIM5)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
+ }
+#endif /* TIM5 */
+ else if (TIMx == TIM6)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
+ }
+#if defined (TIM7)
+ else if (TIMx == TIM7)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
+ }
+#endif /* TIM7 */
+#if defined(TIM8)
+ else if (TIMx == TIM8)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
+ }
+#endif /* TIM8 */
+ else if (TIMx == TIM15)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
+ }
+ else if (TIMx == TIM16)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
+ }
+#if defined(TIM17)
+ else if (TIMx == TIM17)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
+ }
+#endif /* TIM17 */
+ else
+ {
+ result = ERROR;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Set the fields of the time base unit configuration data structure
+ * to their default values.
+ * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
+ * @retval None
+ */
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+ /* Set the default configuration */
+ TIM_InitStruct->Prescaler = (uint16_t)0x0000;
+ TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
+ TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
+ TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
+ TIM_InitStruct->RepetitionCounter = 0x00000000U;
+}
+
+/**
+ * @brief Configure the TIMx time base unit.
+ * @param TIMx Timer Instance
+ * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
+ * (TIMx time base unit configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+ uint32_t tmpcr1;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
+ assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
+
+ tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
+
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ {
+ /* Select the Counter Mode */
+ MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
+ }
+
+ if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ {
+ /* Set the clock division */
+ MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
+ }
+
+ /* Write to TIMx CR1 */
+ LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
+
+ /* Set the Autoreload value */
+ LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
+
+ /* Set the Prescaler value */
+ LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ {
+ /* Set the Repetition Counter value */
+ LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter value (if applicable) immediately */
+ LL_TIM_GenerateEvent_UPDATE(TIMx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the fields of the TIMx output channel configuration data
+ * structure to their default values.
+ * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
+ * (the output channel configuration data structure)
+ * @retval None
+ */
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+ /* Set the default configuration */
+ TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
+ TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
+ TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
+ TIM_OC_InitStruct->CompareValue = 0x00000000U;
+ TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
+ TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
+ TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
+ TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
+}
+
+/**
+ * @brief Configure the TIMx output channel.
+ * @param TIMx Timer Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
+ * data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx output channel is initialized
+ * - ERROR: TIMx output channel is not initialized
+ */
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+ ErrorStatus result = ERROR;
+
+ switch (Channel)
+ {
+ case LL_TIM_CHANNEL_CH1:
+ result = OC1Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH2:
+ result = OC2Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH3:
+ result = OC3Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH4:
+ result = OC4Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH5:
+ result = OC5Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH6:
+ result = OC6Config(TIMx, TIM_OC_InitStruct);
+ break;
+ default:
+ break;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Set the fields of the TIMx input channel configuration data
+ * structure to their default values.
+ * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
+ * data structure)
+ * @retval None
+ */
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Set the default configuration */
+ TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
+ TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+ * @brief Configure the TIMx input channel.
+ * @param TIMx Timer Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
+ * structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx output channel is initialized
+ * - ERROR: TIMx output channel is not initialized
+ */
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
+{
+ ErrorStatus result = ERROR;
+
+ switch (Channel)
+ {
+ case LL_TIM_CHANNEL_CH1:
+ result = IC1Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH2:
+ result = IC2Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH3:
+ result = IC3Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH4:
+ result = IC4Config(TIMx, TIM_IC_InitStruct);
+ break;
+ default:
+ break;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Fills each TIM_EncoderInitStruct field with its default value
+ * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
+ * configuration data structure)
+ * @retval None
+ */
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+ /* Set the default configuration */
+ TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
+ TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
+ TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+ * @brief Configure the encoder interface of the timer instance.
+ * @param TIMx Timer Instance
+ * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
+ * configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
+
+ /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+ TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Configure TI1 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
+
+ /* Configure TI2 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
+
+ /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
+ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
+ tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
+ tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Set encoder mode */
+ LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the fields of the TIMx Hall sensor interface configuration data
+ * structure to their default values.
+ * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
+ * configuration data structure)
+ * @retval None
+ */
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+ /* Set the default configuration */
+ TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
+ TIM_HallSensorInitStruct->CommutationDelay = 0U;
+}
+
+/**
+ * @brief Configure the Hall sensor interface of the timer instance.
+ * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
+ * to the TI1 input channel
+ * @note TIMx slave mode controller is configured in reset mode.
+ Selected internal trigger is TI1F_ED.
+ * @note Channel 1 is configured as input, IC1 is mapped on TRC.
+ * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
+ * between 2 changes on the inputs. It gives information about motor speed.
+ * @note Channel 2 is configured in output PWM 2 mode.
+ * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
+ * @note OC2REF is selected as trigger output on TRGO.
+ * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
+ * when TIMx operates in Hall sensor interface mode.
+ * @param TIMx Timer Instance
+ * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
+ * interface configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+ uint32_t tmpcr2;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
+ assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
+
+ /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+ TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
+
+ /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
+ tmpcr2 |= TIM_CR2_TI1S;
+
+ /* OC2REF signal is used as trigger output (TRGO) */
+ tmpcr2 |= LL_TIM_TRGO_OC2REF;
+
+ /* Configure the slave mode controller */
+ tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
+ tmpsmcr |= LL_TIM_TS_TI1F_ED;
+ tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
+
+ /* Configure input channel 1 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
+ tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
+
+ /* Configure input channel 2 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
+ tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
+
+ /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
+ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
+ tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx SMCR */
+ LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ /* Write to TIMx CCR2 */
+ LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the fields of the Break and Dead Time configuration data structure
+ * to their default values.
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
+ * data structure)
+ * @retval None
+ */
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+ /* Set the default configuration */
+ TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
+ TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
+ TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
+ TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
+ TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
+ TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
+ TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
+ TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
+ TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
+ TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
+ TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
+}
+
+/**
+ * @brief Configure the Break and Dead Time feature of the timer instance.
+ * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
+ * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
+ * can be necessary to configure all of them during the first write access to
+ * the TIMx_BDTR register.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @param TIMx Timer Instance
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
+ * data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Break and Dead Time is initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+ uint32_t tmpbdtr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
+ assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
+ assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
+ assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
+ assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
+ assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+ /* Set the BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
+ if (IS_TIM_ADVANCED_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
+ }
+
+ if (IS_TIM_BKIN2_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
+ assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
+ assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
+
+ /* Set the BREAK2 input related BDTR bit-fields */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
+ }
+
+ /* Set TIMx_BDTR */
+ LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
+
+ return SUCCESS;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
+ * @brief Private functions
+ * @{
+ */
+/**
+ * @brief Configure the TIMx output channel 1.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
+
+ /* Set the Output Compare Mode */
+ MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 2.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 3.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR2 */
+ LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 4.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR2 */
+ LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 5.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr3;
+ uint32_t tmpccer;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC5_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+ /* Disable the Channel 5: Reset the CC5E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CCMR3 register value */
+ tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the Output Idle state */
+ MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
+
+ }
+
+ /* Write to TIMx CCMR3 */
+ LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 6.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr3;
+ uint32_t tmpccer;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC6_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+ /* Disable the Channel 5: Reset the CC6E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CCMR3 register value */
+ tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the Output Idle state */
+ MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
+ }
+
+ /* Write to TIMx CCMR3 */
+ LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 1.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR1,
+ (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+ /* Select the Polarity and set the CC1E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC1P | TIM_CCER_CC1NP),
+ (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 2.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR1,
+ (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+ /* Select the Polarity and set the CC2E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC2P | TIM_CCER_CC2NP),
+ ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 3.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR2,
+ (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+ /* Select the Polarity and set the CC3E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC3P | TIM_CCER_CC3NP),
+ ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 4.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR2,
+ (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+ /* Select the Polarity and set the CC2E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC4P | TIM_CCER_CC4NP),
+ ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
+
+ return SUCCESS;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usart.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usart.c
new file mode 100644
index 0000000..90f603f
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usart.c
@@ -0,0 +1,476 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_usart.c
+ * @author MCD Application Team
+ * @brief USART LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_usart.h"
+#include "stm32l4xx_ll_rcc.h"
+#include "stm32l4xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
+
+/** @addtogroup USART_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Macros
+ * @{
+ */
+
+#if defined(USART_PRESC_PRESCALER)
+#define IS_LL_USART_PRESCALER(__VALUE__) (((__VALUE__) == LL_USART_PRESCALER_DIV1) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
+ || ((__VALUE__) == LL_USART_PRESCALER_DIV256))
+
+#endif /* USART_PRESC_PRESCALER */
+/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
+ * divided by the smallest oversampling used on the USART (i.e. 8) */
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 15000000U)
+#else
+#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
+
+/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
+#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
+
+#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
+ || ((__VALUE__) == LL_USART_DIRECTION_RX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
+
+#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
+ || ((__VALUE__) == LL_USART_PARITY_EVEN) \
+ || ((__VALUE__) == LL_USART_PARITY_ODD))
+
+#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
+ || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+ || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+
+#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
+ || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
+
+#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
+ || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
+
+#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
+ || ((__VALUE__) == LL_USART_PHASE_2EDGE))
+
+#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
+ || ((__VALUE__) == LL_USART_POLARITY_HIGH))
+
+#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
+ || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
+
+#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
+ || ((__VALUE__) == LL_USART_STOPBITS_1) \
+ || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
+ || ((__VALUE__) == LL_USART_STOPBITS_2))
+
+#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup USART_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize USART registers (Registers restored to their default values).
+ * @param USARTx USART Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers are de-initialized
+ * - ERROR: USART registers are not de-initialized
+ */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+
+ if (USARTx == USART1)
+ {
+ /* Force reset of USART clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
+
+ /* Release reset of USART clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
+ }
+ else if (USARTx == USART2)
+ {
+ /* Force reset of USART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
+
+ /* Release reset of USART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
+ }
+#if defined(USART3)
+ else if (USARTx == USART3)
+ {
+ /* Force reset of USART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
+
+ /* Release reset of USART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
+ }
+#endif /* USART3 */
+#if defined(UART4)
+ else if (USARTx == UART4)
+ {
+ /* Force reset of UART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
+
+ /* Release reset of UART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
+ }
+#endif /* UART4 */
+#if defined(UART5)
+ else if (USARTx == UART5)
+ {
+ /* Force reset of UART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
+
+ /* Release reset of UART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
+ }
+#endif /* UART5 */
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize USART registers according to the specified
+ * parameters in USART_InitStruct.
+ * @note As some bits in USART configuration registers can only be written when
+ * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+ * this function. Otherwise, ERROR result will be returned.
+ * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
+ * @param USARTx USART Instance
+ * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
+ * that contains the configuration information for the specified USART peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers are initialized according to USART_InitStruct content
+ * - ERROR: Problem occurred during USART Registers initialization
+ */
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
+{
+ ErrorStatus status = ERROR;
+ uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+#if defined(USART_PRESC_PRESCALER)
+ assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue));
+#endif /* USART_PRESC_PRESCALER */
+ assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
+ assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
+ assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
+ assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
+ assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
+ assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
+ assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
+
+ /* USART needs to be in disabled state, in order to be able to configure some bits in
+ CRx registers */
+ if (LL_USART_IsEnabled(USARTx) == 0U)
+ {
+ /*---------------------------- USART CR1 Configuration ---------------------
+ * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
+ * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
+ * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
+ * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
+ * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
+ */
+ MODIFY_REG(USARTx->CR1,
+ (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+ (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
+ USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
+
+ /*---------------------------- USART CR2 Configuration ---------------------
+ * Configure USARTx CR2 (Stop bits) with parameters:
+ * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
+ * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
+ */
+ LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
+
+ /*---------------------------- USART CR3 Configuration ---------------------
+ * Configure USARTx CR3 (Hardware Flow Control) with parameters:
+ * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
+ * USART_InitStruct->HardwareFlowControl value.
+ */
+ LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
+
+ /*---------------------------- USART BRR Configuration ---------------------
+ * Retrieve Clock frequency used for USART Peripheral
+ */
+ if (USARTx == USART1)
+ {
+ periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
+ }
+ else if (USARTx == USART2)
+ {
+ periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
+ }
+#if defined(USART3)
+ else if (USARTx == USART3)
+ {
+ periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
+ }
+#endif /* USART3 */
+#if defined(UART4)
+ else if (USARTx == UART4)
+ {
+ periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
+ }
+#endif /* UART4 */
+#if defined(UART5)
+ else if (USARTx == UART5)
+ {
+ periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE);
+ }
+#endif /* UART5 */
+ else
+ {
+ /* Nothing to do, as error code is already assigned to ERROR value */
+ }
+
+ /* Configure the USART Baud Rate :
+#if defined(USART_PRESC_PRESCALER)
+ - prescaler value is required
+#endif
+ - valid baud rate value (different from 0) is required
+ - Peripheral clock as returned by RCC service, should be valid (different from 0).
+ */
+ if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+ && (USART_InitStruct->BaudRate != 0U))
+ {
+ status = SUCCESS;
+ LL_USART_SetBaudRate(USARTx,
+ periphclk,
+#if defined(USART_PRESC_PRESCALER)
+ USART_InitStruct->PrescalerValue,
+#endif /* USART_PRESC_PRESCALER */
+ USART_InitStruct->OverSampling,
+ USART_InitStruct->BaudRate);
+
+ /* Check BRR is greater than or equal to 16d */
+ assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
+ }
+#if defined(USART_PRESC_PRESCALER)
+
+ /*---------------------------- USART PRESC Configuration -----------------------
+ * Configure USARTx PRESC (Prescaler) with parameters:
+ * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value.
+ */
+ LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue);
+#endif /* USART_PRESC_PRESCALER */
+ }
+ /* Endif (=> USART not in Disabled state => return ERROR) */
+
+ return (status);
+}
+
+/**
+ * @brief Set each @ref LL_USART_InitTypeDef field to default value.
+ * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
+{
+ /* Set USART_InitStruct fields to default values */
+#if defined(USART_PRESC_PRESCALER)
+ USART_InitStruct->PrescalerValue = LL_USART_PRESCALER_DIV1;
+#endif /* USART_PRESC_PRESCALER */
+ USART_InitStruct->BaudRate = 9600U;
+ USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
+ USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
+ USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
+ USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
+ USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+ USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
+}
+
+/**
+ * @brief Initialize USART Clock related settings according to the
+ * specified parameters in the USART_ClockInitStruct.
+ * @note As some bits in USART configuration registers can only be written when
+ * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+ * this function. Otherwise, ERROR result will be returned.
+ * @param USARTx USART Instance
+ * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * that contains the Clock configuration information for the specified USART peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers related to Clock settings are initialized according
+ * to USART_ClockInitStruct content
+ * - ERROR: Problem occurred during USART Registers initialization
+ */
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check USART Instance and Clock signal output parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+ assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
+
+ /* USART needs to be in disabled state, in order to be able to configure some bits in
+ CRx registers */
+ if (LL_USART_IsEnabled(USARTx) == 0U)
+ {
+#if defined(USART_CR2_SLVEN)
+ /* Ensure USART instance is USART capable */
+ assert_param(IS_USART_INSTANCE(USARTx));
+
+ /* Check clock related parameters */
+ assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+ assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+ assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+
+ /*---------------------------- USART CR2 Configuration -----------------------
+ * Configure USARTx CR2 (Clock signal related bits) with parameters:
+ * - Clock Output: USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value
+ * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
+ * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
+ * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
+ */
+ MODIFY_REG(USARTx->CR2,
+ USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+ USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity |
+ USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
+#else
+ /* If USART Clock signal is disabled */
+ if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
+ {
+ /* Deactivate Clock signal delivery :
+ * - Disable Clock Output: USART_CR2_CLKEN cleared
+ */
+ LL_USART_DisableSCLKOutput(USARTx);
+ }
+ else
+ {
+ /* Ensure USART instance is USART capable */
+ assert_param(IS_USART_INSTANCE(USARTx));
+
+ /* Check clock related parameters */
+ assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+ assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+ assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+
+ /*---------------------------- USART CR2 Configuration -----------------------
+ * Configure USARTx CR2 (Clock signal related bits) with parameters:
+ * - Enable Clock Output: USART_CR2_CLKEN set
+ * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
+ * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
+ * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
+ */
+ MODIFY_REG(USARTx->CR2,
+ USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+ USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
+ USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
+ }
+#endif /* USART_CR2_SLVEN */
+ }
+ /* Else (USART not in Disabled state => return ERROR */
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
+ * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+ /* Set LL_USART_ClockInitStruct fields with default values */
+ USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
+ USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+
diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c
new file mode 100644
index 0000000..5375be8
--- /dev/null
+++ b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c
@@ -0,0 +1,913 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_ll_utils.c
+ * @author MCD Application Team
+ * @brief UTILS LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_utils.h"
+#include "stm32l4xx_ll_rcc.h"
+#include "stm32l4xx_ll_system.h"
+#include "stm32l4xx_ll_pwr.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32L4xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup UTILS_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Constants
+ * @{
+ */
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define UTILS_MAX_FREQUENCY_SCALE1 120000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE2 26000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
+#else
+#define UTILS_MAX_FREQUENCY_SCALE1 80000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE2 26000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
+#endif
+
+/* Defines used for PLL range */
+#define UTILS_PLLVCO_INPUT_MIN 4000000U /*!< Frequency min for PLLVCO input, in Hz */
+#define UTILS_PLLVCO_INPUT_MAX 16000000U /*!< Frequency max for PLLVCO input, in Hz */
+#define UTILS_PLLVCO_OUTPUT_MIN 64000000U /*!< Frequency min for PLLVCO output, in Hz */
+#define UTILS_PLLVCO_OUTPUT_MAX 344000000U /*!< Frequency max for PLLVCO output, in Hz */
+
+/* Defines used for HSE range */
+#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
+#define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */
+
+/* Defines used for FLASH latency according to HCLK Frequency */
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define UTILS_SCALE1_LATENCY1_FREQ 20000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define UTILS_SCALE1_LATENCY2_FREQ 40000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#define UTILS_SCALE1_LATENCY3_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
+#define UTILS_SCALE1_LATENCY4_FREQ 80000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
+#define UTILS_SCALE1_LATENCY5_FREQ 100000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
+#define UTILS_SCALE2_LATENCY1_FREQ 8000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define UTILS_SCALE2_LATENCY2_FREQ 16000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+#else
+#define UTILS_SCALE1_LATENCY1_FREQ 16000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define UTILS_SCALE1_LATENCY2_FREQ 32000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#define UTILS_SCALE1_LATENCY3_FREQ 48000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
+#define UTILS_SCALE1_LATENCY4_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
+#define UTILS_SCALE2_LATENCY1_FREQ 6000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define UTILS_SCALE2_LATENCY2_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+#define UTILS_SCALE2_LATENCY3_FREQ 18000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
+#endif
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
+
+#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_16))
+
+#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_16))
+
+#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_1) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
+ || ((__VALUE__) == LL_RCC_PLLM_DIV_8))
+
+#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
+
+#define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \
+ || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \
+ || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \
+ || ((__VALUE__) == LL_RCC_PLLR_DIV_8))
+
+#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
+
+#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
+
+#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
+ ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))
+
+#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
+ || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
+
+#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
+ * @{
+ */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+static ErrorStatus UTILS_PLL_IsBusy(void);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UTILS_LL_EF_DELAY
+ * @{
+ */
+
+/**
+ * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
+ * @note When a RTOS is used, it is recommended to avoid changing the Systick
+ * configuration by calling this function, for a delay use rather osDelay RTOS service.
+ * @param HCLKFrequency HCLK frequency in Hz
+ * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
+ * @retval None
+ */
+void LL_Init1msTick(uint32_t HCLKFrequency)
+{
+ /* Use frequency provided in argument */
+ LL_InitTick(HCLKFrequency, 1000U);
+}
+
+/**
+ * @brief This function provides accurate delay (in milliseconds) based
+ * on SysTick counter flag
+ * @note When a RTOS is used, it is recommended to avoid using blocking delay
+ * and use rather osDelay service.
+ * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
+ * will configure Systick to 1ms
+ * @param Delay specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+void LL_mDelay(uint32_t Delay)
+{
+ __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
+ uint32_t tmpDelay = Delay;
+
+ /* Add this code to indicate that local variable is not used */
+ ((void)tmp);
+
+ /* Add a period to guaranty minimum wait */
+ if(tmpDelay < LL_MAX_DELAY)
+ {
+ tmpDelay++;
+ }
+
+ while (tmpDelay != 0U)
+ {
+ if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
+ {
+ tmpDelay--;
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup UTILS_EF_SYSTEM
+ * @brief System Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### System Configuration functions #####
+ ===============================================================================
+ [..]
+ System, AHB and APB buses clocks configuration
+
+ (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is
+ 120000000 Hz for STM32L4Rx/STM32L4Sx devices and 80000000 Hz for others.
+ @endverbatim
+ @internal
+ Depending on the device voltage range, the maximum frequency should be
+ adapted accordingly:
+
+ (++) Table 1. HCLK clock frequency for STM32L4+ Series devices
+ (++) +--------------------------------------------------------+
+ (++) | Latency | HCLK clock frequency (MHz) |
+ (++) | |--------------------------------------|
+ (++) | | voltage range 1 | voltage range 2 |
+ (++) | | 1.2 V | 1.0 V |
+ (++) |-----------------|-------------------|------------------|
+ (++) |0WS(1 CPU cycles)| 0 < HCLK <= 20 | 0 < HCLK <= 8 |
+ (++) |-----------------|-------------------|------------------|
+ (++) |1WS(2 CPU cycles)| 20 < HCLK <= 40 | 8 < HCLK <= 16 |
+ (++) |-----------------|-------------------|------------------|
+ (++) |2WS(3 CPU cycles)| 40 < HCLK <= 60 | 16 < HCLK <= 26 |
+ (++) |-----------------|-------------------|------------------|
+ (++) |3WS(4 CPU cycles)| 60 < HCLK <= 80 | 16 < HCLK <= 26 |
+ (++) |-----------------|-------------------|------------------|
+ (++) |4WS(5 CPU cycles)| 80 < HCLK <= 100 | 16 < HCLK <= 26 |
+ (++) |-----------------|-------------------|------------------|
+ (++) |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26 |
+ (++) +--------------------------------------------------------+
+
+ (++) Table 2. HCLK clock frequency for STM32L4 Series devices
+ (++) +-------------------------------------------------------+
+ (++) | Latency | HCLK clock frequency (MHz) |
+ (++) | |-------------------------------------|
+ (++) | | voltage range 1 | voltage range 2 |
+ (++) | | 1.2 V | 1.0 V |
+ (++) |-----------------|------------------|------------------|
+ (++) |0WS(1 CPU cycles)| 0 < HCLK <= 16 | 0 < HCLK <= 6 |
+ (++) |-----------------|------------------|------------------|
+ (++) |1WS(2 CPU cycles)| 16 < HCLK <= 32 | 6 < HCLK <= 12 |
+ (++) |-----------------|------------------|------------------|
+ (++) |2WS(3 CPU cycles)| 32 < HCLK <= 48 | 12 < HCLK <= 18 |
+ (++) |-----------------|------------------|------------------|
+ (++) |3WS(4 CPU cycles)| 48 < HCLK <= 64 | 18 < HCLK <= 26 |
+ (++) |-----------------|------------------|------------------|
+ (++) |4WS(5 CPU cycles)| 64 < HCLK <= 80 | 18 < HCLK <= 26 |
+ (++) +-------------------------------------------------------+
+
+ @endinternal
+ * @{
+ */
+
+/**
+ * @brief This function sets directly SystemCoreClock CMSIS variable.
+ * @note Variable can be calculated also through SystemCoreClockUpdate function.
+ * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+ * @retval None
+ */
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
+{
+ /* HCLK clock frequency */
+ SystemCoreClock = HCLKFrequency;
+}
+
+/**
+ * @brief Update number of Flash wait states in line with new frequency and current
+ voltage range.
+ * @param HCLKFrequency HCLK frequency
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Latency has been modified
+ * - ERROR: Latency cannot be modified
+ */
+ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency)
+{
+ ErrorStatus status = SUCCESS;
+
+ uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
+
+ /* Frequency cannot be equal to 0 or greater than max clock */
+ if ((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_MAX_FREQUENCY_SCALE1))
+ {
+ status = ERROR;
+ }
+ else
+ {
+ if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
+ {
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+ if(HCLKFrequency > UTILS_SCALE1_LATENCY5_FREQ)
+ {
+ /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */
+ latency = LL_FLASH_LATENCY_5;
+ }
+ else if(HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ)
+ {
+ /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */
+ latency = LL_FLASH_LATENCY_4;
+ }
+ else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ)
+ {
+ /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */
+ latency = LL_FLASH_LATENCY_3;
+ }
+ else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ)
+ {
+ /* 40 < HCLK <= 20 => 2WS (3 CPU cycles) */
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else
+ {
+ if(HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ)
+ {
+ /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */
+ latency = LL_FLASH_LATENCY_1;
+ }
+ /* else HCLKFrequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */
+ }
+#else
+ if(HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ)
+ {
+ /* 64 < HCLK <= 80 => 4WS (5 CPU cycles) */
+ latency = LL_FLASH_LATENCY_4;
+ }
+ else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ)
+ {
+ /* 48 < HCLK <= 64 => 3WS (4 CPU cycles) */
+ latency = LL_FLASH_LATENCY_3;
+ }
+ else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ)
+ {
+ /* 32 < HCLK <= 48 => 2WS (3 CPU cycles) */
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else
+ {
+ if(HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ)
+ {
+ /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */
+ latency = LL_FLASH_LATENCY_1;
+ }
+ /* else HCLKFrequency <= 16MHz default LL_FLASH_LATENCY_0 0WS */
+ }
+#endif
+ }
+ else /* SCALE2 */
+ {
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+ if(HCLKFrequency > UTILS_MAX_FREQUENCY_SCALE2)
+ {
+ /* Unexpected HCLK > 26 */
+ status = ERROR;
+ }
+ else if(HCLKFrequency > UTILS_SCALE2_LATENCY2_FREQ)
+ {
+ /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else
+ {
+ if(HCLKFrequency > UTILS_SCALE2_LATENCY1_FREQ)
+ {
+ /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */
+ latency = LL_FLASH_LATENCY_1;
+ }
+ /* else HCLKFrequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */
+ }
+#else
+ if(HCLKFrequency > UTILS_MAX_FREQUENCY_SCALE2)
+ {
+ /* Unexpected HCLK > 26 */
+ status = ERROR;
+ }
+ else if(HCLKFrequency > UTILS_SCALE2_LATENCY3_FREQ)
+ {
+ /* 18 < HCLK <= 26 => 3WS (4 CPU cycles) */
+ latency = LL_FLASH_LATENCY_3;
+ }
+ else if(HCLKFrequency > UTILS_SCALE2_LATENCY2_FREQ)
+ {
+ /* 12 < HCLK <= 18 => 2WS (3 CPU cycles) */
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else
+ {
+ if(HCLKFrequency > UTILS_SCALE2_LATENCY1_FREQ)
+ {
+ /* 6 < HCLK <= 12 => 1WS (2 CPU cycles) */
+ latency = LL_FLASH_LATENCY_1;
+ }
+ /* else HCLKFrequency <= 6MHz default LL_FLASH_LATENCY_0 0WS */
+ }
+#endif
+ }
+
+ LL_FLASH_SetLatency(latency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if(LL_FLASH_GetLatency() != latency)
+ {
+ status = ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief This function configures system clock with MSI as clock source of the PLL
+ * @note The application needs to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
+ * @note Function is based on the following formula:
+ * - PLL output frequency = (((MSI frequency / PLLM) * PLLN) / PLLR)
+ * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = MSI frequency / PLLM)
+ * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
+ * - PLLR: ensure that max frequency at 120000000 Hz is reached (PLLVCO_output / PLLR)
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Max frequency configuration done
+ * - ERROR: Max frequency configuration not done
+ */
+ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ uint32_t pllfreq, msi_range;
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+ uint32_t hpre = 0U; /* Set default value */
+#endif
+
+ /* Check if one of the PLL is enabled */
+ if(UTILS_PLL_IsBusy() == SUCCESS)
+ {
+ /* Get the current MSI range */
+ if(LL_RCC_MSI_IsEnabledRangeSelect() != 0U)
+ {
+ msi_range = LL_RCC_MSI_GetRange();
+ switch (msi_range)
+ {
+ case LL_RCC_MSIRANGE_0: /* MSI = 100 KHz */
+ case LL_RCC_MSIRANGE_1: /* MSI = 200 KHz */
+ case LL_RCC_MSIRANGE_2: /* MSI = 400 KHz */
+ case LL_RCC_MSIRANGE_3: /* MSI = 800 KHz */
+ case LL_RCC_MSIRANGE_4: /* MSI = 1 MHz */
+ case LL_RCC_MSIRANGE_5: /* MSI = 2 MHz */
+ /* PLLVCO input frequency is not in the range from 4 to 16 MHz*/
+ status = ERROR;
+ break;
+
+ case LL_RCC_MSIRANGE_6: /* MSI = 4 MHz */
+ case LL_RCC_MSIRANGE_7: /* MSI = 8 MHz */
+ case LL_RCC_MSIRANGE_8: /* MSI = 16 MHz */
+ case LL_RCC_MSIRANGE_9: /* MSI = 24 MHz */
+ case LL_RCC_MSIRANGE_10: /* MSI = 32 MHz */
+ case LL_RCC_MSIRANGE_11: /* MSI = 48 MHz */
+ default:
+ break;
+ }
+ }
+ else
+ {
+ msi_range = LL_RCC_MSI_GetRangeAfterStandby();
+ switch (msi_range)
+ {
+ case LL_RCC_MSISRANGE_4: /* MSI = 1 MHz */
+ case LL_RCC_MSISRANGE_5: /* MSI = 2 MHz */
+ /* PLLVCO input frequency is not in the range from 4 to 16 MHz*/
+ status = ERROR;
+ break;
+
+ case LL_RCC_MSISRANGE_7: /* MSI = 8 MHz */
+ case LL_RCC_MSISRANGE_6: /* MSI = 4 MHz */
+ default:
+ break;
+ }
+ }
+
+ /* Main PLL configuration and activation */
+ if(status != ERROR)
+ {
+ /* Calculate the new PLL output frequency */
+ pllfreq = UTILS_GetPLLOutputFrequency(__LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), msi_range),
+ UTILS_PLLInitStruct);
+
+ /* Enable MSI if not enabled */
+ if(LL_RCC_MSI_IsReady() != 1U)
+ {
+ LL_RCC_MSI_Enable();
+ while ((LL_RCC_MSI_IsReady() != 1U))
+ {
+ /* Wait for MSI ready */
+ }
+ }
+
+ /* Configure PLL */
+ LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
+ UTILS_PLLInitStruct->PLLR);
+
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+ /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
+ if(pllfreq > 80000000U)
+ {
+ if(UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1)
+ {
+ UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
+ hpre = LL_RCC_SYSCLK_DIV_2;
+ }
+ }
+#endif
+ /* Enable PLL and switch system clock to PLL */
+ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+ /* Apply definitive AHB prescaler value if necessary */
+ if((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1))
+ {
+ /* Set FLASH latency to highest latency */
+ status = LL_SetFlashLatency(pllfreq);
+ if(status == SUCCESS)
+ {
+ UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
+ LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ LL_SetSystemCoreClock(pllfreq);
+ }
+ }
+#endif
+ }
+ }
+ else
+ {
+ /* Current PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
+ * @note The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
+ * @note Function is based on the following formula:
+ * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
+ * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
+ * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
+ * - PLLR: ensure that max frequency at 120000000 Hz is reach (PLLVCO_output / PLLR)
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Max frequency configuration done
+ * - ERROR: Max frequency configuration not done
+ */
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status;
+ uint32_t pllfreq;
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+ uint32_t hpre = LL_RCC_SYSCLK_DIV_1; /* Set default value */
+#endif
+
+ /* Check if one of the PLL is enabled */
+ if(UTILS_PLL_IsBusy() == SUCCESS)
+ {
+ /* Calculate the new PLL output frequency */
+ pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
+
+ /* Enable HSI if not enabled */
+ if(LL_RCC_HSI_IsReady() != 1U)
+ {
+ LL_RCC_HSI_Enable();
+ while (LL_RCC_HSI_IsReady() != 1U)
+ {
+ /* Wait for HSI ready */
+ }
+ }
+
+ /* Configure PLL */
+ LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
+ UTILS_PLLInitStruct->PLLR);
+
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+ /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
+ if(pllfreq > 80000000U)
+ {
+ if(UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1)
+ {
+ UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
+ hpre = LL_RCC_SYSCLK_DIV_2;
+ }
+ }
+#endif
+ /* Enable PLL and switch system clock to PLL */
+ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+ /* Apply definitive AHB prescaler value if necessary */
+ if((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1))
+ {
+ /* Set FLASH latency to highest latency */
+ status = LL_SetFlashLatency(pllfreq);
+ if(status == SUCCESS)
+ {
+ UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
+ LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ LL_SetSystemCoreClock(pllfreq);
+ }
+ }
+#endif
+ }
+ else
+ {
+ /* Current PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief This function configures system clock with HSE as clock source of the PLL
+ * @note The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
+ * @note Function is based on the following formula:
+ * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
+ * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSE frequency / PLLM)
+ * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
+ * - PLLR: ensure that max frequency at 120000000 Hz is reached (PLLVCO_output / PLLR)
+ * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
+ * @param HSEBypass This parameter can be one of the following values:
+ * @arg @ref LL_UTILS_HSEBYPASS_ON
+ * @arg @ref LL_UTILS_HSEBYPASS_OFF
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Max frequency configuration done
+ * - ERROR: Max frequency configuration not done
+ */
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status;
+ uint32_t pllfreq;
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+ uint32_t hpre = 0U; /* Set default value */
+#endif
+
+ /* Check the parameters */
+ assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
+ assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
+
+ /* Check if one of the PLL is enabled */
+ if(UTILS_PLL_IsBusy() == SUCCESS)
+ {
+ /* Calculate the new PLL output frequency */
+ pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
+
+ /* Enable HSE if not enabled */
+ if(LL_RCC_HSE_IsReady() != 1U)
+ {
+ /* Check if need to enable HSE bypass feature or not */
+ if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
+ {
+ LL_RCC_HSE_EnableBypass();
+ }
+ else
+ {
+ LL_RCC_HSE_DisableBypass();
+ }
+
+ /* Enable HSE */
+ LL_RCC_HSE_Enable();
+ while (LL_RCC_HSE_IsReady() != 1U)
+ {
+ /* Wait for HSE ready */
+ }
+ }
+
+ /* Configure PLL */
+ LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
+ UTILS_PLLInitStruct->PLLR);
+
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+ /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
+ if(pllfreq > 80000000U)
+ {
+ if(UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1)
+ {
+ UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
+ hpre = LL_RCC_SYSCLK_DIV_2;
+ }
+ }
+#endif
+ /* Enable PLL and switch system clock to PLL */
+ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+
+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+ /* Apply definitive AHB prescaler value if necessary */
+ if((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1))
+ {
+ /* Set FLASH latency to highest latency */
+ status = LL_SetFlashLatency(pllfreq);
+ if(status == SUCCESS)
+ {
+ UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
+ LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ LL_SetSystemCoreClock(pllfreq);
+ }
+ }
+#endif
+ }
+ else
+ {
+ /* Current PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup UTILS_LL_Private_Functions
+ * @{
+ */
+/**
+ * @brief Function to check that PLL can be modified
+ * @param PLL_InputFrequency PLL input frequency (in Hz)
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @retval PLL output frequency (in Hz)
+ */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
+{
+ uint32_t pllfreq;
+
+ /* Check the parameters */
+ assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
+ assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
+ assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR));
+
+ /* Check different PLL parameters according to RM */
+ /* - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz. */
+ pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_PLLCFGR_PLLM_Pos) + 1U));
+ assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
+
+ /* - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz.*/
+ pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
+ assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
+
+ /* - PLLR: ensure that max frequency at 120000000 Hz is reached */
+ pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U);
+ assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
+
+ return pllfreq;
+}
+
+/**
+ * @brief Function to check that PLL can be modified
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: PLL modification can be done
+ * - ERROR: PLL is busy
+ */
+static ErrorStatus UTILS_PLL_IsBusy(void)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check if PLL is busy*/
+ if(LL_RCC_PLL_IsReady() != 0U)
+ {
+ /* PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+#if defined(RCC_PLLSAI1_SUPPORT)
+ /* Check if PLLSAI1 is busy*/
+ if(LL_RCC_PLLSAI1_IsReady() != 0U)
+ {
+ /* PLLSAI1 configuration cannot be modified */
+ status = ERROR;
+ }
+#endif /*RCC_PLLSAI1_SUPPORT*/
+#if defined(RCC_PLLSAI2_SUPPORT)
+
+ /* Check if PLLSAI2 is busy*/
+ if(LL_RCC_PLLSAI2_IsReady() != 0U)
+ {
+ /* PLLSAI2 configuration cannot be modified */
+ status = ERROR;
+ }
+#endif /*RCC_PLLSAI2_SUPPORT*/
+
+ return status;
+}
+
+/**
+ * @brief Function to enable PLL and switch system clock to PLL
+ * @param SYSCLK_Frequency SYSCLK frequency
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: No problem to switch system to PLL
+ * - ERROR: Problem to switch system to PLL
+ */
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ uint32_t hclk_frequency;
+
+ assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
+ assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
+ assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
+
+ /* Calculate HCLK frequency */
+ hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
+
+ /* Increasing the number of wait states because of higher CPU frequency */
+ if(SystemCoreClock < hclk_frequency)
+ {
+ /* Set FLASH latency to highest latency */
+ status = LL_SetFlashLatency(hclk_frequency);
+ }
+
+ /* Update system clock configuration */
+ if(status == SUCCESS)
+ {
+ /* Enable PLL */
+ LL_RCC_PLL_Enable();
+ LL_RCC_PLL_EnableDomain_SYS();
+ while (LL_RCC_PLL_IsReady() != 1U)
+ {
+ /* Wait for PLL ready */
+ }
+
+ /* Sysclk activation on the main PLL */
+ LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+ while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+ {
+ /* Wait for system clock switch to PLL */
+ }
+
+ /* Set APB1 & APB2 prescaler*/
+ LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
+ LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
+ }
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if(SystemCoreClock > hclk_frequency)
+ {
+ /* Set FLASH latency to lowest latency */
+ status = LL_SetFlashLatency(hclk_frequency);
+ }
+
+ /* Update SystemCoreClock variable */
+ if(status == SUCCESS)
+ {
+ LL_SetSystemCoreClock(hclk_frequency);
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/STMGyro.ioc b/STMGyro.ioc
index 399f59e..001d463 100644
--- a/STMGyro.ioc
+++ b/STMGyro.ioc
@@ -5,16 +5,25 @@ KeepUserPlacement=false
Mcu.Family=STM32L4
Mcu.IP0=NVIC
Mcu.IP1=RCC
-Mcu.IP2=SYS
-Mcu.IPNb=3
+Mcu.IP2=SPI1
+Mcu.IP3=SYS
+Mcu.IP4=TIM1
+Mcu.IP5=USART1
+Mcu.IPNb=6
Mcu.Name=STM32L432K(B-C)Ux
Mcu.Package=UFQFPN32
Mcu.Pin0=PA1
Mcu.Pin1=PA2
+Mcu.Pin10=VP_TIM1_VS_ClockSourceINT
Mcu.Pin2=PA3
-Mcu.Pin3=PB0
-Mcu.Pin4=VP_SYS_VS_Systick
-Mcu.PinsNb=5
+Mcu.Pin3=PA5
+Mcu.Pin4=PA6
+Mcu.Pin5=PA7
+Mcu.Pin6=PB0
+Mcu.Pin7=PA9
+Mcu.Pin8=PA10
+Mcu.Pin9=VP_SYS_VS_Systick
+Mcu.PinsNb=11
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32L432KCUx
@@ -28,8 +37,11 @@ NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SPI1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true
+NVIC.TIM1_UP_TIM16_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
PA1.GPIOParameters=PinState,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP
PA1.GPIO_Label=CS1
@@ -38,6 +50,8 @@ PA1.GPIO_PuPd=GPIO_NOPULL
PA1.Locked=true
PA1.PinState=GPIO_PIN_SET
PA1.Signal=GPIO_Output
+PA10.Mode=Asynchronous
+PA10.Signal=USART1_RX
PA2.GPIOParameters=PinState,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP
PA2.GPIO_Label=CS2
PA2.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_PP
@@ -52,6 +66,14 @@ PA3.GPIO_PuPd=GPIO_NOPULL
PA3.Locked=true
PA3.PinState=GPIO_PIN_SET
PA3.Signal=GPIO_Output
+PA5.Mode=Full_Duplex_Master
+PA5.Signal=SPI1_SCK
+PA6.Mode=Full_Duplex_Master
+PA6.Signal=SPI1_MISO
+PA7.Mode=Full_Duplex_Master
+PA7.Signal=SPI1_MOSI
+PA9.Mode=Asynchronous
+PA9.Signal=USART1_TX
PB0.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP
PB0.GPIO_Label=RESET
PB0.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
@@ -86,7 +108,7 @@ ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=STM32CubeIDE
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=true
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-false,3-MX_SPI1_Init-SPI1-false-LL-true,4-MX_USART1_UART_Init-USART1-false-LL-true,5-MX_TIM1_Init-TIM1-false-LL-true
RCC.ADCFreq_Value=80000000
RCC.AHBFreq_Value=80000000
RCC.APB1Freq_Value=80000000
@@ -133,7 +155,24 @@ RCC.USBFreq_Value=80000000
RCC.VCOInputFreq_Value=16000000
RCC.VCOOutputFreq_Value=160000000
RCC.VCOSAI1OutputFreq_Value=160000000
+SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_8
+SPI1.CalculateBaudRate=10.0 MBits/s
+SPI1.DataSize=SPI_DATASIZE_8BIT
+SPI1.Direction=SPI_DIRECTION_2LINES
+SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,DataSize,BaudRatePrescaler
+SPI1.Mode=SPI_MODE_MASTER
+SPI1.VirtualType=VM_MASTER
+TIM1.IPParameters=Prescaler,Period
+TIM1.Period=99
+TIM1.Prescaler=799
+USART1.BaudRate=460800
+USART1.IPParameters=VirtualMode-Asynchronous,BaudRate,Mode,OverSampling
+USART1.Mode=MODE_TX
+USART1.OverSampling=UART_OVERSAMPLING_16
+USART1.VirtualMode-Asynchronous=VM_ASYNC
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+VP_TIM1_VS_ClockSourceINT.Mode=Internal
+VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT
board=custom
isbadioc=false