74 lines
3.3 KiB
Batchfile
74 lines
3.3 KiB
Batchfile
/*----------------------------------------------------------------------------*/
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/* Linker Settings */
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--retain="*(.intvecs)"
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--stack_size=0x700
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/*----------------------------------------------------------------------------*/
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/* Section Configuration */
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-ldsplib.ae64P
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-llibmmwavealg_xwr16xx.ae674
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-lmathlib.ae674
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-llibsoc_xwr16xx.ae674
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SECTIONS
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{
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systemHeap : {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
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.l2data : {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
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/* HSSRAM has output data from processing chain running on DSP */
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.demoSharedMem > HSRAM
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/* L3SRAM has code that is overlaid with data, so data must be
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marked uninitialized. Application can initialize this section
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using _L3data_* symbols defined below. Code should be written carefully as
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these are linker symbols (see for example http://e2e.ti.com/support/development_tools/compiler/f/343/t/92002 ):
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extern far uint8_t _L3data_start; // the type here does not matter
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extern far uint8_t _L3data_size; // the type here does not matter
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memset((void *)_symval(&_L3data_start), 0, (uint32_t) _symval(&_L3data_size));
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*/
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.l3data: type=NOINIT, start(_L3data_start), size(_L3data_size), load=L3SRAM PAGE 1
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/* Bootloader cannot load L1DSRAM, make sure to mark as NOINIT */
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.l1data : type=NOINIT, load=L1DSRAM
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/* Currently bootloader does not allow loading in L1PSRAM because of supporting
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low power. Below fast code is loaded in L3SRAM but run from L1PSRAM. The copy-in
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is called during initialization phase and copy-out is not used but can be added when
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supporting low-power mode (where L1 contents are not retained).
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*/
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.fastCode:
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{
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dsplib.ae64P(.text)
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libmmwavealg_xwr16xx.ae674(.text)
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mathlib.ae674(.text)
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//dss_data_path.oe674 (.text:MmwDemo_interFrameProcessing)
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/*dss_data_path.oe674 (.text:MmwDemo_processChirp)*/
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//dss_data_path.oe674 (.text:MmwDemo_interChirpProcessing)
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//dss_data_path.oe674 (.text:MmwDemo_XYestimation)
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//dss_data_path.oe674 (.text:MmwDemo_cfarPeakGrouping)
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//dss_data_path.oe674 (.text:MmwDemo_cfarPeakGroupingCfarQualified)
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//dss_main.oe674 (.text:MmwDemo_dssDataPathProcessEvents)
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/* Below may be risky to expose hence currently hiding */
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// libosal_xwr16xx.ae674 (.text:SemaphoreP_pend)
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// libosal_xwr16xx.ae674 (.text:SemaphoreP_post)
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} load=L3SRAM PAGE 0, run=L1PSRAM PAGE 0, table(_MmwDemo_fastCode_L1PSRAM_copy_table, compression=off)
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/* This is auto generated by linker related to copy table above */
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.ovly > L2SRAM_UMAP0 | L2SRAM_UMAP1
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/* Overlay one-time/init-time (and non-critical in cycles) with L3 data,
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will be erased during data path processing. Note do not put any
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code that is required related to start/stop/reconfig processing */
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.overlay:
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{
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libsoc_xwr16xx.ae674 (.text:SOC_init)
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dss_main.oe674 (.text:MmwDemo_dssInitTask)
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dss_main.oe674 (.text:main)
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//dss_data_path.oe674 (.text:MmwDemo_dataPathInitEdma)
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} > L3SRAM PAGE 0
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}
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/*----------------------------------------------------------------------------*/
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