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Максим Шишов
2021-04-07 10:53:34 +03:00
commit 44b43036b5
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mmw_dss_16xx/.ccsproject Normal file
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/*
* Copyright (c) 2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#define L1P_CACHE_SIZE (16*1024)
#define L1D_CACHE_SIZE (16*1024)
MEMORY
{
PAGE 0:
#if (L1P_CACHE_SIZE < 0x8000)
L1PSRAM: o = 0x00E00000, l = (0x00008000 - L1P_CACHE_SIZE)
#endif
#if (L1D_CACHE_SIZE < 0x8000)
L1DSRAM: o = 0x00F00000, l = (0x00008000 - L1D_CACHE_SIZE)
#endif
L2SRAM_UMAP1: o = 0x007E0000, l = 0x00020000
L2SRAM_UMAP0: o = 0x00800000, l = 0x00020000
L3SRAM: o = 0x20000000, l = MMWAVE_L3RAM_SIZE
HSRAM: o = 0x21080000, l = 0x8000
/* PAGEs 1 and onwards are for overlay purposes for memory optimization.
Some examples:
1. Overlay one-time only text with uninitialized data.
2. Overlay L1PSRAM data path processing fast code and use copy tables
to page in (before entering data path) and out of L1PSRAM (when entering
sleep/low power).
*/
PAGE 1:
L3SRAM: o = 0x20000000, l = MMWAVE_L3RAM_SIZE
}
/* Set L1D, L1P and L2 Cache Sizes */
ti_sysbios_family_c64p_Cache_l1dSize = L1D_CACHE_SIZE;
ti_sysbios_family_c64p_Cache_l1pSize = L1P_CACHE_SIZE;
ti_sysbios_family_c64p_Cache_l2Size = 0;
SECTIONS
{
/* hard addresses forces vecs to be allocated there */
.vecs: {. = align(32); } > 0x007E0000
/* Allocate data preferentially in one UMAP and code (.text) in another,
this can improve performance due to simultaneous misses from L1P
and L1D caches to L2 SRAM, for more information see C674 Megamodule
User Guide section "Level 2 Memory Architecture".
The linker notation "X >> Y | Z" indicates section X is first allocated in Y
and allowed to overflow into Z and can be split from Y to Z.
The linker notation "X > Y | Z" indicates section X is first allocated in Y
and allowed to overflow into Z and cannot be split from Y to Z. Some sections
like bss are not allowed to be split so > notation is used for them */
.fardata: {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
.const: {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
.switch: {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
.cio: {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
.data: {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
.rodata: {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
.bss: {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
.neardata: {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
.stack: {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
.cinit: {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
.far: {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
.text: {} >> L2SRAM_UMAP1 | L2SRAM_UMAP0
}

186
mmw_dss_16xx/dss_main.c Normal file
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/* Standard Include Files. */
#include <stdint.h>
#include <stdlib.h>
#include <stddef.h>
#include <string.h>
#include <stdio.h>
/* BIOS/XDC Include Files. */
#include <xdc/std.h>
#include <xdc/cfg/global.h>
#include <xdc/runtime/IHeap.h>
#include <xdc/runtime/System.h>
#include <xdc/runtime/Error.h>
#include <xdc/runtime/Memory.h>
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Event.h>
#include <ti/sysbios/knl/Semaphore.h>
#include <ti/sysbios/knl/Clock.h>
#include <ti/sysbios/heaps/HeapBuf.h>
#include <ti/sysbios/heaps/HeapMem.h>
#include <ti/sysbios/knl/Event.h>
#include <ti/sysbios/family/c64p/Cache.h>
#include <ti/sysbios/family/c64p/Hwi.h>
#include <ti/sysbios/family/c64p/EventCombiner.h>
/* Mailbox Driver: */
#include <ti/drivers/mailbox/mailbox.h>
#include <ti/drivers/mailbox/include/mailbox_internal.h>
#include <ti/drivers/soc/soc.h>
#include "ti/utils/testlogger/logger.h"
SOC_Handle socHandle;
Mbox_Handle peerMailbox;
#define BIG_MSG_SIZE 3
#define BUFFER_SIZE 128
uint8_t buffer[BUFFER_SIZE];
volatile uint8_t mboxProcToken = 0;
void MmwDemo_sleep(void)
{
/* issue WFI (Wait For Interrupt) instruction */
asm(" IDLE ");
}
static uint32_t split(uint8_t *mes){
uint32_t i;
for(i = 0; i < BIG_MSG_SIZE; i++){
if(mes[i] == '\n') break;
}
i++;
return i;
}
static int32_t mboxWrite_ch0(uint8_t message, int32_t len)
{
int32_t retVal = -1;
retVal = Mailbox_write(peerMailbox, &message, len);
if (retVal == len)
{
retVal = 0;
}
return retVal;
}
static void mboxReadProc_ch0()
{
uint8_t message[BIG_MSG_SIZE];
uint8_t id;
int32_t retVal = 0;
int32_t ret = 0;
/* Read the message from the peer mailbox: We are not trying to protect the read
* from the peer mailbox because this is only being invoked from a single thread */
retVal = Mailbox_read(peerMailbox, message, sizeof(message)/sizeof(uint8_t));
if (retVal < 0)
{
/* Error: Unable to read the message. Setup the error code and return values */
System_printf("Error read dss\n");
return;
}
else
{
Mailbox_readFlush (peerMailbox);
id = message[1];
if(message[0] == 0) {
ret = mboxWrite_ch0(buffer[id], 1);
} else if(message[0] == 1) {
buffer[id] = message[2];
}
if (ret != 0)
{
System_printf ("Error: Mailbox send message failed \n");
}
/* We are done: There are no messages available from the peer execution domain. */
return;
}
}
void mboxCallback_ch0 (Mbox_Handle handle, Mailbox_Type peer)
{
/* Message has been received from the peer endpoint. */
mboxProcToken = 1;
}
void mBox(UArg a0, UArg a1)
{
while(true){
if (mboxProcToken == 1)
{
mboxProcToken = 0;
/* If the mailbox has a message and the frame processing task has finished. */
mboxReadProc_ch0();
}
}
}
void InitTask(UArg arg0, UArg arg1)
{
int32_t errCode;
Mailbox_Config cfg;
Task_Params taskParams;
Mailbox_init(MAILBOX_TYPE_DSS);
if(Mailbox_Config_init(&cfg) < 0)
{
System_printf ("Error: Mailbox init failed\n");
return;
}
/* Setup the configuration: */
cfg.chType = MAILBOX_CHTYPE_MULTI;
cfg.chId = MAILBOX_CH_ID_0;
cfg.writeMode = MAILBOX_MODE_BLOCKING;
cfg.readMode = MAILBOX_MODE_CALLBACK;
cfg.readCallback = &mboxCallback_ch0;
peerMailbox = Mailbox_open(MAILBOX_TYPE_MSS, &cfg, &errCode);
if (peerMailbox == NULL)
{
System_printf ("Error: Mailbox open failed 0\n");
return;
}
Task_Params_init(&taskParams);
taskParams.priority = 2;
taskParams.stackSize = 3 * 1024;
Task_create(mBox, &taskParams, NULL);
return;
}
int main (void)
{
Task_Params taskParams;
SOC_Cfg socCfg;
int32_t errCode;
/* Initialize the SOC confiugration: */
memset ((void *)&socCfg, 0, sizeof(SOC_Cfg));
/* Populate the SOC configuration: We are bypassing the clock initialization
* in the unit test here since the MSS unit test is doing this. */
socCfg.clockCfg = SOC_SysClock_BYPASS_INIT;
/* Initialize the SOC Module: */
socHandle = SOC_init (&socCfg, &errCode);
if (socHandle == NULL)
{
System_printf ("Error: SOC Module Initialization failed [Error code %d]\n", errCode);
return -1;
}
/* Initialize the Task Parameters. */
Task_Params_init(&taskParams);
taskParams.stackSize = 4*1024;
taskParams.priority = 4;
Task_create(InitTask, &taskParams, NULL);
/* Start BIOS */
BIOS_start();
return 0;
}

91
mmw_dss_16xx/dss_mmw.cfg Normal file
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/*
* Copyright 2016 by Texas Instruments Incorporated.
*
* All rights reserved. Property of Texas Instruments Incorporated.
* Restricted rights to use, duplicate or disclose this code are
* granted through contract.
*
*/
environment['xdc.cfg.check.fatal'] = 'false';
/********************************************************************
************************** BIOS Modules ****************************
********************************************************************/
var Memory = xdc.useModule('xdc.runtime.Memory');
var BIOS = xdc.useModule('ti.sysbios.BIOS');
var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
var Task = xdc.useModule('ti.sysbios.knl.Task');
var Idle = xdc.useModule('ti.sysbios.knl.Idle');
var SEM = xdc.useModule('ti.sysbios.knl.Semaphore');
var Event = xdc.useModule('ti.sysbios.knl.Event');
var Hwi = xdc.useModule('ti.sysbios.family.c64p.Hwi');
var System = xdc.useModule('xdc.runtime.System');
var SysStd = xdc.useModule('xdc.runtime.SysStd');
var EventCombiner = xdc.useModule('ti.sysbios.family.c64p.EventCombiner');
var Load = xdc.useModule('ti.sysbios.utils.Load');
System.SupportProxy = SysStd;
/*
* Enable Event Groups here and registering of ISR for specific GEM INTC is done
* using EventCombiner_dispatchPlug() and Hwi_eventMap() APIs
*/
EventCombiner.eventGroupHwiNum[0] = 7;
EventCombiner.eventGroupHwiNum[1] = 8;
EventCombiner.eventGroupHwiNum[2] = 9;
EventCombiner.eventGroupHwiNum[3] = 10;
/* Default Heap Creation: Local L2 memory */
var heapMemParams = new HeapMem.Params();
heapMemParams.size = 20*1024;
heapMemParams.sectionName = "systemHeap";
Program.global.heap0 = HeapMem.create(heapMemParams);
Memory.defaultHeapInstance = Program.global.heap0;
/* Enable BIOS Task Scheduler */
BIOS.taskEnabled = true;
/* do not call update for load - Application will call it at inter-frame boundary */
Load.updateInIdle = false;
/* Install idle function to sleep the DSP (using IDLE instruction). Note above
Load.updateInIdle is false which allows to sleep the DSP in idle.
Also, no other book-keeping etc functions should be installed in the idle thread */
Idle.addFunc('&MmwDemo_sleep');
/*
var Defaults = xdc.useModule('xdc.runtime.Defaults');
var Log = xdc.useModule('xdc.runtime.Log');
var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
var loggerBufParams = new LoggerBuf.Params();
loggerBufParams.numEntries = 1024;
var logger0 = LoggerBuf.create(loggerBufParams);
Defaults.common$.logger = logger0;
var Diags = xdc.useModule('xdc.runtime.Diags');
Hwi.common$.logger = logger0;
Hwi.common$.diags_USER1 = Diags.RUNTIME_ON;
Hwi.common$.diags_USER2 = Diags.RUNTIME_ON;
*/
/*
Task.common$.diags_USER1 = Diags.ALWAYS_ON;
Task.common$.diags_USER2 = Diags.ALWAYS_ON;
*/
//Program.sectMap[".vecs"] = "VECTORS";
/* Some options to reduce BIOS code and data size, see BIOS User Guide section
"Minimizing the Application Footprint" */
System.maxAtexitHandlers = 0;
BIOS.swiEnabled = false; /* We don't use SWIs */
BIOS.libType = BIOS.LibType_Custom;
/* Compile BIOS with size optimization at level 0.
Note this line must be after "BIOS.libType = " statements (which overrides customCCOpts)
to take effect. */
BIOS.customCCOpts += "-ms0";
//print(BIOS.customCCOpts);
Task.defaultStackSize = 1500;
Task.idleTaskStackSize = 800;
Program.stack = 1048; /* for isr context */
var Text = xdc.useModule('xdc.runtime.Text');
Text.isLoaded = false;

73
mmw_dss_16xx/dss_mmw_linker.cmd Normal file
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/*----------------------------------------------------------------------------*/
/* Linker Settings */
--retain="*(.intvecs)"
--stack_size=0x700
/*----------------------------------------------------------------------------*/
/* Section Configuration */
-ldsplib.ae64P
-llibmmwavealg_xwr16xx.ae674
-lmathlib.ae674
-llibsoc_xwr16xx.ae674
SECTIONS
{
systemHeap : {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
.l2data : {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
/* HSSRAM has output data from processing chain running on DSP */
.demoSharedMem > HSRAM
/* L3SRAM has code that is overlaid with data, so data must be
marked uninitialized. Application can initialize this section
using _L3data_* symbols defined below. Code should be written carefully as
these are linker symbols (see for example http://e2e.ti.com/support/development_tools/compiler/f/343/t/92002 ):
extern far uint8_t _L3data_start; // the type here does not matter
extern far uint8_t _L3data_size; // the type here does not matter
memset((void *)_symval(&_L3data_start), 0, (uint32_t) _symval(&_L3data_size));
*/
.l3data: type=NOINIT, start(_L3data_start), size(_L3data_size), load=L3SRAM PAGE 1
/* Bootloader cannot load L1DSRAM, make sure to mark as NOINIT */
.l1data : type=NOINIT, load=L1DSRAM
/* Currently bootloader does not allow loading in L1PSRAM because of supporting
low power. Below fast code is loaded in L3SRAM but run from L1PSRAM. The copy-in
is called during initialization phase and copy-out is not used but can be added when
supporting low-power mode (where L1 contents are not retained).
*/
.fastCode:
{
dsplib.ae64P(.text)
libmmwavealg_xwr16xx.ae674(.text)
mathlib.ae674(.text)
//dss_data_path.oe674 (.text:MmwDemo_interFrameProcessing)
/*dss_data_path.oe674 (.text:MmwDemo_processChirp)*/
//dss_data_path.oe674 (.text:MmwDemo_interChirpProcessing)
//dss_data_path.oe674 (.text:MmwDemo_XYestimation)
//dss_data_path.oe674 (.text:MmwDemo_cfarPeakGrouping)
//dss_data_path.oe674 (.text:MmwDemo_cfarPeakGroupingCfarQualified)
//dss_main.oe674 (.text:MmwDemo_dssDataPathProcessEvents)
/* Below may be risky to expose hence currently hiding */
// libosal_xwr16xx.ae674 (.text:SemaphoreP_pend)
// libosal_xwr16xx.ae674 (.text:SemaphoreP_post)
} load=L3SRAM PAGE 0, run=L1PSRAM PAGE 0, table(_MmwDemo_fastCode_L1PSRAM_copy_table, compression=off)
/* This is auto generated by linker related to copy table above */
.ovly > L2SRAM_UMAP0 | L2SRAM_UMAP1
/* Overlay one-time/init-time (and non-critical in cycles) with L3 data,
will be erased during data path processing. Note do not put any
code that is required related to start/stop/reconfig processing */
.overlay:
{
libsoc_xwr16xx.ae674 (.text:SOC_init)
dss_main.oe674 (.text:MmwDemo_dssInitTask)
dss_main.oe674 (.text:main)
//dss_data_path.oe674 (.text:MmwDemo_dataPathInitEdma)
} > L3SRAM PAGE 0
}
/*----------------------------------------------------------------------------*/