98 lines
4.0 KiB
Batchfile
98 lines
4.0 KiB
Batchfile
/*
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* Copyright (c) 2016, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define L1P_CACHE_SIZE (16*1024)
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#define L1D_CACHE_SIZE (16*1024)
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MEMORY
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{
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PAGE 0:
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#if (L1P_CACHE_SIZE < 0x8000)
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L1PSRAM: o = 0x00E00000, l = (0x00008000 - L1P_CACHE_SIZE)
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#endif
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#if (L1D_CACHE_SIZE < 0x8000)
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L1DSRAM: o = 0x00F00000, l = (0x00008000 - L1D_CACHE_SIZE)
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#endif
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L2SRAM_UMAP1: o = 0x007E0000, l = 0x00020000
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L2SRAM_UMAP0: o = 0x00800000, l = 0x00020000
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L3SRAM: o = 0x20000000, l = MMWAVE_L3RAM_SIZE
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HSRAM: o = 0x21080000, l = 0x8000
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/* PAGEs 1 and onwards are for overlay purposes for memory optimization.
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Some examples:
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1. Overlay one-time only text with uninitialized data.
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2. Overlay L1PSRAM data path processing fast code and use copy tables
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to page in (before entering data path) and out of L1PSRAM (when entering
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sleep/low power).
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*/
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PAGE 1:
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L3SRAM: o = 0x20000000, l = MMWAVE_L3RAM_SIZE
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}
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/* Set L1D, L1P and L2 Cache Sizes */
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ti_sysbios_family_c64p_Cache_l1dSize = L1D_CACHE_SIZE;
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ti_sysbios_family_c64p_Cache_l1pSize = L1P_CACHE_SIZE;
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ti_sysbios_family_c64p_Cache_l2Size = 0;
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SECTIONS
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{
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/* hard addresses forces vecs to be allocated there */
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.vecs: {. = align(32); } > 0x007E0000
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/* Allocate data preferentially in one UMAP and code (.text) in another,
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this can improve performance due to simultaneous misses from L1P
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and L1D caches to L2 SRAM, for more information see C674 Megamodule
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User Guide section "Level 2 Memory Architecture".
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The linker notation "X >> Y | Z" indicates section X is first allocated in Y
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and allowed to overflow into Z and can be split from Y to Z.
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The linker notation "X > Y | Z" indicates section X is first allocated in Y
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and allowed to overflow into Z and cannot be split from Y to Z. Some sections
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like bss are not allowed to be split so > notation is used for them */
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.fardata: {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
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.const: {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
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.switch: {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
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.cio: {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
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.data: {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
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.rodata: {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
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.bss: {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
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.neardata: {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
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.stack: {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
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.cinit: {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
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.far: {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
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.text: {} >> L2SRAM_UMAP1 | L2SRAM_UMAP0
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}
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